Virtual Machine Support for Many-Core Architectures: Decoupling Abstract from Concrete Concurrency Models

Virtual Machine Support for Many-Core Architectures
Decoupling Abstract from Concrete Concurrency Models
Stefan Marr
VrijeUniversiteitBrussel
PLACES Workshop, 22nd March 2009, York, UK

Agenda
Motivation
Concurrency Support for VM Instruction Sets
Methodology
Combining Different Models
Investigate Tradeoffs
Research Platform
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VM Support forMany-CoreArchitectures

The Free Lunch Is Over
Many Core ≠ Many Core
Homogeneous vs. heterogeneous designs
Different memory and cache patterns/partitions
Different concrete concurrency models
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1. Motivation
Cell Broadband Engine
- 1 PPE, 8 SPE
- bus interconnect
Intel Larrabee
- up to 48 cores (IA32)
- bus interconnect, virtual shared memory
Tilera TILE64
- 64 cores (MIPS)
- up to 866 MHz
- virtual shared memory

Abstract Concurrency Models
Broad range of programming models
Shared memory with locking is error-prone/hard
STM and actors still not mainstream
Combinations and new approaches expected
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1. Motivation

Virtual Machines as Abstraction Layer
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1. Motivation
C#
Prolog, …
JVM/CLR/…
Today, concurrency support is very limited!

Concurrency Support for VM Instruction Sets
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Methodology
To develop instruction set with concurrency support
Combination of concurrency models
Guidelines for design decision, tradeoffs
Instruction set design
Application area
General purpose/multi-langVMs like JVM/CLR
Special purpose VMs like DalvikVM
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Combining Different Models
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2. Concurrency Support for VM Instruction Sets

Consider abstract models separately
Distil basic concepts/instructions
Analyze design space for ISA
Stepwise integration
Based on existing ideas

Tradeoffs to be Considered
Model combinations
Different types/approaches of integration
Instruction set size
Design space with respect to #instructions
Instruction set type
Opcode vs. higher level representation
…?
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2. Concurrency Support for VM Instruction Sets

Research Platform
Requirements for an appropriate VM
Portable, support for Linux and MIPS
Available STM and Actors languages/libraries
Unused instructions in bytecode/opcode set
Easy to adapt just-in-time compiler
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Tilera TILE64™
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3. Research Platform

64 cores, up to 866 MHz
MIPS derived 32-bit VLIW ISA
L1 cache/core: 8KB instructions, 8KB data
L2 cache/core: 64KB
4 DDR2 RAM controller

Choosing a VM as Research Platform
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3. Research Platform

Discussion
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VM Support forMany-CoreArchitectures
Methodology
Tradeoffs
Concurrency Model Integration
Research Platform
Instruction Set Design