Vhd lhigh2003

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Vhd lhigh2003

  1. 1. VHDL<br />Prepared by:<br />Gaurav<br />
  2. 2. Outline….. <br />Brief Overview of VHDL<br />Structural elements of VHDL<br />Entity<br />Architecture<br />Signals<br />Data Types & Operator VHDL<br />Design Methodology<br />Behavioral <br />Structural<br />Dataflow <br />
  3. 3. Brief Overview of VHDL<br />• VHDL<br />... stands forVeryHighSpeedIntegratedCircuit<br />Hardware<br />Description<br />Language<br /><ul><li>can be translated into an actual hardware implementation
  4. 4. allows complex digital circuits to be easily created
  5. 5. In VHDL, strong understanding of your code is more important than syntax & style.</li></li></ul><li>Structural Elements<br />• Entity<br /> • Interface<br /> • Example: Ports, I/O<br />• Architecture <br /> • Implementation<br /> • Behavior<br /> •Function<br />Vhdl model <br />
  6. 6. ENTITY<br />provides a name to the component <br />contains the port definitions in the interface list<br />can contain some generic definitions which can be used to override default values<br />entity identifier is <br /> generic interface_list;<br /> port interface_list;<br /> declarations<br />begin<br />statements<br />end [entity] [identifier];<br />
  7. 7. Example <br /> And<br />a<br />c<br />b<br />2 input And gate<br />1. entity and is<br /> port (a, b: in bit; c : out bit);<br /> end and;<br />2. ENTITY and IS<br /> PORT( a, b : IN std_logic; c: OUT std_logic );<br /> END and;<br />
  8. 8. Architecture<br />encapsulates the behavior and timing information<br />contains a number of concurrent statements<br />there can be multiple architecture bodies for a given entity<br /> architecture identifier of entity_name is<br />declarations<br /> begin<br />statements<br /> end [architecture] [identifier];<br />
  9. 9. Example <br /> And<br />a<br />c<br />b<br />2 input And gate<br />architecture and_arch of and is;<br />begin;<br />c<= a and b;<br />end and_arch;<br />
  10. 10. Signals<br /><ul><li>Signals are intermediary ‘ports’ within the architecture
  11. 11. represents wires and storage elements</li></ul>A<br />Xor<br />B<br />sum<br />C<br />D<br />And <br />Or <br />E<br />And <br />Carry <br />F <br />And <br />Circuit diagram of full adder<br />
  12. 12. Data Types<br />Data type<br />Scalar Type<br />Composite Type<br /> Access Type<br />File Type<br />Record<br />Integer<br />Float<br />Array<br />Physical<br />Enumeration<br />
  13. 13. Typical Operators<br />Operators<br />
  14. 14. Design Methodology <br />
  15. 15. Dataflow <br />Concurrent/ Continuously or Combinational Logic<br />To give a signal a concurrent assignment<br />SignalName <= expression;<br />Inputs <br />Outputs <br />Full adder<br />Sum (s)<br />A<br />B<br />Carry out (c)<br />Carry( in)<br />
  16. 16. Dataflow(cont.)<br />A<br />Xor<br />B<br />Sum (s)<br />Carry in (c _in)<br />D<br />And <br />Or <br />E<br />Carry out (c_out)<br />And <br />F <br />And <br />Circuit diagram of full adder<br />
  17. 17. Dataflow(cont.)<br />library ieee;<br />use ieee.std_logic_1164.all;<br />ENTITY fulladder IS<br />PORT ( a, b, c_in : IN BIT; s, c_out : OUT BIT);<br />END fulladder;<br />architecture fulladder_arch of fulladder is<br />begin<br />s<=a xor b xor c;<br />c_out<= (a and b) or (b and c ) or (c and a);<br />end fulladder_arch;<br />
  18. 18. Behavioral <br /><ul><li>The circuit is described by means of Boolean equations and a set of sequential instructions.</li></ul>4 x 1<br />a<br />b<br />x<br />c<br />d<br />s0<br />s1<br />Multiplexer 4 x 1<br />
  19. 19. Behavioral (cont.)<br />ENTITY mux IS<br />PORT ( a, b, c, d : IN BIT;<br />s0, s1 : IN BIT;<br />x, : OUT BIT);<br />END mux;<br />ARCHITECTURE sequential OF mux IS<br />Process (a, b, c, d, s0, s1 )<br />VARIABLE sel : INTEGER;<br />BEGIN<br />IF s0 = ‘0’ and s1 = ‘0’ THEN<br />sel := 0;<br />ELSIF s0 = ‘1’ and s1 = ‘0’ THEN<br />sel := 1;<br />ELSIF s0 = ‘0’ and s1 = ‘0’ THEN<br />sel := 2;<br />ELSE<br />sel := 3;<br />END IF;<br />CASE sel IS<br />WHEN 0 =><br />x <= a;<br />WHEN 1 =><br />x <= b;<br />WHEN 2 =><br />x <= c;<br />WHEN OTHERS =><br />x <= d;<br />END CASE;<br />END PROCESS;<br />END sequential;<br />
  20. 20. Structural<br /><ul><li>The circuit is described as an interconnection of known components.</li></ul>A<br />xor<br />sum<br />B<br />and<br />carry<br />Half adder<br />A<br />Half Adder 1<br />sum<br />Half Adder 2<br />B <br />Carry<br />out<br />Or<br />Carry in<br />Full adder using half adder<br />
  21. 21. Structural (cont.)<br />HALF ADDER (USED FOR FULL ADDER)<br />library ieee;<br />use ieee.std_logic_1164.all;<br />entity HA is<br />port(a,b:in std_logic;s,c:out std_logic);<br />end HA;<br />architecture dataflow of HA is<br />begin<br />s<= a xor b;<br />c<= a and b;<br />end dataflow;<br />library ieee;<br />use ieee.std_logic_1164.all;<br />entity OR2 is<br />port(i1,i2:in std_logic; o:out std_logic);<br />end OR2;<br />architecture dataflow of OR2 is<br />begin<br />o<= i1 or i2;<br />end dataflow;<br />
  22. 22. Structural (cont.)<br />--STRURAL DESCRIPTION OF FULL ADDER<br />library ieee;<br />use ieee.std_logic_1164.all;<br />entity FA is<br />port(x, y, ci :in std_logic;sum,co:out std_logic);<br />end FA;<br />architecture struct of FA is<br />component HA port(a, b: in std_logic;s, c:out std_logic);end component;<br />component OR2 port(i1,i2:in std_logic;o:out std_logic);end component;<br />signal s1,c1,c2:std_logic;<br />begin<br /> HA1:HA port map(x ,y ,s1 ,c1);<br /> HA2:HA port map(s1,ci,sum ,c2);<br /> ORG:OR2 port map(c1,c2,co);<br />end struct;<br />
  23. 23. Advantages of VHDL<br />Standard language<br />Concurrent & sequential statement processing<br />No standard methodology<br />Man machine readable documentation<br />Versatile design support <br />
  24. 24. References<br />[1] Douglas L. Perry, VHDL: “programming by example”, McGraw-Hill, New York, 2002, Fourth Edition.<br />[2] Wai-Kai Chen,” The VLSI Handbook “, CRC Press, USA, Second Edition.<br /> [3] Dr. Cecil alford tsai chi huang, “Digital design vhdl laboratory notes”, 1996, version 1.01, <br /> [4] http://en.wikipedia.org/wiki/Very-large-scale_integration<br /> [5] 1076 IEEE Standard VHDL Language Reference Manual<br />
  25. 25. Questions<br />?<br />

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