Lec 3

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Lec 3

  1. 1. Caching
  2. 2. The Processor-MemoryPerformance Gap
  3. 3. The Memory Problem
  4. 4. Program Locality
  5. 5. Typical Memory Hierarchy:Everything is a Cache forSomething Else
  6. 6. Caches
  7. 7. Cache Organization & Access
  8. 8. Cache Operation
  9. 9. What About Writes?
  10. 10. Cache Write Policies: MajorOptions
  11. 11. Write Policy Trade-offs
  12. 12. Write Miss Policies
  13. 13. Cache Performance
  14. 14. Understanding Cache Misses: The“3 Cs”
  15. 15. Block size
  16. 16. Conflict misses
  17. 17. Fully Associative Cache
  18. 18. Set-associative caches
  19. 19. Replacement Policies
  20. 20. Tuning Basic Cache Parameters:Size, Associativity, Block size
  21. 21. Within a Multi-core Processor
  22. 22. Multi-level Caches
  23. 23. 2-level Cache PerformanceEquations
  24. 24. Multi-level Inclusion
  25. 25. Victim Caches
  26. 26. Pseudo-Associative Caches
  27. 27. Pseudo-Associative Cache“
  28. 28. Skew-Associative Caches
  29. 29. Critical Word First
  30. 30. Non-blocking or Lockup FreeCaches
  31. 31. Potential of Non-blockingCaches
  32. 32. Miss Status Handling Register
  33. 33. MSHR
  34. 34. Non-block Caches: Operation
  35. 35. Prefetching
  36. 36. Software Prefetching
  37. 37. Hardware Prefetching
  38. 38. Simple Sequential Prefetching
  39. 39. Stream Prefetching
  40. 40. Strided Prefetching
  41. 41. Other Ideas in Prefetching
  42. 42. Multi-ported Caches
  43. 43. True Multi-porting
  44. 44. Multi-banked Caches
  45. 45. Sun UltraSPARCT28-bank L2cache

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