System (HW & SW) Architecture RISC/DSP/Array CPU Cores SOC, ASIC, ASSP HW/SW Integration RT and Embedded SW Design Experience Overview and Service Proposal

Technologies Overview CPU Architectures On-chip (SOC/ASIC/ASSP) Internal Bus Optimized Topology DRAM Access Optimization SOC/ASIC/ASSP Secured Architecture for Anti-cloning and Content Protection SW development tools and SW development automation SW modeling of pipelined architectures – bit-accurate, clock-accurate and pipe-accurate Automatic optimization technology for high-level language compiler back-end (Assembler) Real Time and Embedded SW and FW design System Architecture and API design C and Assembler low-level implementation

CPU Architectures

On-chip (SOC/ASIC/ASSP) Internal Bus Optimized Topology

DRAM Access Optimization

SOC/ASIC/ASSP Secured Architecture for Anti-cloning and Content Protection

SW development tools and SW development automation

SW modeling of pipelined architectures – bit-accurate, clock-accurate and pipe-accurate

Automatic optimization technology for high-level language compiler back-end (Assembler)

Real Time and Embedded SW and FW design

System Architecture and API design

C and Assembler low-level implementation

CPU Architecture Experience Background Carmel DSP architecture – Infineon Technologies (I.C.Com) Super scalar architecture – Pipeline and ISA Configurable Long Instruction Word – US Patent 6453407 Concept of C-like Assembly based SW development - US Patent 6314557 Associative Processing Array – NeoMagic Ltd. Silicon size-efficient Array Processing Architecture Billions operations per second below 200MHz operating frequency Massive vector operations – tens to hundreds operations per machine clock Efficient for video/image/neural-networks applications Service Proposal Architecture and Detailed Micro-architecture definition and support of RISC/DSP/Array architectures, including definition of pipeline, ISA (SIMD and MIMD), timing, etc. SW Development Tools definition – concept, language notation, functionality, components behavior and interconnection, etc Simulators Debuggers Compiler & Assembler Linker

Experience Background

Carmel DSP architecture – Infineon Technologies (I.C.Com)

Super scalar architecture – Pipeline and ISA

Configurable Long Instruction Word – US Patent 6453407

Concept of C-like Assembly based SW development - US Patent 6314557

Associative Processing Array – NeoMagic Ltd.

Silicon size-efficient Array Processing Architecture

Billions operations per second below 200MHz operating frequency

Massive vector operations – tens to hundreds operations per machine clock

Efficient for video/image/neural-networks applications

Service Proposal

Architecture and Detailed Micro-architecture definition and support of RISC/DSP/Array architectures, including definition of pipeline, ISA (SIMD and MIMD), timing, etc.

SW Development Tools definition – concept, language notation, functionality, components behavior and interconnection, etc

Simulators

Debuggers

Compiler & Assembler

Linker

On-chip Internal Bus Optimized Topology Experience Background MiMagic6 – NeoMagic Ltd. Advanced bus arbitration - US Patent 6976109 Access-oriented bus layout DVB receiver SOC – CeRoma Ltd. Advanced low-size multi-master bus arbiter Ultra-small DRAM controller with highly efficient bus utilization – over 70% in average Access-oriented multi-layer system bus Service Proposal SOC/ASIC/ASSP Architecture definition – Multimedia (Video, Image, Audio processing) Streaming, Network applications Data traffic efficient bus specification Optimal arbitration Detailed bandwidth analysis and prediction Architecture and Micro-architecture of major functional blocks

Experience Background

MiMagic6 – NeoMagic Ltd.

Advanced bus arbitration - US Patent 6976109

Access-oriented bus layout

DVB receiver SOC – CeRoma Ltd.

Advanced low-size multi-master bus arbiter

Ultra-small DRAM controller with highly efficient bus utilization – over 70% in average

Access-oriented multi-layer system bus

Service Proposal

SOC/ASIC/ASSP Architecture definition – Multimedia (Video, Image, Audio processing) Streaming, Network applications

Data traffic efficient bus specification

Optimal arbitration

Detailed bandwidth analysis and prediction

Architecture and Micro-architecture of major functional blocks

DRAM Access Optimization Experience Background SDRAM Controller – NeoMagic Ultra small – less than 10Kgates Highly efficient – over 80% bus utilization in average DDR SDRAM Controller – CeRoma Ltd. Ultra small – about 12Kgates Single port data and multi port arbitration – 16 masters Highly efficient – over 2GB/sec on 64-bit bus at 200MHz Service Proposal DDR-x Controller architecture and specification Bandwidth-efficient and silicon-effective design

Experience Background

SDRAM Controller – NeoMagic

Ultra small – less than 10Kgates

Highly efficient – over 80% bus utilization in average

DDR SDRAM Controller – CeRoma Ltd.

Ultra small – about 12Kgates

Single port data and multi port arbitration – 16 masters

Highly efficient – over 2GB/sec on 64-bit bus at 200MHz

Service Proposal

DDR-x Controller architecture and specification

Bandwidth-efficient and silicon-effective design

SOC/ASIC/ASSP Secured Architecture Experience Background DVB receiver SOC – CeRoma Ltd Digital TV Transport Stream receiver with CAS support PVR (DVR) content security for DRM Anti-cloning architecture Investigation – VBox Ltd. Digital TV receiver SOC – Support of multiple DRM standards Copy protection on content transferring – DTCP Anti-cloning architecture Service Proposal SOC/ASIC/ASSP architecture for content protection and data security DRM support – specifications for networking and storage applications System specifications for any requirements of embedded cryptography support

Experience Background

DVB receiver SOC – CeRoma Ltd

Digital TV Transport Stream receiver with CAS support

PVR (DVR) content security for DRM

Anti-cloning architecture

Investigation – VBox Ltd.

Digital TV receiver SOC – Support of multiple DRM standards

Copy protection on content transferring – DTCP

Anti-cloning architecture

Service Proposal

SOC/ASIC/ASSP architecture for content protection and data security

DRM support – specifications for networking and storage applications

System specifications for any requirements of embedded cryptography support

SW Development Tools and Automation Experience Background Carmel DSP – Infineon Technologies (I.C.Com) Programming languages concept for highly-parallel architecture - US Patent 6314557 Pipe/Clock accurate SW model/simulator Associative Processing Core – NeoMagic Ltd. C-language concept for massive SIMD (large vector) architecture Pipeline and ILP (Instruction-level parallelism) and DLP (Data-level parallelism) automatic optimizer on machine language layer (Assembler) Service Proposal Pipe- and clock-accurate high-performance SW models Development tools complete concept specification High-level and machine-level languages specifications optimized to the certain architecture Automatic ILP and DLP Assembler optimizer for highly parallel VLIW and SIMD architectures Support of VLIW architectures Optimization of pipeline and flow break effects Automatic parallelism

Experience Background

Carmel DSP – Infineon Technologies (I.C.Com)

Programming languages concept for highly-parallel architecture - US Patent 6314557

Pipe/Clock accurate SW model/simulator

Associative Processing Core – NeoMagic Ltd.

C-language concept for massive SIMD (large vector) architecture

Pipeline and ILP (Instruction-level parallelism) and DLP (Data-level parallelism) automatic optimizer on machine language layer (Assembler)

Service Proposal

Pipe- and clock-accurate high-performance SW models

Development tools complete concept specification

High-level and machine-level languages specifications optimized to the certain architecture

Automatic ILP and DLP Assembler optimizer for highly parallel VLIW and SIMD architectures

Support of VLIW architectures

Optimization of pipeline and flow break effects

Automatic parallelism

RT & Embedded SW & FW Design Experience Background DSPG – speech codecs and speech recognition algorithms implementation Infineon Technologies (I.C.Com) – speech codecs and DSP benchmarks implementation AiTech – RT OS BSP and drivers development Service Proposal Low-level drivers and BSP design and implementation DSP, benchmarks, video and image processing algorithms implementation Low-level programming on C and Assembly, RT-optimized implementation

Experience Background

DSPG – speech codecs and speech recognition algorithms implementation

Infineon Technologies (I.C.Com) – speech codecs and DSP benchmarks implementation

AiTech – RT OS BSP and drivers development

Service Proposal

Low-level drivers and BSP design and implementation

DSP, benchmarks, video and image processing algorithms implementation

Low-level programming on C and Assembly, RT-optimized implementation

IP-s Architecture & Specification Bus Arbiter 2D Accelerator Digital Display Controller Digital TV Multi-Standard Stream Receiver Crypto-DMA for Digital TV CAS and DRM DRAMx Ultra-small and Highly-efficient Controller Scalable Long Instruction Word (VLIW-like) CPU Core and ISA Assembler-layer automatic optimizer

Bus Arbiter

2D Accelerator

Digital Display Controller

Digital TV Multi-Standard Stream Receiver

Crypto-DMA for Digital TV CAS and DRM

DRAMx Ultra-small and Highly-efficient Controller

Scalable Long Instruction Word (VLIW-like) CPU Core and ISA

Assembler-layer automatic optimizer

IP Example Scalable Long Instruction Word CPU Core

Scalable Long Instruction Word Architecture SLIW – Scalable Long Instruction Word More than traditional VLIW architecture A single Instruction word contains parallel and single instructions The highest possible utilization of the Long Instruction Word Pyramid Instruction Decoder Up to 4 short instructions contained in a single SLIW instruction word Up to 2 long instructions contained in a single SLIW instruction word A single quad instruction occupies the entire SLIW instruction word Various permutations of short and long instructions in combinatorial parallel and single layouts within a single SLIW instruction word 16-bit Decoder 16-bit Decoder 16-bit Decoder 16-bit Decoder 32-bit Decoder 32-bit Decoder 64-bit Decoder Lite Pyramid Instruction Decoder Up to 2 short instructions can be executed in a single clock A single long instruction can be executed in a single clock Various permutation of short instructions within a single 32-bit SLIW instruction word 16-bit Decoder 16-bit Decoder 32-bit Decoder

SLIW – Scalable Long Instruction Word

More than traditional VLIW architecture

A single Instruction word contains parallel and single instructions

The highest possible utilization of the Long Instruction Word

Pyramid Instruction Decoder

Up to 4 short instructions contained in a single SLIW instruction word

Up to 2 long instructions contained in a single SLIW instruction word

A single quad instruction occupies the entire SLIW instruction word

Various permutations of short and long instructions in combinatorial parallel and single layouts within a single SLIW instruction word

Lite Pyramid Instruction Decoder

Up to 2 short instructions can be executed in a single clock

A single long instruction can be executed in a single clock

Various permutation of short instructions within a single 32-bit SLIW instruction word

SLIW Versus VLIW Execution Unit 1 Execution Unit 2 Execution Unit 3 Execution Unit 4 Instructon1 Instruction 2 Instruction 3 Instruction 4 EU1 EU2 EU3 EU4 NOP NOP EU1 EU2 EU3 EU4 NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP VLIW VLIW Instruction keeps the same length independently on the number of activated Execution units

SLIW Versus VLIW NOP-less approach: A single SLIW word may contain a couple of single instructions Execution Unit 1 Execution Unit 2 Execution Unit 3 Execution Unit 4 Instructon1 Instruction 2 Instruction 3 Instruction 4 EU1 EU2 EU3 EU4 EU1 EU2 EU3 EU4 SLIW Instruction 1 Instruction 2 EU2 EU3 More layouts are available ...

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