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Solution Introduction
Solution Introduction
CONFIDENTIAL

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P.O.B 10124, Petah Tiqwa 49001, Israel Fax: +972‐3‐9214577
ARCHITECTERRA
Automatic SW Optimization For Parallel Processing Architectures
© Copyright Georgiy Shenderovich, 2009
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ARCHITECTERRA
Solution Introduction
Table of Contents
1 THE BACKGROUND............................................................................................................................ 4
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P.O.B 10124, Petah Tiqwa 49001, Israel Fax: +972‐3‐9214577
ARCHITECTERRA
Automatic SW Optimization For Parallel Processing Architectures
1 THE BACKGROUND
ArchitecTerra presents a generic methodology for automatic optimization of SW code generated for modern
processing architectures with high degree of instructions and data parallelism.
The optimal SW is required for time critical SW like interrupt handlers, inner loops in the computing
intensive implementations or any other purpose where SW developer is required to achieve the best
processor performance.
The modern processing architectures for better performance are using deep instructions pipeline, vectored
instructions with multiple operands in a single instruction, long instruction words containing several
processor instructions executed simultaneously and special purpose or coprocessor macro instructions
utilizing at the same time multiple resources of the processor and its subsystem.
Two pipeline approaches are used in the modern architectures: the data-stationary model and the time-
stationary model. The data-stationary model guarantees that instructions order for the certain data flow will
prevent any data hazards. The processor HW controls that new instructions entering the pipeline will not be
able to change any resource involved in the current data operation until this operations completes. The time-
stationary model guaranties instructions execution in order and in rate of entering into the pipeline, where
the programmer is responsible for preventing any data hazard effects. The data-stationary model allows
more reliable code when the time-stationary model allows more efficient manipulation by the processor
resources and more efficient code finally.
The high-level languages are usually used today even for embedded and RT SW development. It
significantly increases the development efficiency and shortens the SW products time-to-market. C and C++
languages are widely used today for embedded and RT SW development. However, even the best C or C++
compiler is not capable to consider for SW optimization all the advantages of processor architecture. Many
techniques and tricks are used by compilers to increase its ability to generate more HW-oriented code.
Unfortunately, all these methods finally require from the SW engineer to think much more HW than SW just
because the improvement in the most cases is achieved by embedding the HW-optimized primitives
encapsulated into C or C++ syntax constructions. Such primitives are finally a kind of macro or real Run-
Time library which should be used in certain critical sections of the SW code. Usage of these libraries
already requires from the SW engineer the knowledge about very low-level processor resources like
registers, accumulators, available parallelism (DLP and ILP) and probably more. However, even such
methodology doesn’t guarantee that the generated code will be optimal. Indeed, the primitives inserted into
the generated code are optimized within themselves, but performance lost is more than probable between the
primitives during integration.
The ArhitecTerra methodology allows creation of automatic tools set for generated SW code optimization
considering all the architectural advantages of the processor and getting very close to the manual
optimization quality. The technology is especially very usable for automatic code optimization of programs
written with Assembly languages.
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