Endianness
Upcoming SlideShare
Loading in...5
×
 

Endianness

on

  • 2,973 views

Lecture slides

Lecture slides

Statistics

Views

Total Views
2,973
Views on SlideShare
2,960
Embed Views
13

Actions

Likes
0
Downloads
41
Comments
0

4 Embeds 13

http://www.slideshare.net 7
http://www.linkedin.com 3
http://www.slideee.com 2
http://www.slashdocs.com 1

Accessibility

Categories

Upload Details

Uploaded via as Adobe PDF

Usage Rights

© All Rights Reserved

Report content

Flagged as inappropriate Flag as inappropriate
Flag as inappropriate

Select your reason for flagging this presentation as inappropriate.

Cancel
  • Full Name Full Name Comment goes here.
    Are you sure you want to
    Your message goes here
    Processing…
Post Comment
Edit your comment

Endianness Endianness Presentation Transcript

  • Endianness A Lecture to FW and VLSI Engineers
  • CONVENTION Binary Numbers Presentation Notation Each binary digit represents only a single bit of binary number – N- digit binary number means the same as N-bit binary number Binary digit weight The most left positioned bit is called The Most Significant Bit – MSB The most right positioned bit is called The Least Significant Bit – LSB Each bit has its own weight • LSB – the lowest • MSB – the highest For N-bit binary number each bit has a weight equal to 2i-1, where i∈[1,N] Presenting N-bit binary numbers, it is acceptable to reference each bit by its index – else it is called a bit order The indices are incrementally growing from 0 to N-1 When indices grow from left to right the MSB is 0th bit and the LSB is (N- 1)th bit When indices grow from right to left the MSB is (N-1)th bit and the LSB is 0th bit © Georgiy Shenderovich, 2006-2009 Shenderovich, 2006- Email: georgiysh@gmail.com Mbl.: +972-544-491911 +972- 544- 2
  • CONVENTION Storage Units Byte – 8 bits Half Word – 2 bytes MSB LSB Word – 4 bytes 231...20 Word Double Word – 8 bytes Register Storage Presentation – either CPU internal, standalone or functional blocks internal registers © Georgiy Shenderovich, 2006-2009 Shenderovich, 2006- Email: georgiysh@gmail.com Mbl.: +972-544-491911 +972- 544- 3
  • CONVENTION Memory Storage Presentation Byte is the minimally addressable storage and therefore has not alignment Half word is aligned at even address (dividable on 2) Word is aligned at even address but dividable on 4, 8, etc… Double word is aligned at even address but dividable on 8, 16, etc… MSB LSB MSB LSB MSB LSB MSB LSB Address Offset 0...7 Address Offset 0 Address Offset 0 Address Offset 0 Address Offset 1 Address Offset 1 Address Offset 1 27...20 Byte Address Offset 2 Address Offset 2 27...20 Half Word Address Offset 3 Address Offset 3 Address Offset 4 27...20 Word Address Offset 5 Address Offset 6 Address Offset 7 27...20 Double Word © Georgiy Shenderovich, 2006-2009 Shenderovich, 2006- Email: georgiysh@gmail.com Mbl.: +972-544-491911 +972- 544- 4
  • 1st station Some conclusions so far about binary numbers presentation convention Writing, printing, showing the binary numbers use the same convention as any other Number System – the higher significant digits are located at the left of the number and have higher weights, when the lower significant digits are located at the right of the number and have lower weights Binary digits or bits in binary numbers are referencing by their indices growing from left to right or vice versa having at the same time no any relation to weight of each bit Some conclusions so far about storage resources Register may be a standalone storage resource or internal storage resource of CPU or resource of any other functional block in the system. Register completely represents the binary numbers presentation convention and bits in the register may be indexed in any direction Memory is a storage resource representing an array of bytes sequentially addressed depending on access width – byte, half word, word or double word © Georgiy Shenderovich, 2006-2009 Shenderovich, 2006- Email: georgiysh@gmail.com Mbl.: +972-544-491911 +972- 544- 5
  • Endianness Introduction In computing, endianness is the byte (and sometimes bit) ordering used to represent some kind of data. Typical cases are the order in which integer values are stored as bytes in computer memory (relative to a given memory addressing scheme) and the transmission order over a network or other medium. When specifically talking about bytes, endianness is also referred to simply as byte order More Definitions Increasing numeric significance with increasing memory addresses, is known as little-endian Opposite of the above, most-significant byte first, is called big- endian All the definitions look simple, clear and unambiguous – however a lot of questions appear when HW implementation starts, especially when systems with mixed endianeess are created or integrated © Georgiy Shenderovich, 2006-2009 Shenderovich, 2006- Email: georgiysh@gmail.com Mbl.: +972-544-491911 +972- 544- 6
  • Basic But Necessary Statements Memory doesn’t have endianness – memory just stores the bytes of data Registers don’t have endianness – registers represent the data on their way from or to the memory for further processing The LSB of Register contains the LSB of data after read from the memory or before write to the memory The MSB of Register contains the MSB of data after read from the memory or before write to the memory The main questions of endianness How the data are transferred from the memory to the register and back Which byte of the register and which addressable byte of the memory correspond to each other during the read/write operation Fortunately there is a very simple answer – it depends on the interpretation of the CPU, functional block or any other operating unit in the system And Finally – Endianness is not less and not more than INTERPRETATION. Only operating unit decides about order and weight of bytes and bits during byte, half word, word, duble word or any other transaction size © Georgiy Shenderovich, 2006-2009 Shenderovich, 2006- Email: georgiysh@gmail.com Mbl.: +972-544-491911 +972- 544- 7
  • 2nd Station Memory doesn’t have endianness – it’s only a data storage Register doesn’t have endianness – it’s another kind of data storage Endianness is interpretation of data on its way between memory and register © Georgiy Shenderovich, 2006-2009 Shenderovich, 2006- Email: georgiysh@gmail.com Mbl.: +972-544-491911 +972- 544- 8
  • Byte Access Each byte of register may be exchanged with any single byte of memory There is not a place for endianness interpretation – so particularly a byte memory access doesn’t have endianness © Georgiy Shenderovich, 2006-2009 Shenderovich, 2006- Email: georgiysh@gmail.com Mbl.: +972-544-491911 +972- 544- 9
  • Half Word Access Little-endian data exchange – more significant data byte corresponds to higher address Big-endian data exchange – more significant data byte corresponds to lower address © Georgiy Shenderovich, 2006-2009 Shenderovich, 2006- Email: georgiysh@gmail.com Mbl.: +972-544-491911 +972- 544- 10
  • Word Access Little-endian data exchange – more significant data byte corresponds to higher address, similar to half word © Georgiy Shenderovich, 2006-2009 Shenderovich, 2006- Email: georgiysh@gmail.com Mbl.: +972-544-491911 +972- 544- 11
  • Word Access Big-endian data exchange – more significant data byte corresponds to lower address, similar to half word MSB LSB MSB LSB MSB LSB A B C D A B C D E F G H I J 263...20 231...20 215...20 Double Word Word Half Word MSB LSB MSB LSB MSB LSB Address Offset 0 Address Offset 0 Address Offset 0 A E I Address Offset 1 Address Offset 1 Address Offset 1 B F J Address Offset 2 Address Offset 2 Address Offset 2 C G I Address Offset 3 Address Offset 3 Address Offset 3 D H J 27...20 27...20 27...20 Word Word Word © Georgiy Shenderovich, 2006-2009 Shenderovich, 2006- Email: georgiysh@gmail.com Mbl.: +972-544-491911 +972- 544- 12
  • Double Word Access Little-endian data exchange – more significant data byte corresponds to higher address, similar to word and half word MSB LSB MSB LSB MSB LSB A B C D E F G H I J K L M N 263...20 231...20 215...20 Double Word Word Half Word MSB LSB MSB LSB MSB LSB Address Offset 0 Address Offset 0 Address Offset 0 H L N Address Offset 1 Address Offset 1 Address Offset 1 G K M Address Offset 2 Address Offset 2 Address Offset 2 F J N Address Offset 3 Address Offset 3 Address Offset 3 E I M Address Offset 4 Address Offset 4 Address Offset 4 D L N Address Offset 5 Address Offset 5 Address Offset 5 C K M Address Offset 6 Address Offset 6 Address Offset 6 B J N Address Offset 7 Address Offset 7 Address Offset 7 A I M 27...20 27...20 27...20 Double Word Double Word Double Word © Georgiy Shenderovich, 2006-2009 Shenderovich, 2006- Email: georgiysh@gmail.com Mbl.: +972-544-491911 +972- 544- 13
  • Double Word Access Big-endian data exchange – more significant data byte corresponds to lower address, similar to word and half word MSB LSB MSB LSB MSB LSB A B C D E F G H I J K L M N 263...20 231...20 215...20 Double Word Word Half Word MSB LSB MSB LSB MSB LSB Address Offset 0 Address Offset 0 Address Offset 0 A I M Address Offset 1 Address Offset 1 Address Offset 1 B J N Address Offset 2 Address Offset 2 Address Offset 2 C K M Address Offset 3 Address Offset 3 Address Offset 3 D L N Address Offset 4 Address Offset 4 Address Offset 4 E I M Address Offset 5 Address Offset 5 Address Offset 5 F J N Address Offset 6 Address Offset 6 Address Offset 6 G K M Address Offset 7 Address Offset 7 Address Offset 7 H L N 27...20 27...20 27...20 Double Word Double Word Double Word © Georgiy Shenderovich, 2006-2009 Shenderovich, 2006- Email: georgiysh@gmail.com Mbl.: +972-544-491911 +972- 544- 14
  • 3rd Station A byte access doesn’t have endianness In big-endian and little-endian systems the half word, word and double word data is kept differently in the memory while keeping the same interpretation in the operating registers ATTENTION: Output of little-endian functional block will be INTERPRETED by big-endian block in OPPOSITE order and vice versa There is a number of mistaken approaches when integrating functional units with different endianness. Some of them are presented further © Georgiy Shenderovich, 2006-2009 Shenderovich, 2006- Email: georgiysh@gmail.com Mbl.: +972-544-491911 +972- 544- 15
  • Mistake #1 – Data lines crossing It is very known mistake when designer crosses the data lines to emulate opposite directions of big and little endianness MSB LSB MSB LSB A B C D C D ? ? MSB LSB MSB LSB A B C D D C B A A B C D ? ? D C 231...20 231...20 231...20 231...20 Word Word MSB LSB MSB LSB MSB LSB MSB LSB Address Offset 0 Address Offset 0 Address Offset 0 Address Offset 0 A A C C Address Offset 1 Address Offset 1 Address Offset 1 Address Offset 1 B B D D Address Offset 2 Address Offset 2 Address Offset 2 Address Offset 2 C C ? ? Address Offset 3 Address Offset 3 Address Offset 3 Address Offset 3 D D ? ? 27...20 27...20 27...20 27...20 Word Word Word Word Little-endian device reads 16-bit from Little-endian device reads 32-bit from Big-endian device writes Big-endian device writes memory at address 0. Data read 32-bit 0xABCD to memory memory at address 0. Data read 16-bit 0xCD to memory at conversion scheme incorrectly converts conversion scheme converts the read at address 0 address 0 the read data so that 16-bit transaction data to correct order may cause unpredictable result, and 32- bit transaction brings the data into the upper part of target register A single data lines crossing scheme causes the address logic to be dependent on transaction width. For problem resolving the dedicated lines crossing scheme should exist for each type of transaction © Georgiy Shenderovich, 2006-2009 Shenderovich, 2006- Email: georgiysh@gmail.com Mbl.: +972-544-491911 +972- 544- 16
  • Mistake #2 – Expanding Data Access Width A 32-bit little-endian device is expected to support big- endian 64-bit access It happens that each 32-bit part of the emulated 64-bit transaction is converted correctly to big-endian order, when the entire transaction doesn’t succeed The usual reason – internal data path remains little- endian and less significant internal registers are accessed first on their way to system memory In its turn the memory is accessed starting at lower addresses what finally cause data swapping on 32-bit boundary © Georgiy Shenderovich, 2006-2009 Shenderovich, 2006- Email: georgiysh@gmail.com Mbl.: +972-544-491911 +972- 544- 17
  • Final Note Behind the work with byte orders representing two types of endianness some platforms include the bit order in their endianness definition. So, the big-endian order of bytes also introduces an order of bits in byte where bit 0 is the MSB and bit 7 is the LSB Connection between the systems based on regular and “big- endian” bit order may look tricky, but actually it is very simple. There is only one rule – bits in bytes representing different orders are mutually connected from MSB to MSB of each other towards LSB respectively © Georgiy Shenderovich, 2006-2009 Shenderovich, 2006- Email: georgiysh@gmail.com Mbl.: +972-544-491911 +972- 544- 18