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Electrónica Digital       Flip-Flops
Objetivos:• Determinar la salida de un F-F RS NAND y un F-FNOR dado un m, state the output of an RS NAND andRS NOR.• Given...
LOGIC CIRCUITS      Logic circuits are classified into two groups:Combinational logic circuits   Logic gates make decision...
FLIP-FLOPS         •Memory device capable of storing one         bitS   Q    •Memory means circuit remains in one         ...
FLIP-FLOPS        SymbolSET                      •To SET a flip flop means to        S      Q         make Q =1RESET      ...
FLIP-FLOPS                                      5V                                      +V                       1k       ...
R-S FLIP-FLOPSymbols:                            Set                          Normal                                      ...
R-S FLIP-FLOP  Active-Low            NAND LATCH                                       Q     SET                        740...
ACTIVE-LOW R-S FLIP-FLOP       TIMING DIAGRAMS
R-S FLIP-FLOP  Active-High
ACTIVE-HIGH R-S FLIP-FLOP        TIMING DIAGRAMS
TEST                                                    Memory1. Logic gates make decisions, flip flops have _____________...
TESTWhat is the mode of operation of the R-S flip-flop (set, reset or hold)?What is the output at Q from the R-S flip-flop...
CLOCKED R-S FLIP-FLOP   Set         FF                Set          FF           S        Q                     S        Q ...
ClockDigital signal in the form of a rectangularor square wave        Astable      multivibrator A clocked flip flop chang...
TRIGGERING OF FLIP-FLOPS  • Level-triggering is the transfer of data from input to    output of a flip-flop anytime the cl...
CLOCKED R-S FLIP-FLOPSymbols:                                 Set             FF       Normal                             ...
TESTWhat is the mode of operation of the clocked R-S flip-flop (set, reset, hold)?What is the output at Q from the clocked...
CLOCKED R-S FLIP-FLOP      TIMING DIAGRAMS
POSITIVE EDGE TRIGGEREDSymbols:    R-S FLIP-FLOP        EDGE TRIGGERED R-S FLIP FLOP        SET                           ...
POSITIVE EDGE TRIGGERED        R-S FLIP-FLOP                        TIMING DIAGRAMS                        C              ...
NEGATIVE EDGE TRIGGEREDSymbols:   R-S FLIP-FLOP            EDGE TRIGGERED R-S FLIP FLOP            SET                    ...
NEGATIVE EDGE TRIGGERED      R-S FLIP-FLOP                        TIMING DIAGRAMS                        C                ...
TEST1. Type of flip flop where the outputs of circuit can change state anytimeone or more input changes?     ASYNCHRONOUS2...
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Unit 4 clocked_flip_flops

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Transcript of "Unit 4 clocked_flip_flops"

  1. 1. Electrónica Digital Flip-Flops
  2. 2. Objetivos:• Determinar la salida de un F-F RS NAND y un F-FNOR dado un m, state the output of an RS NAND andRS NOR.• Given a clock signal, determine the PGT and NGT.• Define “Edge Triggered” and “Level Triggered”.• Draw a Clocked F/F with and “Edge Triggered”clock input and a “Level Triggered” clock input.
  3. 3. LOGIC CIRCUITS Logic circuits are classified into two groups:Combinational logic circuits Logic gates make decisionsBasic buildingblocks include:Sequential logic circuits Flip Flops have memoryBasic building blocksinclude FLIP-FLOPS:
  4. 4. FLIP-FLOPS •Memory device capable of storing one bitS Q •Memory means circuit remains in one state after condition that caused the state is removed.R Q •Two outputs designated Q and Q-Not that are always opposite or complimentary. •When referring to the state of a flip flop, referring to the state of the Q output.
  5. 5. FLIP-FLOPS SymbolSET •To SET a flip flop means to S Q make Q =1RESET R Q Truth Table •To RESET a flip flop means to make Q = 0
  6. 6. FLIP-FLOPS 5V +V 1k 1k OUTPUT 1k 1k OUTPUT Q NOT Q 1k 1k NPN NPN 1k 1k set reset input input•The flip flop is a bi-stable multivibrator; it has two stable states.•The RS flip flop can be implemented with transistors.
  7. 7. R-S FLIP-FLOPSymbols: Set Normal S Q FF R Q Reset Comple- mentaryTruth Table: Mode of Operation Inputs Outputs S R Q Q’ Prohibited 0 0 1 1 Set 0 1 1 0 Reset 1 0 0 1 Hold 1 1 Q Q’
  8. 8. R-S FLIP-FLOP Active-Low NAND LATCH Q SET 7400 Q NOT RESET 7400DEMORGANIZED NAND LATCH NAND LATCH Q SET Q NOT RESET SET RES Q NOT-Q MODE 0 0 1 1 PROHIBITED 0 1 1 0 SET 1 0 0 1 RESET 1 1 NO CHG HOLD
  9. 9. ACTIVE-LOW R-S FLIP-FLOP TIMING DIAGRAMS
  10. 10. R-S FLIP-FLOP Active-High
  11. 11. ACTIVE-HIGH R-S FLIP-FLOP TIMING DIAGRAMS
  12. 12. TEST Memory1. Logic gates make decisions, flip flops have ____________________?2. One flip flop can store how many bits? 13. What are the two outputs of a flip flop? Q Q-NOT4. When referring to the state of a flip flop, we’re referring to the stateof which output? Q5. What does it mean to SET a flip flop? Q = 16. What does it mean to RESET a flip flop? Q = 0
  13. 13. TESTWhat is the mode of operation of the R-S flip-flop (set, reset or hold)?What is the output at Q from the R-S flip-flop (active LOW inputs)? L ? High H Mode of operation = ? Set H ? High H Mode of operation = ? Hold H ? Low L Mode of operation = ? Reset
  14. 14. CLOCKED R-S FLIP-FLOP Set FF Set FF S Q S Q Clock CLK Reset Q Reset Q R R ASYNCHRONOU SYNCHRONOUS SOutputs of logic circuit can Clock signal determineschange state anytime one exact time at which anyor more input changes output can change state
  15. 15. ClockDigital signal in the form of a rectangularor square wave Astable multivibrator A clocked flip flop changes state only when permitted by the clock signal
  16. 16. TRIGGERING OF FLIP-FLOPS • Level-triggering is the transfer of data from input to output of a flip-flop anytime the clock pulse is proper voltage level. • Edge-triggering is the transfer of data from input to output of a flip-flop on the rising edge (L-to-H) or falling edge (H-to-L) of the clock pulse. Edge triggering may be either positive-edge (L-to-H) or negative-edge (H-to-L). NGT-Negative Going TransitionPGT-Positive Going Transition Negative-edge triggering Positive-edge triggering H L time Level triggering
  17. 17. CLOCKED R-S FLIP-FLOPSymbols: Set FF Normal S Q Clock CLK Reset Q R Comple- mentaryTruth Table: Mode of operation Inputs Outputs Clk S R Q Q’ Hold + pulse 0 0 no change Reset + pulse 0 1 0 1 Set + pulse 1 0 1 0
  18. 18. TESTWhat is the mode of operation of the clocked R-S flip-flop (set, reset, hold)?What is the output at Q from the clocked R-S flip-flop (active HIGH inputs)? H ? High ^ L Mode of operation = ? Set L ? High ^ Mode of operation = Hold ? L L ?Low ^ H Mode of operation = ? Reset
  19. 19. CLOCKED R-S FLIP-FLOP TIMING DIAGRAMS
  20. 20. POSITIVE EDGE TRIGGEREDSymbols: R-S FLIP-FLOP EDGE TRIGGERED R-S FLIP FLOP SET QCLOCK Q NOT RESET CLK SET RES Q NOT-Q MODE PGT 0 0 NO CHG HOLD PGT 0 1 0 1 RESETTruth Table: PGT 1 PGT 1 0 1 0 SET 1 1 1 INVALID CLK R S Q 0 X X NO CHG 1 X X NO CHG X X NO CHG 0 0 NO CHG 0 1 SET 1 0 RESET 1 1 ILLEGAL
  21. 21. POSITIVE EDGE TRIGGERED R-S FLIP-FLOP TIMING DIAGRAMS C RCLK R S Q 0 0 0 1 NO CHG SET S 1 0 RESET 1 1 ILLEGAL Q
  22. 22. NEGATIVE EDGE TRIGGEREDSymbols: R-S FLIP-FLOP EDGE TRIGGERED R-S FLIP FLOP SET QCLOCK EDGE DETECTOR Q NOT RESET CLK SET RES Q NOT-Q MODE PGT 0 0 NO CHG HOLD PGT 0 1 0 1 RESETTruth Table: PGT 1 PGT 1 0 1 0 SET 1 1 1 INVALID CLK R S Q 0 X X NO CHG 1 X X NO CHG X X NO CHG 0 0 NO CHG 0 1 SET 1 0 RESET 1 1 ILLEGAL
  23. 23. NEGATIVE EDGE TRIGGERED R-S FLIP-FLOP TIMING DIAGRAMS C RCLK R S Q 0 0 0 1 NO CHG SET S 1 0 RESET 1 1 ILLEGAL Q
  24. 24. TEST1. Type of flip flop where the outputs of circuit can change state anytimeone or more input changes? ASYNCHRONOUS2. Type of flip flop where the clock signal controls when any output canchange state? SYNCHRONOUS3. What do we call a digital signal in the form of a repetitive pulse or square wave? CLOCK4. Which is easier to design and troubleshoot, clocked or not clocked flip flops? Clocked flip flops are easier to troubleshoot because we can stop the clock and examine one set of input and output conditions.
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