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Accuracy Management for Delay-oriented Control of Digital VLSI Simulation. Basic overview of Ph.D. thesis work at Columbia University under Professor Charles Zukowski.

Accuracy Management for Delay-oriented Control of Digital VLSI Simulation. Basic overview of Ph.D. thesis work at Columbia University under Professor Charles Zukowski.

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Glsv00dare Glsv00dare Presentation Transcript

  • Accuracy Management for Mixed-Mode Digital VLSI Simulation Gary L. Dare* & Charles A. Zukowski Department of Electrical Engineering Columbia University New York, New York 10027-6699 * DigitalDNA Systems Architecture Lab Motorola Labs
  • State of the Art/Motivation
    • VLSI Design
      • Higher levels of circuit integration
      • Larger scale systems
        • System-on-Chip
      • High Performance Applications
        • computing, telecommunications
    • VLSI Simulation
      • Improve cycle time – reduce/eliminate prototyping.
      • Electrical simulation (SPICE) - accurate, costly
      • Approximate methods - efficient, limited feasibility
      • Switch-level simulation - fast but simple; too little info
  • State of the Art/Motivation II
    • Mixed-Mode Digital VLSI Simulation
      • Combines higher & lower accuracy analysis
        • Manual selection of accuracy (usually 2)
        • Problems involve large # subcircuits
    • Waveform Relaxation
      • Partitioned simulation of subcircuits
      • Iterative refinement
      • Compatible with Mixed-Mode Simulation
    •  Solution Requirements
      • Automate assignment of simulation accuracy
        • Higher accuracy on critical paths
        • Lower accuracy off
  • Problems Addressed
    • Simulation Accuracy
      • Provide guaranteed accuracy in timing simulation of digital VLSI.
    • Computational Efficiency
      • Determine efficient means of analyzing different parts of circuit.
      • Highest accuracy throughout not necessary.
    • Handling large circuits
      • Data management for assigning accuracy to large numbers of subcircuits.
  • Uncertainty on Critical Paths
    • Critical path (B, C) determines delay at Output
    • For 20% accuracy in simulated output signal delay
      • Simulate all at 20%, or …
      • Simulate differently in mixed mode (A @ 40%)
  • Uncertainty Redistribution
    • Computation increases with accuracy
      • Uncertainty x i decreases
    • Computation increases with “complexity”
      • e.g., size, b i
    • Delay uncertainty on signal path constrained by output specification, e.
    • Required accuracy for block N on a signal path:
      • x n = e sqrt(b n / d n ) /  sqrt(b i d i )
    10 20 15
  • Application of Heuristics
    • Utilization
      • Iterative simulation
        • Start with “rough”, low accuracy analysis
        • Refine with heuristics
        • Update simulation (iterative process) – until convergence
      • Refinement process:
        • Apply heuristic to end block; calculate accuracy
        • Redistribute remaining uncertainty among preceding blocks
      • Recursive levelized traversal of circuit:
        • Output-to-input (post-simulation iteration)
        • Level-by-level
    •  Accuracy Management
  • Mixed-Mode Testbed
    • A mixed-mode relaxation simulation framework
      • Input, scheduling, waveform data management
      • V.1 “Algorithmic” – modeled AM behavior
        • “ virtual” simulators
      • V.2 Ported some existing simulators
        • Electrical – GSOLVER [Gristede]
        • Piece-wise Approximate – SPECS [Visweswariah]
        • Switch-level RC Delay – DIY [do-it-yourself]
    Testbed shell: Accuracy Mgt & Scheduling Sim 1 Sim 2 Sim 3
  • Predicted Simulation Costs
  • Simulated Benchmarks
  • Conclusions, Future Research
    • Conclusions
      • Automated the management of mixed-mode timing simulation.
      • Efficient heuristics & analysis to determine required accuracy.
      • Yield efficient computation for large # subcircuits
    • Future Research
      • Implement in actual EDA framework
      • Complement with analog for mixed-signal analysis
      • MIMD parallel processing (e.g., virtual time)
      • Other optimization bases?
      • Re-simulation approaches – localized updates?