Accuracy Management for Mixed-Mode Digital VLSI Simulation Gary L. Dare* & Charles A. Zukowski Department of Electrical En...
State of the Art/Motivation <ul><li>VLSI Design </li></ul><ul><ul><li>Higher levels of circuit integration </li></ul></ul>...
State of the Art/Motivation II <ul><li>Mixed-Mode Digital VLSI Simulation </li></ul><ul><ul><li>Combines higher & lower ac...
Problems Addressed <ul><li>Simulation Accuracy </li></ul><ul><ul><li>Provide guaranteed accuracy in timing simulation of d...
Uncertainty on Critical Paths <ul><li>Critical path (B, C) determines delay at Output </li></ul><ul><li>For 20% accuracy i...
Uncertainty Redistribution <ul><li>Computation increases with accuracy </li></ul><ul><ul><li>Uncertainty x i  decreases </...
Application of Heuristics <ul><li>Utilization </li></ul><ul><ul><li>Iterative simulation </li></ul></ul><ul><ul><ul><li>St...
Mixed-Mode Testbed <ul><li>A mixed-mode relaxation simulation framework </li></ul><ul><ul><li>Input, scheduling, waveform ...
Predicted Simulation Costs
Simulated Benchmarks
Conclusions, Future Research <ul><li>Conclusions </li></ul><ul><ul><li>Automated the management of mixed-mode timing simul...
Upcoming SlideShare
Loading in …5
×

Glsv00dare

776 views
723 views

Published on

Accuracy Management for Delay-oriented Control of Digital VLSI Simulation. Basic overview of Ph.D. thesis work at Columbia University under Professor Charles Zukowski.

0 Comments
0 Likes
Statistics
Notes
  • Be the first to comment

  • Be the first to like this

No Downloads
Views
Total views
776
On SlideShare
0
From Embeds
0
Number of Embeds
4
Actions
Shares
0
Downloads
1
Comments
0
Likes
0
Embeds 0
No embeds

No notes for slide

Glsv00dare

  1. 1. Accuracy Management for Mixed-Mode Digital VLSI Simulation Gary L. Dare* & Charles A. Zukowski Department of Electrical Engineering Columbia University New York, New York 10027-6699 * DigitalDNA Systems Architecture Lab Motorola Labs
  2. 2. State of the Art/Motivation <ul><li>VLSI Design </li></ul><ul><ul><li>Higher levels of circuit integration </li></ul></ul><ul><ul><li>Larger scale systems </li></ul></ul><ul><ul><ul><li>System-on-Chip </li></ul></ul></ul><ul><ul><li>High Performance Applications </li></ul></ul><ul><ul><ul><li>computing, telecommunications </li></ul></ul></ul><ul><li>VLSI Simulation </li></ul><ul><ul><li>Improve cycle time – reduce/eliminate prototyping. </li></ul></ul><ul><ul><li>Electrical simulation (SPICE) - accurate, costly </li></ul></ul><ul><ul><li>Approximate methods - efficient, limited feasibility </li></ul></ul><ul><ul><li>Switch-level simulation - fast but simple; too little info </li></ul></ul>
  3. 3. State of the Art/Motivation II <ul><li>Mixed-Mode Digital VLSI Simulation </li></ul><ul><ul><li>Combines higher & lower accuracy analysis </li></ul></ul><ul><ul><ul><li>Manual selection of accuracy (usually 2) </li></ul></ul></ul><ul><ul><ul><li>Problems involve large # subcircuits </li></ul></ul></ul><ul><li>Waveform Relaxation </li></ul><ul><ul><li>Partitioned simulation of subcircuits </li></ul></ul><ul><ul><li>Iterative refinement </li></ul></ul><ul><ul><li>Compatible with Mixed-Mode Simulation </li></ul></ul><ul><li> Solution Requirements </li></ul><ul><ul><li>Automate assignment of simulation accuracy </li></ul></ul><ul><ul><ul><li>Higher accuracy on critical paths </li></ul></ul></ul><ul><ul><ul><li>Lower accuracy off </li></ul></ul></ul>
  4. 4. Problems Addressed <ul><li>Simulation Accuracy </li></ul><ul><ul><li>Provide guaranteed accuracy in timing simulation of digital VLSI. </li></ul></ul><ul><li>Computational Efficiency </li></ul><ul><ul><li>Determine efficient means of analyzing different parts of circuit. </li></ul></ul><ul><ul><li>Highest accuracy throughout not necessary. </li></ul></ul><ul><li>Handling large circuits </li></ul><ul><ul><li>Data management for assigning accuracy to large numbers of subcircuits. </li></ul></ul>
  5. 5. Uncertainty on Critical Paths <ul><li>Critical path (B, C) determines delay at Output </li></ul><ul><li>For 20% accuracy in simulated output signal delay </li></ul><ul><ul><li>Simulate all at 20%, or … </li></ul></ul><ul><ul><li>Simulate differently in mixed mode (A @ 40%) </li></ul></ul>
  6. 6. Uncertainty Redistribution <ul><li>Computation increases with accuracy </li></ul><ul><ul><li>Uncertainty x i decreases </li></ul></ul><ul><li>Computation increases with “complexity” </li></ul><ul><ul><li>e.g., size, b i </li></ul></ul><ul><li>Delay uncertainty on signal path constrained by output specification, e. </li></ul><ul><li>Required accuracy for block N on a signal path: </li></ul><ul><ul><li>x n = e sqrt(b n / d n ) /  sqrt(b i d i ) </li></ul></ul>10 20 15
  7. 7. Application of Heuristics <ul><li>Utilization </li></ul><ul><ul><li>Iterative simulation </li></ul></ul><ul><ul><ul><li>Start with “rough”, low accuracy analysis </li></ul></ul></ul><ul><ul><ul><li>Refine with heuristics </li></ul></ul></ul><ul><ul><ul><li>Update simulation (iterative process) – until convergence </li></ul></ul></ul><ul><ul><li>Refinement process: </li></ul></ul><ul><ul><ul><li>Apply heuristic to end block; calculate accuracy </li></ul></ul></ul><ul><ul><ul><li>Redistribute remaining uncertainty among preceding blocks </li></ul></ul></ul><ul><ul><li>Recursive levelized traversal of circuit: </li></ul></ul><ul><ul><ul><li>Output-to-input (post-simulation iteration) </li></ul></ul></ul><ul><ul><ul><li>Level-by-level </li></ul></ul></ul><ul><li> Accuracy Management </li></ul>
  8. 8. Mixed-Mode Testbed <ul><li>A mixed-mode relaxation simulation framework </li></ul><ul><ul><li>Input, scheduling, waveform data management </li></ul></ul><ul><ul><li>V.1 “Algorithmic” – modeled AM behavior </li></ul></ul><ul><ul><ul><li>“ virtual” simulators </li></ul></ul></ul><ul><ul><li>V.2 Ported some existing simulators </li></ul></ul><ul><ul><ul><li>Electrical – GSOLVER [Gristede] </li></ul></ul></ul><ul><ul><ul><li>Piece-wise Approximate – SPECS [Visweswariah] </li></ul></ul></ul><ul><ul><ul><li>Switch-level RC Delay – DIY [do-it-yourself] </li></ul></ul></ul>Testbed shell: Accuracy Mgt & Scheduling Sim 1 Sim 2 Sim 3
  9. 9. Predicted Simulation Costs
  10. 10. Simulated Benchmarks
  11. 11. Conclusions, Future Research <ul><li>Conclusions </li></ul><ul><ul><li>Automated the management of mixed-mode timing simulation. </li></ul></ul><ul><ul><li>Efficient heuristics & analysis to determine required accuracy. </li></ul></ul><ul><ul><li>Yield efficient computation for large # subcircuits </li></ul></ul><ul><li>Future Research </li></ul><ul><ul><li>Implement in actual EDA framework </li></ul></ul><ul><ul><li>Complement with analog for mixed-signal analysis </li></ul></ul><ul><ul><li>MIMD parallel processing (e.g., virtual time) </li></ul></ul><ul><ul><li>Other optimization bases? </li></ul></ul><ul><ul><li>Re-simulation approaches – localized updates? </li></ul></ul>

×