1. Work items
By Sean Chen

2. Work items
● ATPG
● stil2tstl
● Slow path
● path delay
● CPU test
● Test flow
● JTAG
● Software solution
● openRISC
● External work for free publish
● Reference

3. stil2tstl
● What's stil /tstl
● Test Pattern
– stil for human view
– tstl for machine view
● Why use it?
● License issue...
● Debug / Hack / Mask

4. stil2tstl
Design flow *.STIL
● Translation
● Parser:
Parser
● Define Key words
● Assignment:
● Fit our data structures Lib
Assignment
(class)
● Analysis:
● Preamble
● Shift Analysis
● capture
● Translation:
Translation
● Cycle based
● Mapping:
● TSTL format Mapping

5. stil2tstl
● Memory usage
●

6. Traditional path delay flow
PATH DELAY
1. Slack based 1.Report analysis
1 2. Module based
3. clock based 6
*.xml total.rpt
STA
debussy
2 1.False path analysis
2. scan path analysis scan.rpt
3 1.critical path analysis
2.Latch analysis ana.rpt
3.Lopp analysis
4.Multi drive analysis
4 ATPG
5 NC-sim
Pattern
1.ATPG report analysis 1.NC-sim report analysis
atpg.rpt Nc-sim.rpt
No Nc vs atpg analysis
Yes

7. Enhance Path-Delay Flow
Garbage in = out

8. Enhance Path-Delay Flow
● What's un-testable path?
0
1 0
1
1
0

9. Enhance Path-Delay Flow
● Path extraction by STA
● Report timing … slack, multi cycle check...
Is that enough ?

10. Enhance Path-Delay Flow
● Sample timing report
A true Path list {
=====================
pin type incr path_delay c
=====================
A[0] (in) 0 0 r
U10/A NAND2 0 0 r
U10/Y NAND2 1 1 f
a b
U9/A NOT1 0 1 f
U9/Y NOT1 1 2 r
U4/A NAND2 1 3 r
U4/Y NAND2 1 4 f
M[1] (out) 0 4 f
d
====================
Data Required time 5
Data Arrival time 4 Only one to one path test
==================== not
Slack 1 whole chip test
}
coverage lost ......

12. *.v
*.lib
Check design constrain Design
constrain STA
SCAN_CHIN SCAN
SCAN TRS CELL
CHIN
XML Re_Check PATH
VIEWER DELAY
SLOW Report_timing Report_timing
Debussy PATH
SLOW
PATH
THROUGH
LATCH
SLOW PATH PATH DELAY

13. Enhance Path-Delay Flow
● Simulation results
Enhance flow is better

14. Enhance Path-Delay Flow
● XML path Dumper

15. Flow extent

16. Commands
● Commands
• max_paths
• slack
• -nworst
• clock
SLACK
• launch
• capture
SLACK
• IO SLACK +
+ CELL
• each CELL
+CLOCK
– noZ
Critical case filter
• group
Example : command
write_delay_paths –group <list>
-slack <float>
-nworst <int>
-max_paths <int>

17. CPU test flow
● HW/SW co Design flow

18. CPU test flow
The key components of the ASCII Interface are
ASCII Interface configuration file
DVC file
ASCII vector file
ait tool for running timing translation automatically
d2w for device cycle to timing setup conversion
aiv tool for running pattern translation automatically
v2b for translating tabular ASCII test patterns to binary
vector setups

19. CPU test flow

20. CPU test flow
● Test flow

21. CPU test flow
● Code analysis
● Test Suites
– DC test, Cache test
● Setup Files
– Pins, Levels, Timing, Vector, attribute

22. CPU test flow
● Test-suite for Bin Map.
● What's Bin?
● CPU rank definition ex: 2.4G, 2.8G...

23. Hard to read

24. CPU test flow
● HARD Bin(1) ● HARD Bin(2)
C1 ULV00 C1 ULV00
C2 ULV01 C3 ULV02
C3 ULV02 C4 ULV03
... ...

25. CPU test flow
● For each bin classify
● Cut redundant Test suites
● Merge Test suites
● Reduce ATE test time
● Enhance flow density
● Reduce ATE memory usage

26. CPU test flow

27. JTAG
● What's JTAG?
● Standard Test Access Port and Boundary-Scan
Architecture
● Why use it?
● Easy debug
● GUI viewer
● Low cost
● Step by step
● OpenRISC project

28. JTAG
● Software solution

29. JTAG

30. JTAG
● JTAG FSM

31. JTAG
● Real view for JTAG
● @ Print port parallel control “Wiggler”

32. JTAG
● Wiggler

33. JTAG
● DLL control

34. ● How to use.
●

35. JTAG
● Test pattern inserted launch/capture

36. JTAG
verilog/
C/
Driver/

37. JTAG

38. JTAG

39. JTAG / UART
● HW/SW co simulation
All c model
● SystemC model
●
c/c++
Hardware

40. JTAG / UART

41. JTAG
● Same language @ platform
● Simulation time
● Debug
● Fast
Test suite
C/C++
Verilog 2 SystemC
Hardware Driver
Linux system call

42. External work for ARM
● ARM
● ARM BUS 3.0
– AHB, APB, AHB2APB Bridge.
– SystemC hardware model
– Emulator platform
● ARM BUS 4.0 (AXI)
– Emulator
● TLB(translation Lookup table)
– Emulator
● Cross compiler (gcc)
– Bootloader

43. External work
● High level synthesis
● LLVM
– C 2 Verilog assignment
● For loop 2 Bus interface emulator
● RISC CPU
– Emulator
● 3D IC Power Partition
● Multi STA

44. Reference
● My site
● http://funningboy.blogspot.com/