Virtual platform with OpenRisc 2010/06/08 by Sean Chen
How to Co-Work?
Case for OpenRisc
How to write your test program?
UART sample case
How to run and simulation ?
Include JTAG interface
Communication between host and target
Cross compiler (gcc 4 ARM)
How to debug?
Virtual platform Using the software platform to model the hardware components Benefits: Fast, build easily, debug quickly …. Effort: Model building (the Model accurately issue) Black Box (c) TDI TDO TMS TCLK TRST JTAG (SystemC) GDB (Client) Wrapper (SystemC) Console (Host)
SystemC processes can communicate in a simulated real-time environment, using signals of all the datatypes offered by C++, some additional ones offered by the SystemC library, as well as user defined. In certain respects, SystemC deliberately mimics the hardware description languages VHDL and Verilog , but is more aptly described as a system-level modeling language
Transaction-level modeling (TLM) is a high-level approach to modeling digital systems where details of communication among modules are separated from the details of the implementation of functional units or of the communication architecture. Communication mechanisms such as busses or FIFOs are modeled as channels ,
a toolchain is the set of programming tools that are used to create a product (typically another computer program or system of programs). The tools may be used in a chain, so that the output of each tool becomes the input for the next, but the term is used widely to refer to any set of linked development tools.
GNU compiler (cross compiler)
SystemPerl is a version of the SystemC language. It is designed to expand text so that needless repetition in the language is minimized. By using sp_preproc , SystemPerl files can be expanded into C++ files at compile time, or expanded in place to make them valid stand-alone SystemC files.
Verilator is the fastest free Verilog HDL simulator, and beats many commercial simulators. It compiles synthesizable Verilog (not test-bench code!), plus some PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code
The event-driven simulation tests are configured mainly by a single command file for Icarus. This command file is generated for each test. Another generated file is a header file defining some things such as the name of the test