serializer sean 2006/10/10
OUTLINE <ul><li>Introduction </li></ul><ul><li>Fundamental of serial links </li></ul><ul><li>Fundamental of PLL PFD Charge...
Introduction <ul><li>why use serializer? </li></ul><ul><li>In order to achieve higher data transfer rate, the internal bus...
Fundamental of serial links
Fundamental of serial links
Fundamental  of PLL
Fundamental of PLL
Fundamental of PFD
Fundamental of PLL <ul><li>PFD </li></ul>
Simulation of PFD
Fundamental of charge pump
Simulation of charge pump
PLL with freq domain
Fundamental Loop filter
Fundamental Loop filter
Fundamental Loop filter
Simulation of loop filter <ul><li>c1 vctrl gnd 2.28p </li></ul><ul><li>c2 vctrl net1 36.49p </li></ul><ul><li>r1 net1 gnd ...
Fundamental of VCO
VCO delay cell
Source bias circuit
VCO differential to single end
Simulation of VCO
 
 
Divider
Divide by 8
 
PLL device <ul><li>Bandwidth=5M </li></ul><ul><li>Kvco=953.8Mhz/v </li></ul><ul><li>r=4 </li></ul><ul><li>Phase margin=61....
 
The structure of PLL
serializer
PRBS
Serializer about 1.6G
Synchronization  circuit
 
Serializer cell
 
Serializer circuit
Output driver
 
cable <ul><li>r (propagation constant) </li></ul><ul><li>(attenuation constant) </li></ul><ul><li>B (phase constant) </li>...
 
 
<ul><li>Cycle to cycle jitter 0.010417 </li></ul><ul><li>the period jitter is : 0.329201  </li></ul><ul><li>total voltage ...
reference <ul><li>Design of  CMOS transmitter circuit for 2.5Gps NRZ data transmission </li></ul><ul><li>1Gbps serial-link...
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Serializer

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Serializer

  1. 1. serializer sean 2006/10/10
  2. 2. OUTLINE <ul><li>Introduction </li></ul><ul><li>Fundamental of serial links </li></ul><ul><li>Fundamental of PLL PFD Charge pump VCO Divide </li></ul><ul><li>Output driver </li></ul><ul><li>reference </li></ul>
  3. 3. Introduction <ul><li>why use serializer? </li></ul><ul><li>In order to achieve higher data transfer rate, the internal bus width has been increased, increasing the bus width, however, costs more pins and enlarge the chip area, so using parallel is not a good method ,that’s why we use the serializer </li></ul>
  4. 4. Fundamental of serial links
  5. 5. Fundamental of serial links
  6. 6. Fundamental of PLL
  7. 7. Fundamental of PLL
  8. 8. Fundamental of PFD
  9. 9. Fundamental of PLL <ul><li>PFD </li></ul>
  10. 10. Simulation of PFD
  11. 11. Fundamental of charge pump
  12. 12. Simulation of charge pump
  13. 13. PLL with freq domain
  14. 14. Fundamental Loop filter
  15. 15. Fundamental Loop filter
  16. 16. Fundamental Loop filter
  17. 17. Simulation of loop filter <ul><li>c1 vctrl gnd 2.28p </li></ul><ul><li>c2 vctrl net1 36.49p </li></ul><ul><li>r1 net1 gnd 3.442k </li></ul>
  18. 18. Fundamental of VCO
  19. 19. VCO delay cell
  20. 20. Source bias circuit
  21. 21. VCO differential to single end
  22. 22. Simulation of VCO
  23. 25. Divider
  24. 26. Divide by 8
  25. 28. PLL device <ul><li>Bandwidth=5M </li></ul><ul><li>Kvco=953.8Mhz/v </li></ul><ul><li>r=4 </li></ul><ul><li>Phase margin=61.9 </li></ul><ul><li>Divide by 8 </li></ul><ul><li>Charge current 150ua </li></ul><ul><li>c1 vctrl gnd 2.28p </li></ul><ul><li>c2 vctrl net1 36.49p </li></ul><ul><li>r1 net1 gnd 3.442k </li></ul>
  26. 30. The structure of PLL
  27. 31. serializer
  28. 32. PRBS
  29. 33. Serializer about 1.6G
  30. 34. Synchronization circuit
  31. 36. Serializer cell
  32. 38. Serializer circuit
  33. 39. Output driver
  34. 41. cable <ul><li>r (propagation constant) </li></ul><ul><li>(attenuation constant) </li></ul><ul><li>B (phase constant) </li></ul>
  35. 44. <ul><li>Cycle to cycle jitter 0.010417 </li></ul><ul><li>the period jitter is : 0.329201 </li></ul><ul><li>total voltage source power dissipation= 85.7196m watts </li></ul>
  36. 45. reference <ul><li>Design of CMOS transmitter circuit for 2.5Gps NRZ data transmission </li></ul><ul><li>1Gbps serial-link transceiver </li></ul><ul><li>A 30phase 500MHz pll for3X over-sampling clock </li></ul><ul><li>Data redcovery </li></ul>

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