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Image scalar hw_algorithm

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  • 1. Image Scalar HW Algorithm By Sean Chen
  • 2.
      Constrain
    • SOC Constrain
      • External memory
        • without bank or page support
        • 3. One space
          • ( DATA = ARR[Address] )
        • One read/ write
      • Communication Bus
        • Burst Mode support
        • 4. Interrupt
        • 5. Arbiter
        • 6. Master/Slaver
    Bus MEM IP
  • 7. Analysis
    • Constrain
      • For loop extension
        • I, j -> Address Mapped
        • 8. Timing sequence
      • I's it good ?
        • No Burst type
          • Not continuous Address
        • Cycle time
          • No reduce the computation time
    R0 R1 R4 R5 W0 W0 W1 W2 C W2 W3 W4 W4 W5 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
  • 9. Issue case
    • Issue case
      • Communication
        • Try to add Burst Mode
          • Increase Utility rate
          • 10. Easily into sleep/Idle mode
          • 11. Decrease Bus access time
      • Computation
        • PIPE line design
          • PINPON Buffer
      • Cost function
        • HW resource
          • Area ( inside Buffer )
  • 12. RD_BUF_0 RD_BUF_1 RD_BUF_1 RD_BUF_0 WT_BUF_0 WT_BUF_1 WT_BUF_0 WT_BUF_1 Cycle 1 Cycle 2 0 1 2 3 4 5 6 7 0 1 2 3 2 3 3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1
  • 13. RD_BUF_1 RD_BUF_0 WT_BUF_0 WT_BUF_1 RD_BUF_1 WT_BUF_1 WT_BUF_0 RD_BUF_1 RD_BUF_0 Cycle 3 Cycle 4 4 5 6 7 0 1 2 3 2 2 3 3 4 4 5 5 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 0 1 1 2 2 3 3 0 0 1 1 2 2 3 3 4 5 6 7 4 4 5 5 2 2 3 3 4 4 5 5 2 2 3 3 4 5 6 7 4 5 6 7
  • 14. RD_BUF_1 RD_BUF_0 WT_BUF_0 WT_BUF_1 Cycle 5 RD_BUF_1 RD_BUF_0 WT_BUF_0 WT_BUF_1 Cycle 6 8 9 10 11 4 5 6 7 4 4 5 5 4 4 5 5 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 2 2 3 3 2 2 3 4 8 9 10 11 4 5 6 7 4 4 5 5 6 6 7 7 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 2 2 3 3 4 4 5 5 0 0 1 1 2 2 3 3 2 2 3 3 4 4 5 5
  • 15. Row Column Column detection Row detection Tn-1 Tn R1 R2 R2 D1 row R2 R2 D2 row R2 R2 D1 row R2 W1 D1,2 column S W1,2 W1 W1 R3 R2 R2 R2 W1 W1 W2,3 D2,3 column S S W2 D3 row R2 R2 R2 W1 W2.3 W3 S W BND 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 8 9 10 11 12 13 14 15
  • 16.
      Performance estimation
    • Performance estimation
      • Case 4x4 -> 8x8 direct transform
        • One read/ write
          • C >= R_Bus(16) + W_bus(64) + C(4)/PE(N) ;
      • Case 4x4 -> 8x8 Our case
        • R_Buff dep 4, W_Buff dep 8
        • 17. Burst Mode
          • C >= ( 4*R_Bus(4) + 8*W_Bus(8) + S(6) ):