Design Automation Tool from Behavior Level to Transaction Level for Virtual Bus-Based Platforms  Advisor: Lih-Yih Chiou St...
Outline <ul><li>Motivation and Contributions </li></ul><ul><li>Previous Works </li></ul><ul><li>Proposed Design Automation...
Introduction <ul><li>Entering SoC era, more and more IPs are integrated onto one single chip </li></ul><ul><li>ESL (Electr...
Top-down Design Flow [1]S. S. Pasricha, N. Dutt, and M. Ben-Romdhane, &quot;Using TLM for exploring bus-based SoC communic...
Arbitration Level vs. Simulation Speed [2]C. Lennard and D. Mista, &quot;Taking Design to the System Level,&quot; 2006 [On...
High Level Synthesis <ul><li>Behavior Synthesis </li></ul><ul><li>Separate the Control and Data path from the behavior des...
Contributions <ul><ul><li>Rapid system exploration </li></ul></ul><ul><ul><ul><li>Fast exploration of multiple micro-archi...
Outline <ul><li>Motivation and Contributions </li></ul><ul><li>Previous Works </li></ul><ul><li>Proposed Design Automation...
Previous Works - SPARK (1) <ul><li>Input : C </li></ul><ul><li>Output C   VHDL </li></ul><ul><li>Advantages : </li></ul><u...
Previous Works - xPilot (2) <ul><li>Input: c/SystemC </li></ul><ul><li>Output: Verilog/SystemC </li></ul><ul><li>Method </...
Previous Works - MFASE (3) <ul><li>MFASE: </li></ul><ul><li>(Multiple Functions SoCs Analysis Environment) </li></ul><ul><...
Summary <ul><li>Previous works </li></ul><ul><ul><li>Synthesis tool  </li></ul></ul><ul><ul><ul><li>SPARK & xPilot Synthes...
Outline <ul><li>Motivation and Contributions </li></ul><ul><li>Previous Works </li></ul><ul><li>Proposed Design Automation...
Representation  <ul><li>Example  C to CDFG </li></ul><ul><li>Example for “If the else” </li></ul><ul><li>Example for </li>...
Outline <ul><li>Motivation and Contributions </li></ul><ul><li>Previous works </li></ul><ul><li>Proposed Design Automation...
Design Flow Overview 1/2
Design Flow Overview 2/2 <ul><li>Block Level </li></ul><ul><ul><li>Methodology </li></ul></ul><ul><ul><ul><li>Parallel  </...
Outline <ul><li>Motivation and Contributions </li></ul><ul><li>Previous Works </li></ul><ul><li>Proposed Design Automation...
Block Level <ul><li>Input  </li></ul><ul><ul><li>Functional Level CDFG </li></ul></ul><ul><ul><li>Block Inside Configurati...
Outline <ul><li>Motivation and Contributions </li></ul><ul><li>Previous works </li></ul><ul><li>Proposed Design Automation...
Block Level - Methodology 1/10 <ul><li>Computation  Reduction </li></ul><ul><li>Parallel analysis </li></ul><ul><ul><li>St...
Block Level – Methodology 2/10 <ul><li>Communication factors </li></ul><ul><ul><li>We assume the array will be located in ...
Block Level - Methodology 3/10 <ul><li>Communication  Reduction </li></ul>
Block Level - Methodology 4/10 <ul><li>Case 1: </li></ul><ul><ul><li>parallel deep 2 operator 1 cycle  </li></ul></ul><ul>...
Block Level - Methodology 5/10 <ul><li>Case 2 :  </li></ul><ul><ul><li>parallel deep 2  operator 2 cycles  </li></ul></ul>...
Block Level - Methodology 6/10 <ul><li>Case 3: </li></ul><ul><ul><li>parallel deep 2 operator 3 cycles </li></ul></ul><ul>...
Block Level - Methodology 7/10 <ul><li>Boundary case </li></ul><ul><li>Limitation: high address relation </li></ul><ul><li...
Block Level - Methodology 8/10 <ul><li>Case 4:  </li></ul><ul><ul><li>parallel deep 2 operator 4 cycles </li></ul></ul><ul...
Block Level - Methodology 9/10 <ul><li>Which case is better for implement? </li></ul><ul><li>Problem </li></ul><ul><ul><li...
Block Level - Methodology 10/10 <ul><li>Under condition  </li></ul><ul><ul><li>Parallel deep </li></ul></ul><ul><ul><li>Bo...
Outline <ul><li>Motivation and Contributions </li></ul><ul><li>Previous Works </li></ul><ul><li>Proposed Design Automation...
Translation  1/3 <ul><li>Example for CDFG to state transaction graph (STG) </li></ul><ul><ul><li>Fit to time step </li></u...
Translation  2/3 <ul><li>Step 1 </li></ul><ul><ul><li>CDFG to STG </li></ul></ul><ul><ul><li>Un-rolling “for loop” conditi...
Translation 3/3 <ul><li>Block Level </li></ul><ul><li>Interface </li></ul><ul><ul><li>Block to Wrapper  </li></ul></ul><ul...
Outline <ul><li>Motivation and Contributions </li></ul><ul><li>Previous Works </li></ul><ul><li>Proposed Design Automation...
Platform Level <ul><li>Input : </li></ul><ul><ul><li>Port mapping </li></ul></ul><ul><ul><li>Library location </li></ul></...
Outline <ul><li>Motivation and Contributions </li></ul><ul><li>Previous Works </li></ul><ul><li>Proposed Design Automation...
Develop Library for CoWare 1/3 <ul><li>Master Wrapper Generator </li></ul><ul><ul><li>Base on CoWare API for AMBA AHB   </...
Develop Library for CoWare 2/3 <ul><li>PMU Generator </li></ul><ul><li>Input :Configure </li></ul><ul><ul><li>Block Num: D...
Develop Library for CoWare 3/3 <ul><li>Known parameters </li></ul><ul><ul><li>Total simulation time </li></ul></ul><ul><ul...
Outline <ul><li>Motivation and Contributions </li></ul><ul><li>Previous Works </li></ul><ul><li>Proposed Design Automation...
System Control Generator <ul><li>TOP Control Generator </li></ul><ul><ul><li>Input </li></ul></ul><ul><ul><ul><li>Block sc...
Outline <ul><li>Motivation and Contributions </li></ul><ul><li>Previous Works </li></ul><ul><li>Proposed Design Automation...
CoWare - Scalar <ul><li>Sequence : Foreman, Football(30 frames) </li></ul>
Simple Bus Environment - Scalar SystemC 2.1 Simple bus  Read Transfer Write Transfer
CoWare Environment -Scalar <ul><li>Top Platform for scalar application </li></ul>Step 1 Step2 Step3 Step4   Step 5
Experiments – Scalar  <ul><li>Performance with app-time and cycle time </li></ul><ul><li>Scalar performance && State size ...
Experiments – Power Monitor <ul><li>Power Library </li></ul><ul><li>Method  </li></ul><ul><ul><li>Search the Look up table...
Experiments - Scalar <ul><li>Scalar176*144 Power saving  </li></ul>2124065.68 423934 1000 101638 WITH PMU 11000089.08 X X ...
<ul><li>DWT && IDWT </li></ul>Experiments - DWT DWT IDWT
Experiments - DWT <ul><li>Top Platform for DWT application </li></ul>Step 1 Step 2 Step 3 Step 4
Experiments - DWT <ul><li>Performance with app-time and cycle time </li></ul><ul><li>DWT performance && State size in Cycl...
Experiments - DWT <ul><li>DWT 44*36 Power saving </li></ul>2155442.52 68600 1000 76362 WITH PMU 4066501.32 X X 145962 NO P...
Outline <ul><li>Motivation and Contributions </li></ul><ul><li>Previous works </li></ul><ul><li>Proposed Design Automation...
Conclusions <ul><li>We develop a Automation tool from behavior level CDFG to TLM level SystemC for virtual bus based platf...
Future Works <ul><li>Model each module’s power using equations so that a more accurate power management could be carried o...
References <ul><li>[1]S. S. Pasricha, N. Dutt, and M. Ben-Romdhane, &quot;Using TLM for exploring bus-based SoC communicat...
<ul><li>Thank you </li></ul>
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Defense

  1. 1. Design Automation Tool from Behavior Level to Transaction Level for Virtual Bus-Based Platforms Advisor: Lih-Yih Chiou Student: Hi-Ho Chen 23 June 2008
  2. 2. Outline <ul><li>Motivation and Contributions </li></ul><ul><li>Previous Works </li></ul><ul><li>Proposed Design Automation Tool from Behavior Level to Transaction Level for Virtual Bus-Based Platforms </li></ul><ul><ul><li>Representation </li></ul></ul><ul><ul><li>Design Flow Overview </li></ul></ul><ul><ul><li>Block Level </li></ul></ul><ul><ul><ul><li>Methodology </li></ul></ul></ul><ul><ul><ul><li>Translation </li></ul></ul></ul><ul><ul><li>Platform Level </li></ul></ul><ul><ul><ul><li>Develop Library for CoWare </li></ul></ul></ul><ul><ul><ul><li>System Control Generator </li></ul></ul></ul><ul><li>Experiments </li></ul><ul><ul><li>Scalar 176*144 </li></ul></ul><ul><ul><li>DWT 44*36 </li></ul></ul><ul><li>Conclusions and Future works </li></ul><ul><li>References </li></ul>
  3. 3. Introduction <ul><li>Entering SoC era, more and more IPs are integrated onto one single chip </li></ul><ul><li>ESL (Electronic System Level) design is proposed to rapidly allow designer to simulate the system function behavior at higher level before hardware implementation </li></ul><ul><li>Communication design has become one of the important criteria for SoC design </li></ul>
  4. 4. Top-down Design Flow [1]S. S. Pasricha, N. Dutt, and M. Ben-Romdhane, &quot;Using TLM for exploring bus-based SoC communication architectures,&quot; 16th IEEE International Conference on Application-Specific Systems, Architecture Processors, 2005, pp. 79-85, 2005
  5. 5. Arbitration Level vs. Simulation Speed [2]C. Lennard and D. Mista, &quot;Taking Design to the System Level,&quot; 2006 [Online]. Available:(http://www.arm.com/pdfs/ARM_ESL_20_3_JC.pdf)
  6. 6. High Level Synthesis <ul><li>Behavior Synthesis </li></ul><ul><li>Separate the Control and Data path from the behavior description </li></ul><ul><ul><li>Control </li></ul></ul><ul><ul><ul><li>If then else </li></ul></ul></ul><ul><ul><ul><li>Switch case </li></ul></ul></ul><ul><ul><li>Data Path </li></ul></ul><ul><ul><ul><li>Data flow </li></ul></ul></ul>[3]SPARK. Methodology, http:// mesl.ucsd.edu/spark/methodology.shtml
  7. 7. Contributions <ul><ul><li>Rapid system exploration </li></ul></ul><ul><ul><ul><li>Fast exploration of multiple micro-architecture alternatives </li></ul></ul></ul><ul><ul><li>Shorter verification/simulation cycle </li></ul></ul><ul><ul><ul><li>S peed up with behavior-level to transaction level </li></ul></ul></ul><ul><ul><li>Quickly obtain the power and performance information </li></ul></ul><ul><ul><ul><li>Earlier estimation of design specifications </li></ul></ul></ul><ul><ul><li>Increase the performance </li></ul></ul><ul><ul><ul><li>Reduce the communication & computation </li></ul></ul></ul>
  8. 8. Outline <ul><li>Motivation and Contributions </li></ul><ul><li>Previous Works </li></ul><ul><li>Proposed Design Automation Tool from Behavior Level to Transaction Level for Virtual Bus-Based Platforms </li></ul><ul><ul><li>Representation </li></ul></ul><ul><ul><li>Design Flow Overview </li></ul></ul><ul><ul><li>Block Level </li></ul></ul><ul><ul><ul><li>Methodology </li></ul></ul></ul><ul><ul><ul><li>Translation </li></ul></ul></ul><ul><ul><li>Platform Level </li></ul></ul><ul><ul><ul><li>Develop Library for CoWare </li></ul></ul></ul><ul><ul><ul><li>System Control Generator </li></ul></ul></ul><ul><li>Experiments </li></ul><ul><ul><li>Scalar 176*144 </li></ul></ul><ul><ul><li>DWT 44*36 </li></ul></ul><ul><li>Conclusions and Future works </li></ul><ul><li>References </li></ul>
  9. 9. Previous Works - SPARK (1) <ul><li>Input : C </li></ul><ul><li>Output C VHDL </li></ul><ul><li>Advantages : </li></ul><ul><ul><li>They define a new synthesis tool for parallel design </li></ul></ul><ul><li>Disadvantages : </li></ul><ul><ul><li>No platform architecture </li></ul></ul><ul><ul><li>No communication issue </li></ul></ul>[4]SPARK:A High-Level Synthesis Frame work For Applying Parallelizing Compiler Transformations VLSI Design, 2003. Proceedings. 16th International Conference on 4-8 Jan. 2003 Page(s):461 – 466
  10. 10. Previous Works - xPilot (2) <ul><li>Input: c/SystemC </li></ul><ul><li>Output: Verilog/SystemC </li></ul><ul><li>Method </li></ul><ul><ul><li>Phase 1 </li></ul></ul><ul><ul><ul><li>SSDM </li></ul></ul></ul><ul><ul><li>Phase 2 </li></ul></ul><ul><ul><ul><li>Synthesis </li></ul></ul></ul><ul><li>Advantages: </li></ul><ul><ul><li>Directly mapping to FPGA </li></ul></ul><ul><ul><li>Quick Verification </li></ul></ul><ul><li>Disadvantages: </li></ul><ul><ul><li>No communication issue </li></ul></ul>[5]“Platform-Based Behavior-Level and System-Level Synthesis “ International SOC Conference, 2006 IEEE Sept. 2006 Page(s):199 – 202
  11. 11. Previous Works - MFASE (3) <ul><li>MFASE: </li></ul><ul><li>(Multiple Functions SoCs Analysis Environment) </li></ul><ul><li>Design Flow </li></ul><ul><li> HW/SW Partition. </li></ul><ul><li>Architecture mapping. </li></ul><ul><li> communication analysis. </li></ul><ul><li>… .. </li></ul><ul><li>Advantage </li></ul><ul><ul><li>HW/SW co-design </li></ul></ul><ul><li>Limitation </li></ul><ul><ul><li>IP Data Base </li></ul></ul>[6]MFASE: Multiple Functions SoCs Analysis Environment the VLSI Desing/CAD Symposium, Taiwan, Augest 2007
  12. 12. Summary <ul><li>Previous works </li></ul><ul><ul><li>Synthesis tool </li></ul></ul><ul><ul><ul><li>SPARK & xPilot Synthesis from hardware C code to RTL Verilog code </li></ul></ul></ul><ul><ul><ul><li>SPARK & xPilot did not consider communication issue </li></ul></ul></ul><ul><ul><ul><li>MFASE did not mention about how to generate automatically </li></ul></ul></ul><ul><li>Thesis </li></ul><ul><ul><ul><li>Building a automation tool from Functional Level to Transaction Level for virtual Bus-based Platform </li></ul></ul></ul><ul><ul><ul><ul><li>Computation & Communication issues </li></ul></ul></ul></ul><ul><ul><ul><ul><li>Automation tool from Behavior Level to Transaction Level </li></ul></ul></ul></ul>
  13. 13. Outline <ul><li>Motivation and Contributions </li></ul><ul><li>Previous Works </li></ul><ul><li>Proposed Design Automation Tool from Behavior Level to Transaction Level for Virtual Bus-Based Platforms </li></ul><ul><ul><li>Representation </li></ul></ul><ul><ul><li>Design Flow Overview </li></ul></ul><ul><ul><li>Block Level </li></ul></ul><ul><ul><ul><li>Methodology </li></ul></ul></ul><ul><ul><ul><li>Translation </li></ul></ul></ul><ul><ul><li>Platform Level </li></ul></ul><ul><ul><ul><li>Develop Library for CoWare </li></ul></ul></ul><ul><ul><ul><li>System Control Generator </li></ul></ul></ul><ul><li>Experiments </li></ul><ul><ul><li>Scalar 176*144 </li></ul></ul><ul><ul><li>DWT 44*36 </li></ul></ul><ul><li>Conclusions and Future works </li></ul><ul><li>References </li></ul>
  14. 14. Representation <ul><li>Example C to CDFG </li></ul><ul><li>Example for “If the else” </li></ul><ul><li>Example for </li></ul><ul><li>“ for loop” </li></ul>
  15. 15. Outline <ul><li>Motivation and Contributions </li></ul><ul><li>Previous works </li></ul><ul><li>Proposed Design Automation Tool from Behavior Level to Transaction Level for Virtual Bus-Based Platforms </li></ul><ul><ul><li>Representation </li></ul></ul><ul><ul><li>Design Flow Overview </li></ul></ul><ul><ul><li>Block Level </li></ul></ul><ul><ul><ul><li>Methodology </li></ul></ul></ul><ul><ul><ul><li>Translation </li></ul></ul></ul><ul><ul><li>Platform Level </li></ul></ul><ul><ul><ul><li>Develop Library for CoWare </li></ul></ul></ul><ul><ul><ul><li>System Control Generator </li></ul></ul></ul><ul><li>Experiments </li></ul><ul><ul><li>Scalar 176*144 </li></ul></ul><ul><ul><li>DWT 44*36 </li></ul></ul><ul><li>Conclusions and Future works </li></ul><ul><li>References </li></ul>
  16. 16. Design Flow Overview 1/2
  17. 17. Design Flow Overview 2/2 <ul><li>Block Level </li></ul><ul><ul><li>Methodology </li></ul></ul><ul><ul><ul><li>Parallel </li></ul></ul></ul><ul><ul><ul><li>Cascade (Multi cycle) </li></ul></ul></ul><ul><ul><li>Translation </li></ul></ul><ul><ul><ul><li>State & Edge Reduction </li></ul></ul></ul><ul><ul><ul><li>STG to SystemC generator </li></ul></ul></ul><ul><li>Platform Level using Simple Bus </li></ul><ul><ul><li>Approximate time simulation </li></ul></ul><ul><li>Platform Level using CoWare </li></ul><ul><ul><li>*.tcl generator </li></ul></ul><ul><ul><li>Peripheral generator </li></ul></ul>
  18. 18. Outline <ul><li>Motivation and Contributions </li></ul><ul><li>Previous Works </li></ul><ul><li>Proposed Design Automation Tool from Behavior Level to Transaction Level for Virtual Bus-Based Platforms </li></ul><ul><ul><li>Representation </li></ul></ul><ul><ul><li>Design Flow Overview </li></ul></ul><ul><ul><li>Block Level </li></ul></ul><ul><ul><ul><li>Methodology </li></ul></ul></ul><ul><ul><ul><li>Translation </li></ul></ul></ul><ul><ul><li>Platform Level </li></ul></ul><ul><ul><ul><li>Develop Library for CoWare </li></ul></ul></ul><ul><ul><ul><li>System Control Generator </li></ul></ul></ul><ul><li>Experiments </li></ul><ul><ul><li>Scalar 176*144 </li></ul></ul><ul><ul><li>DWT 44*36 </li></ul></ul><ul><li>Conclusions and Future works </li></ul><ul><li>References </li></ul>
  19. 19. Block Level <ul><li>Input </li></ul><ul><ul><li>Functional Level CDFG </li></ul></ul><ul><ul><li>Block Inside Configuration </li></ul></ul><ul><ul><ul><li>Max Parallel deep </li></ul></ul></ul><ul><ul><ul><li>Buffer Size </li></ul></ul></ul><ul><ul><ul><li>Boundary Case </li></ul></ul></ul><ul><ul><li>Block to Bus Configuration </li></ul></ul><ul><ul><ul><li>Max Burst size </li></ul></ul></ul><ul><ul><ul><li>Initial Address </li></ul></ul></ul><ul><ul><ul><li>Address offset </li></ul></ul></ul><ul><li>Output </li></ul><ul><ul><li>TLM SystemC </li></ul></ul>
  20. 20. Outline <ul><li>Motivation and Contributions </li></ul><ul><li>Previous works </li></ul><ul><li>Proposed Design Automation Tool from Behavior Level to Transaction Level for Virtual Bus-Based Platforms </li></ul><ul><ul><li>Representation </li></ul></ul><ul><ul><li>Design Flow </li></ul></ul><ul><ul><li>Block Level </li></ul></ul><ul><ul><ul><li>Methodology </li></ul></ul></ul><ul><ul><ul><li>Translation </li></ul></ul></ul><ul><ul><li>Platform Level </li></ul></ul><ul><ul><ul><li>Develop library </li></ul></ul></ul><ul><ul><ul><li>System Control generator </li></ul></ul></ul><ul><li>Experiment </li></ul><ul><ul><li>Scalar 176*144 </li></ul></ul><ul><ul><li>DWT 44*36 </li></ul></ul><ul><li>Conclusions and Future works </li></ul><ul><li>References </li></ul>
  21. 21. Block Level - Methodology 1/10 <ul><li>Computation Reduction </li></ul><ul><li>Parallel analysis </li></ul><ul><ul><li>Step 1: C to CDFG format </li></ul></ul><ul><ul><li>Step 2 : un-rolling the “for loop” to know the cycle counts </li></ul></ul><ul><ul><li>Step 3 : find the Solution to fit the “for loop” condition </li></ul></ul><ul><ul><ul><li>Under Hardware constrain </li></ul></ul></ul><ul><ul><ul><li>GCD Methodology </li></ul></ul></ul><ul><ul><li>Step 4: We will find the closed solution based on the Hardware condition </li></ul></ul><ul><ul><li>Step 5: update CDFG </li></ul></ul>for(j=0;j< 2 ;j++){ for(i=3;i< 7 ;i++){ b[j][i] = (a[j][i]+a[j][i+1])>>1; } }
  22. 22. Block Level – Methodology 2/10 <ul><li>Communication factors </li></ul><ul><ul><li>We assume the array will be located in the external Memory </li></ul></ul><ul><ul><li>How can we get data from external memory? </li></ul></ul><ul><ul><li>Bus Transform </li></ul></ul><ul><ul><ul><li>Single </li></ul></ul></ul><ul><ul><ul><li>Burst </li></ul></ul></ul><ul><ul><li>Buffer Size requirement </li></ul></ul><ul><ul><li>Parallel & size of data transformation will influence the performance and power </li></ul></ul>Burst New Transform Read Write
  23. 23. Block Level - Methodology 3/10 <ul><li>Communication Reduction </li></ul>
  24. 24. Block Level - Methodology 4/10 <ul><li>Case 1: </li></ul><ul><ul><li>parallel deep 2 operator 1 cycle </li></ul></ul><ul><ul><li>Irregularity: 1 Buss Access times: Read : 4 Write : 4 </li></ul></ul><ul><ul><li>Max Buffer Size usage :3 </li></ul></ul>B(): Burst size T(): Transaction number R: Read from bus W: Write to bus
  25. 25. Block Level - Methodology 5/10 <ul><li>Case 2 : </li></ul><ul><ul><li>parallel deep 2 operator 2 cycles </li></ul></ul><ul><ul><li>Irregularity : 1 Bus Access times: Read 2: Write 2 Max Buffer Size usage :5 </li></ul></ul>B(): Burst size T(): Transaction number R: Read from bus W: Write to bus
  26. 26. Block Level - Methodology 6/10 <ul><li>Case 3: </li></ul><ul><ul><li>parallel deep 2 operator 3 cycles </li></ul></ul><ul><ul><li>Irregularity : 2 Bus Access times: Read 3: Write 3 Max Buffer Size usage :8 </li></ul></ul>B(): Burst size T(): Transaction number R: Read from bus W: Write to bus
  27. 27. Block Level - Methodology 7/10 <ul><li>Boundary case </li></ul><ul><li>Limitation: high address relation </li></ul><ul><li>Relation with the Memory location </li></ul>
  28. 28. Block Level - Methodology 8/10 <ul><li>Case 4: </li></ul><ul><ul><li>parallel deep 2 operator 4 cycles </li></ul></ul><ul><ul><li>Irregularity :1 Bus Access times: Read 2: Write 2 Max Buffer Size usage :10 </li></ul></ul>B(): Burst size T(): Transaction number R: Read from bus W: Write to bus
  29. 29. Block Level - Methodology 9/10 <ul><li>Which case is better for implement? </li></ul><ul><li>Problem </li></ul><ul><ul><li>Case 1 </li></ul></ul><ul><ul><ul><li>single operator cycle </li></ul></ul></ul><ul><ul><ul><li>Bus Access times </li></ul></ul></ul><ul><ul><li>Case 3 </li></ul></ul><ul><ul><ul><li>Control is so complexity </li></ul></ul></ul><ul><ul><ul><li>No considering the Boundary case </li></ul></ul></ul><ul><ul><li>Case 4 </li></ul></ul><ul><ul><ul><li>Buffer size </li></ul></ul></ul><ul><li>We choose “Case 2” to implement </li></ul><ul><ul><li>Under Boundary case condition </li></ul></ul><ul><ul><li>Under Buffer size constrain </li></ul></ul><ul><ul><li>Bus Access issue </li></ul></ul><ul><ul><li>regular </li></ul></ul>2 3 2 4 Write Bus Access times O X O O Boundary Case 4 3 1 Case 1 Read Bus Access times Max Buffer size Irregularity 2 5 1 Case 2 1 2 10 8 2 3 Case 4 Case 3
  30. 30. Block Level - Methodology 10/10 <ul><li>Under condition </li></ul><ul><ul><li>Parallel deep </li></ul></ul><ul><ul><li>Boundary Case </li></ul></ul><ul><li>Analysis </li></ul><ul><ul><li>Step 1: Trace states by operator cycles </li></ul></ul><ul><ul><li>Step 2: separate the Read and Write part, find the period </li></ul></ul><ul><ul><li>Step 3: estimation the cycles and hardware cost </li></ul></ul><ul><ul><li>Step 4: find the best solution </li></ul></ul>O(): operator cycles B(): buffer size R(): Read counts W(): Write counts S(): state sizes Ir(): Irregularity case1 case2 case3 case4
  31. 31. Outline <ul><li>Motivation and Contributions </li></ul><ul><li>Previous Works </li></ul><ul><li>Proposed Design Automation Tool from Behavior Level to Transaction Level for Virtual Bus-Based Platforms </li></ul><ul><ul><li>Representation </li></ul></ul><ul><ul><li>Design Flow Overview </li></ul></ul><ul><ul><li>Block Level </li></ul></ul><ul><ul><ul><li>Methodology </li></ul></ul></ul><ul><ul><ul><li>Translation </li></ul></ul></ul><ul><ul><li>Platform Level </li></ul></ul><ul><ul><ul><li>Develop Library for CoWare </li></ul></ul></ul><ul><ul><ul><li>System Control Generator </li></ul></ul></ul><ul><li>Experiments </li></ul><ul><ul><li>Scalar 176*144 </li></ul></ul><ul><ul><li>DWT 44*36 </li></ul></ul><ul><li>Conclusions and Future works </li></ul><ul><li>References </li></ul>
  32. 32. Translation 1/3 <ul><li>Example for CDFG to state transaction graph (STG) </li></ul><ul><ul><li>Fit to time step </li></ul></ul><ul><ul><li>Easily to FSM Generator </li></ul></ul>Example for ”If then else” Example for ”for loop”
  33. 33. Translation 2/3 <ul><li>Step 1 </li></ul><ul><ul><li>CDFG to STG </li></ul></ul><ul><ul><li>Un-rolling “for loop” condition </li></ul></ul><ul><li>Step 2 </li></ul><ul><ul><li>Methodology </li></ul></ul><ul><ul><ul><li>Reduce Computation </li></ul></ul></ul><ul><ul><ul><ul><li>Parallel </li></ul></ul></ul></ul><ul><ul><ul><li>Reduce Communication </li></ul></ul></ul><ul><ul><ul><ul><li>Cascade </li></ul></ul></ul></ul><ul><ul><li>Architecture definition </li></ul></ul><ul><li>Step 3 </li></ul><ul><ul><li>Translate to TLM SystemC </li></ul></ul><ul><ul><ul><li>Header </li></ul></ul></ul><ul><ul><ul><li>Function </li></ul></ul></ul>
  34. 34. Translation 3/3 <ul><li>Block Level </li></ul><ul><li>Interface </li></ul><ul><ul><li>Block to Wrapper </li></ul></ul><ul><ul><li>Block to Block </li></ul></ul><ul><li>Control </li></ul><ul><ul><li>FSM </li></ul></ul><ul><li>Data path </li></ul><ul><ul><li>Operator assignment </li></ul></ul><ul><ul><li>Control signals </li></ul></ul><ul><ul><ul><li>Block to Wrapper </li></ul></ul></ul><ul><ul><ul><li>Block to Data path </li></ul></ul></ul><ul><ul><ul><li>Block to Buffer </li></ul></ul></ul>
  35. 35. Outline <ul><li>Motivation and Contributions </li></ul><ul><li>Previous Works </li></ul><ul><li>Proposed Design Automation Tool from Behavior Level to Transaction Level for Virtual Bus-Based Platforms </li></ul><ul><ul><li>Representation </li></ul></ul><ul><ul><li>Design Flow Overview </li></ul></ul><ul><ul><li>Block Level </li></ul></ul><ul><ul><ul><li>Methodology </li></ul></ul></ul><ul><ul><ul><li>Translation </li></ul></ul></ul><ul><ul><li>Platform Level </li></ul></ul><ul><ul><ul><li>Develop Library for CoWare </li></ul></ul></ul><ul><ul><ul><li>System Control Generator </li></ul></ul></ul><ul><li>Experiments </li></ul><ul><ul><li>Scalar 176*144 </li></ul></ul><ul><ul><li>DWT 44*36 </li></ul></ul><ul><li>Conclusions and Future works </li></ul><ul><li>References </li></ul>
  36. 36. Platform Level <ul><li>Input : </li></ul><ul><ul><li>Port mapping </li></ul></ul><ul><ul><li>Library location </li></ul></ul><ul><ul><li>CoWare setting </li></ul></ul><ul><li>Output </li></ul><ul><ul><li>*.tcl for CoWare based </li></ul></ul><ul><li>Communication Generator </li></ul><ul><ul><li>System Control </li></ul></ul><ul><ul><li>Wrapper </li></ul></ul><ul><ul><li>Mux </li></ul></ul><ul><ul><li>PMU </li></ul></ul><ul><ul><li>Interrupt </li></ul></ul>
  37. 37. Outline <ul><li>Motivation and Contributions </li></ul><ul><li>Previous Works </li></ul><ul><li>Proposed Design Automation Tool from Behavior Level to Transaction Level for Virtual Bus-Based Platforms </li></ul><ul><ul><li>Representation </li></ul></ul><ul><ul><li>Design Flow Overview </li></ul></ul><ul><ul><li>Block Level </li></ul></ul><ul><ul><ul><li>Methodology </li></ul></ul></ul><ul><ul><ul><li>Translation </li></ul></ul></ul><ul><ul><li>Platform Level </li></ul></ul><ul><ul><ul><li>Develop Library for CoWare </li></ul></ul></ul><ul><ul><ul><li>System Control Generator </li></ul></ul></ul><ul><li>Experiments </li></ul><ul><ul><li>Scalar 176*144 </li></ul></ul><ul><ul><li>DWT 44*36 </li></ul></ul><ul><li>Conclusions and Future works </li></ul><ul><li>References </li></ul>
  38. 38. Develop Library for CoWare 1/3 <ul><li>Master Wrapper Generator </li></ul><ul><ul><li>Base on CoWare API for AMBA AHB </li></ul></ul><ul><li>Advantage </li></ul><ul><ul><li>Support any burst type </li></ul></ul><ul><ul><li>Burst Lock </li></ul></ul><ul><li>Limitation </li></ul><ul><ul><li>Buffer size </li></ul></ul>
  39. 39. Develop Library for CoWare 2/3 <ul><li>PMU Generator </li></ul><ul><li>Input :Configure </li></ul><ul><ul><li>Block Num: Default 3 </li></ul></ul><ul><ul><li>Idle cycle: Default 1000 </li></ul></ul><ul><ul><li>Wake Up cycle: Default 1000 </li></ul></ul><ul><ul><li>Policy: fixed-time out Policy </li></ul></ul><ul><li>Output : SystemC </li></ul>
  40. 40. Develop Library for CoWare 3/3 <ul><li>Known parameters </li></ul><ul><ul><li>Total simulation time </li></ul></ul><ul><ul><li>Operation frequency </li></ul></ul><ul><ul><li>Active duration </li></ul></ul><ul><ul><li>Total active number </li></ul></ul>ACT Energy Idle Energy Total energy = (ACT Energy + Idle Energy) Power= (ACT Energy + Idle Energy)/total time Active power/unit time Number of Active counts <ul><li>Power Calculation </li></ul>Number of Idle counts Idle power/unit time
  41. 41. Outline <ul><li>Motivation and Contributions </li></ul><ul><li>Previous Works </li></ul><ul><li>Proposed Design Automation Tool from Behavior Level to Transaction Level for Virtual Bus-Based Platforms </li></ul><ul><ul><li>Representation </li></ul></ul><ul><ul><li>Design Flow Overview </li></ul></ul><ul><ul><li>Block Level </li></ul></ul><ul><ul><ul><li>Methodology </li></ul></ul></ul><ul><ul><ul><li>Translation </li></ul></ul></ul><ul><ul><li>Platform Level </li></ul></ul><ul><ul><ul><li>Develop Library for CoWare </li></ul></ul></ul><ul><ul><ul><li>System Control Generator </li></ul></ul></ul><ul><li>Experiments </li></ul><ul><ul><li>Scalar 176*144 </li></ul></ul><ul><ul><li>DWT 44*36 </li></ul></ul><ul><li>Conclusions and Future works </li></ul><ul><li>References </li></ul>
  42. 42. System Control Generator <ul><li>TOP Control Generator </li></ul><ul><ul><li>Input </li></ul></ul><ul><ul><ul><li>Block scheduling </li></ul></ul></ul><ul><ul><ul><li>Block numbers </li></ul></ul></ul><ul><ul><ul><li>Type setting </li></ul></ul></ul><ul><ul><ul><ul><li>Parallel </li></ul></ul></ul></ul><ul><ul><ul><ul><li>Pipeline </li></ul></ul></ul></ul><ul><ul><ul><ul><li>Single (Default) </li></ul></ul></ul></ul><ul><ul><li>Output </li></ul></ul><ul><ul><ul><li>SystemC </li></ul></ul></ul>
  43. 43. Outline <ul><li>Motivation and Contributions </li></ul><ul><li>Previous Works </li></ul><ul><li>Proposed Design Automation Tool from Behavior Level to Transaction Level for Virtual Bus-Based Platforms </li></ul><ul><ul><li>Representation </li></ul></ul><ul><ul><li>Design Flow Overview </li></ul></ul><ul><ul><li>Block Level </li></ul></ul><ul><ul><ul><li>Methodology </li></ul></ul></ul><ul><ul><ul><li>Translation </li></ul></ul></ul><ul><ul><li>Platform Level </li></ul></ul><ul><ul><ul><li>Develop Library for CoWare </li></ul></ul></ul><ul><ul><ul><li>System Control Generator </li></ul></ul></ul><ul><li>Experiments </li></ul><ul><ul><li>Scalar 176*144 </li></ul></ul><ul><ul><li>DWT 44*36 </li></ul></ul><ul><li>Conclusions and Future works </li></ul><ul><li>References </li></ul>
  44. 44. CoWare - Scalar <ul><li>Sequence : Foreman, Football(30 frames) </li></ul>
  45. 45. Simple Bus Environment - Scalar SystemC 2.1 Simple bus Read Transfer Write Transfer
  46. 46. CoWare Environment -Scalar <ul><li>Top Platform for scalar application </li></ul>Step 1 Step2 Step3 Step4 Step 5
  47. 47. Experiments – Scalar <ul><li>Performance with app-time and cycle time </li></ul><ul><li>Scalar performance && State size in Cycle time base </li></ul>100638 100638 325296 Cycle time 91775 91775 239761 Approximate time cycle cycle cycle Cr part Cb part Y part scalar Scalar Y part Parallel constrain 4 33388 115118 0 Communication Cycle 1668 31680 1724 81 11 case 3 1403 31680 9916 78 4 case 2 23 126720 0 0 0 Original C code Code Line Computation Cycle Bus Access ST Size Max cascade
  48. 48. Experiments – Power Monitor <ul><li>Power Library </li></ul><ul><li>Method </li></ul><ul><ul><li>Search the Look up table </li></ul></ul><ul><ul><li>Block -> Module </li></ul></ul><ul><ul><ul><li>FSM switch </li></ul></ul></ul><ul><ul><ul><li>InBuffer </li></ul></ul></ul><ul><ul><ul><li>OutBuffer </li></ul></ul></ul><ul><ul><ul><li>Register </li></ul></ul></ul><ul><ul><li>Block ->Data Path </li></ul></ul><ul><ul><ul><li>Operator </li></ul></ul></ul>Data Path 23.4124 nw 1.0444 mw 8 ADD 21.3216 nW 808.2718 uW 8 SUB 67.5333 nW 4.0100 mW 8 DIV 9.9244 nW 425.8246 uW 8 SHR Size Idle power Active power 66 nw 1.7346mw 32 Buffer 1.7346mw 0.418mw Power power 32 6 width 12 nw FSM 66 nw Register Idle power
  49. 49. Experiments - Scalar <ul><li>Scalar176*144 Power saving </li></ul>2124065.68 423934 1000 101638 WITH PMU 11000089.08 X X 526572 NO PMU Scalar Cb 11000089.08 X X 526572 NO PMU Scalar Cr 14038522.54 199276 1000 326296 WITH PMU Scalar Y 2124065.68 22584673.08 Power mw 423934 1000 101638 WITH PMU X X 526572 NO PMU Sleep Cycle Wake up Cycle Active Cycle Case 18286653.9mw with PMU 44584851.24mw No PMU 58.98% Scalar Power Saving Rate
  50. 50. <ul><li>DWT && IDWT </li></ul>Experiments - DWT DWT IDWT
  51. 51. Experiments - DWT <ul><li>Top Platform for DWT application </li></ul>Step 1 Step 2 Step 3 Step 4
  52. 52. Experiments - DWT <ul><li>Performance with app-time and cycle time </li></ul><ul><li>DWT performance && State size in Cycle time base </li></ul>76262 Cycle time 11088 Approximate time cycle DWT DWT Parallel constrain 1 74678 0 Communication Cycle 8630 1584 9504 42 1 case 1 46 1584 0 0 0 Original C code Code Line Computation Cycle Bus Access ST Size Max cascade
  53. 53. Experiments - DWT <ul><li>DWT 44*36 Power saving </li></ul>2155442.52 68600 1000 76362 WITH PMU 4066501.32 X X 145962 NO PMU DWT IDWT 2105550.72 75362 1000 69600 WITH PMU 4415350.53 X X 145962 NO PMU Power mw Sleep Cycle Interrupt Cycle Active Cycle 4260993.24mw With PMU 8481851.85mw NO PMU 49.765% DWT Power Saving Rate
  54. 54. Outline <ul><li>Motivation and Contributions </li></ul><ul><li>Previous works </li></ul><ul><li>Proposed Design Automation Tool from Behavior Level to Transaction Level for Virtual Bus-Based Platforms </li></ul><ul><ul><li>Representation </li></ul></ul><ul><ul><li>Design Flow </li></ul></ul><ul><ul><li>Block Level </li></ul></ul><ul><ul><ul><li>Methodology </li></ul></ul></ul><ul><ul><ul><li>Translation </li></ul></ul></ul><ul><ul><li>Platform Level </li></ul></ul><ul><ul><ul><li>Develop library </li></ul></ul></ul><ul><ul><ul><li>System Control generator </li></ul></ul></ul><ul><li>Experiments </li></ul><ul><ul><li>Scalar 176*144 </li></ul></ul><ul><ul><li>DWT 44*36 </li></ul></ul><ul><li>Conclusions and Future Works </li></ul><ul><li>References </li></ul>
  55. 55. Conclusions <ul><li>We develop a Automation tool from behavior level CDFG to TLM level SystemC for virtual bus based platform design </li></ul><ul><li>We have also incorporated some method to reduce the Bus Access times for the system design at the Architecture level profiling </li></ul><ul><li>We develop some library for virtual bus based platform </li></ul><ul><li>We can fast explore the Architecture to reduce the verification time </li></ul>
  56. 56. Future Works <ul><li>Model each module’s power using equations so that a more accurate power management could be carried out </li></ul><ul><li>Adding a test platform into the tool so that the corresponding test circuitry could be generated automatically </li></ul><ul><li>Including more hardware architectures to extend the Hardware Library so that designer can have more design options to choose </li></ul>
  57. 57. References <ul><li>[1]S. S. Pasricha, N. Dutt, and M. Ben-Romdhane, &quot;Using TLM for exploring bus-based SoC communication architectures,&quot; 16th IEEE International Conference on Application-Specific Systems, Architecture Processors, 2005, pp. 79-85, 2005 </li></ul><ul><li>[2]C. Lennard and D. Mista, &quot;Taking Design to the System Level,&quot; 2006 [Online]. Available:(http://www.arm.com/pdfs/ARM_ESL_20_3_JC.pdf) </li></ul><ul><li>[3] SPARK Methodology, (http://mesl.ucsd.edu/spark/methodology.shtml) </li></ul><ul><li>[4] S. Gupta, S. Gupta, N. Dutt, R. Gupta, and A. Nicolau, &quot;SPARK: a high-level synthesis framework for applying parallelizing compiler transformations,&quot; Proceedings of 16th International Conference on VLSI Design, 2003 , pp. 461-466, 2003 </li></ul><ul><li>[5] J. Cong, F. Yiping, H. Guoling, J. Wei, and Z. Zhiru, &quot;Platform-Based Behavior-Level and System-Level Synthesis,&quot; in IEEE International SOC Conference, 2006 , pp. 199-202, 2006 </li></ul><ul><li>[6] Ya-Shu Chen, Shih-Chun Chou, Chi-Sheng Shih and Tei-Wei Kuo, &quot;MFASE: Multiple Functions SoCs Analysis Environment,&quot; in the VLSI Design/CAD Symposium, Taiwan, August 2007, 2007 </li></ul>
  58. 58. <ul><li>Thank you </li></ul>
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