State Of FPGA: Current & Future - A Panel discussion @ 4th FPGA Camp
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State Of FPGA: Current & Future - A Panel discussion @ 4th FPGA Camp

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State Of FPGA: Current & Future - A Panel discussion @ 4th FPGA Camp....

State Of FPGA: Current & Future - A Panel discussion @ 4th FPGA Camp.
Moderated by: Dave Orecchio, CEO Gaterocket.
For more details visit http://www.fpgacentral.com/fpgacamp or http://www.fpgacentral.com

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  • Presentation Title
  • FPGAs are growing in complexity at an alarming rate and are now the primary drivers for new process technologies. Today’s FPGAs contain the equivalent logic capacity of a 5 million gate ASIC design plus 30Mb RAM and various IP such as Gigabit I/O, DSP blocks and microprocessors. With this complexity comes new problems for the designer in reaching timing goals quickly and accurately. The physical interconnect (routing) of the FPGA dominates the overall percentage of delay in the circuit. Tools and methodologies have started to appear to address this, but more is needed. Power in FPGAs is also an increasing problem. While big FPGAs are not likely to be the choice for battery-powered applications, the large amounts of FPGA logic along with the routing to support it consumes increasing amounts of power and produce heat. Area optimizations and better utilization of local routing resources improves power On-chip microprocessors and other IP introduces complexity and additional special requirements. A software development environment to support processor-based FPGAs is needed. Xilinx offers Embedded Design Kit (EDK) and Altera offers System Builder for processor-based FPGA design. For verification, Real-time stimulus needed to test functionality Networking, Video/Audio, Processors Classic debug methodologies are failing Iterations in the lab extremely time consuming Too complex to debug with probes & educated guesses False errors more common with gate level debug tools More equivalence checking Faster than simulation Guarantees logical equivalence

State Of FPGA: Current & Future - A Panel discussion @ 4th FPGA Camp State Of FPGA: Current & Future - A Panel discussion @ 4th FPGA Camp Presentation Transcript

  • State of FPGA: Current & Future
    • Agenda:
    • Introduce panelists
    • Panelists position on FPGAs current & future
    • Q&A
    © FPGACentral.com – World’s 1 st FPGA Portal
  • Dave Orecchio
    • President & CEO
    • Dave is President and CEO of GateRocket, Inc. He has 28 years of semiconductor industry experience with a focus on ASIC and FPGA design and development.  Prior to GateRocket, Dave held executive positions in marketing, sales and general management at LTX, Viewlogic Systems, Synopsys, Innoveda, Parametric Technologies and DAFCA.
  • Mark Gustlin’s Biography
    • Principal Engineer in the Routing business unit at Cisco Systems.
    • Mark is responsible for the definition and development of high end routers at Cisco. He is an active participant in the IEEE and the Interlaken interface community. Mark was one of the editors and active participants in the recently released 802.3ba standard (100GE and 40GE). Mark has over 20 years of experience in data and telecom system development. Mark holds a B.S. in Electrical Engineering from San Jose State University.
    © FPGACentral.com – World’s 1 st FPGA Portal
  • Gordon Hands’ Biography
    • Director of Marketing for Lattice’s Low Density and Mixed Signal Solutions,
    • Gordon is participating in the definition of Lattice’s next-generation programmable device technologies. Gordon has been involved in the definition and launch of the LatticeECP/ECP2/ECP2M FPGA families, the LatticeXP/XP2 non-volatile FPGAs, the MachXO/XO2 family of programmable logic devices and the ultra low power 4000ZE CPLD family. Prior to joining Lattice, Hands worked in system design for four years. He has an M.B.A. from Arizona State University and a B.Eng. from the University of Birmingham, England.
  • Daniel Platzker’s Biography
    • FPGA Synthesis Product Line Director
    • Daniel started his career as a hardware engineer developing state-of-the-art hardware modeling systems at Daisy Systems, a pioneering EDA company in the 1980’s. He moved on to technical and management positions with responsibility over EDA tools for programmable devices, and for Daisy’s proprietary hardware behavioral language. In the years between Daisy and joining Mentor Graphics, Platzker gained extensive experience in the management of high tech companies, including being the founder and CEO of Tegrity, an e-learning company. Over the last 20 years, Platzker has held executive positions in marketing, engineering, sales and operations in several high-tech organizations, including the Israeli Department of Defense, Daisy, Tegrity, Castelle and BackWeb. Platzker holds patents in image processing applications and is a winner of the prestigious Israeli Prime Minister Award for product innovation. Platzker is a cum laude graduate of Technion's School of Electrical Engineering, Israel, and earned a master's degree in engineering management from Santa Clara University, CA.
    © FPGACentral.com – World’s 1 st FPGA Portal
  • Chris Eddington’s Biography
    • Chris has over 20 years of experience in ASIC and FPGA design for communications and multimedia products. His previous role was Technical Marketing Director for high speed networking ICs at Mellanox Technologies and prior to that had various roles as leading IC design for VOIP processors, video conferencing ICs, and wireless communications systems. He holds a MS engineering degree from the University of Southern California and an undergraduate degree in Physics and Math from Principia College.
    Chris Eddington Product Marketing Director High-level Synthesis Products Synopsys, Inc
  • Umar Mughal’s Biography
    • Senior Marketing Manager, Broadcast BU
    • Background:
      • 11+ years in the PLD industry
      • Recently Managed the Low Cost Products Marketing team at Altera
      • Prior to this he held a variety of roles in marketing and applications at Xilinx
      • Holds a BSEE from Purdue University
  • Panelists Positions on FPGAs, Current & Future © FPGACentral.com – World’s 1 st FPGA Portal
  • Mark’s Position on FPGAs
    • FPGAs have a bright future, but I have some concerns:
    • Soft error rates are troubling, mainly on the configuration SRAMs
    • Power densities of high end FPGAs coupled with low max junction temps are challenging
    • We need better tools for SerDes based FPGA designs
      • Need better visibility into what is happening within a SerDes macro
      • Better ways to tune or sweep SerDes settings between devices
    • What is the next SerDes speed, 10-12G becoming mainstream, is the next speed 25G?
      • What distance can we achieve on chip to chip interfaces with 25G?
      • Is 25G going to be power efficient?
    © FPGACentral.com – World’s 1 st FPGA Portal
  • Gordon’s position on FPGAs
    • The industry is healthy and vibrant
      • $4.8B in 2010
      • $5.9B in 2014*
    • Race to 1 million LUTs has stretched single architecture approach past breaking point
      • New opportunities are emerging for power and cost optimization
    • Mobile consumer emerging as significant market for PLDs
    • FPGAs continue to capture ASIC and ASSP applications
      • Industry grappling with Microcontroller integration
    * iSuppli Core Silicon Market Tracker Dec 2010
  • Daniel’s position on FPGAs
    • The line between FPGA and ASIC is blurring
      • Future: the line between HW and SW will also blur
    • More players (Achronix, Tabula)
      • Future: Expect to see more niche vendors
    • EDA & FPGA vendor tools co-opetition
      • Future: Both are important - will continue to co-exist
    • FPGA vendor independence (V.I.) is important
      • Future: More V.I. methodologies & higher abstraction levels
    • Application-specific devices and tools
      • Future: Greater demand for complete, industry-specific solutions
    4th FPGA Camp - Mentor Graphics Panel Slides
  • Chris’s position on FPGAs
    • FPGAs growing huge in capacity and complexity and design requirements can’t be met by RTL methodologies alone
      • But you can’t ignore RTL tools – they remain critical to success
    • Next generation FPGAs are basically System-on-Chip requiring more high-level and system-level design tool adoption
    • User will want/need more than ever:
      • High quality IP
      • Improved RTL flows that include fast logic synthesis “modes”, hierarchical and incremental synthesis methodologies
      • Higher-level design flows including high-level synthesis, high-level IP, and system modeling
  • Umar’s position on FPGAs
    • FPGAs are a processing engine, similar to CPUs and DSPs in many ways. Their inherent programmability makes them a superb platform for customers who experience product architecture risk – which is nearly everyone.
    • Like other programmable processing engines, FPGAs have migrated to the heart of the system design in many applications. From there, they have the opportunity to integrate other, less strategic circuits, becoming the gravitational force for the future FPGA-based SOC.
  • Questions & Answers © FPGACentral.com – World’s 1 st FPGA Portal