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Memory Interfaces & Controllers - Sandeep Kulkarni, Lattice
Memory Interfaces & Controllers - Sandeep Kulkarni, Lattice
Memory Interfaces & Controllers - Sandeep Kulkarni, Lattice
Memory Interfaces & Controllers - Sandeep Kulkarni, Lattice
Memory Interfaces & Controllers - Sandeep Kulkarni, Lattice
Memory Interfaces & Controllers - Sandeep Kulkarni, Lattice
Memory Interfaces & Controllers - Sandeep Kulkarni, Lattice
Memory Interfaces & Controllers - Sandeep Kulkarni, Lattice
Memory Interfaces & Controllers - Sandeep Kulkarni, Lattice
Memory Interfaces & Controllers - Sandeep Kulkarni, Lattice
Memory Interfaces & Controllers - Sandeep Kulkarni, Lattice
Memory Interfaces & Controllers - Sandeep Kulkarni, Lattice
Memory Interfaces & Controllers - Sandeep Kulkarni, Lattice
Memory Interfaces & Controllers - Sandeep Kulkarni, Lattice
Memory Interfaces & Controllers - Sandeep Kulkarni, Lattice
Memory Interfaces & Controllers - Sandeep Kulkarni, Lattice
Memory Interfaces & Controllers - Sandeep Kulkarni, Lattice
Memory Interfaces & Controllers - Sandeep Kulkarni, Lattice
Memory Interfaces & Controllers - Sandeep Kulkarni, Lattice
Memory Interfaces & Controllers - Sandeep Kulkarni, Lattice
Memory Interfaces & Controllers - Sandeep Kulkarni, Lattice
Memory Interfaces & Controllers - Sandeep Kulkarni, Lattice
Memory Interfaces & Controllers - Sandeep Kulkarni, Lattice
Memory Interfaces & Controllers - Sandeep Kulkarni, Lattice
Memory Interfaces & Controllers - Sandeep Kulkarni, Lattice
Memory Interfaces & Controllers - Sandeep Kulkarni, Lattice
Memory Interfaces & Controllers - Sandeep Kulkarni, Lattice
Memory Interfaces & Controllers - Sandeep Kulkarni, Lattice
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Memory Interfaces & Controllers - Sandeep Kulkarni, Lattice

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  • 1. Memories; interfaces & controllers Sandeep Kulkarni Area Technical Manager g
  • 2. Memory Types SRAM  Does not req ire refresh access is require refresh, easier. Special types based on access methods. Used for faster Volatile access and low power DRAM  Dynamic RAM, requires periodic refreshing. Uses transistor and capacitor to store charge. Is compact and denser Digital Di it l Memory EEPROM  Byte erasable, limited write cycles, faster read, ser/parallel NonVolatile  NOR & NAND type block erase type, erase, FLASH lower cost, denser,ser/parallel
  • 3. SRAM sub-types & applications • upto32Mb, fast 8ns Async • Upto 333Mhz, QDRII concurrent R/W,burst R/W burst support, DDR data • Sync/Async,250Mhz SRAM FIFO DPRAM/MPM • Random access, upto access 200Mhz • Associative returns Associative, CAM address based on data search
  • 4. SDRAM memory subtypes SDR • Upto 133Mhz,LVCMOS, used in p embedded systems • Upto 200Mhz, SSTL18, source DDR synchronous DDR2 • Upto 400Mhz,SSTL18, diff. strobe. SDRAM DDR3 • Upto 800Mhz,SSTL15,flyby architecture hit t RLDRAM/2 • Reduced latency, 533Mhz, high bandwidth, high density SRAM-like SRAM like random access LPDDR/2 • Lowpower, upto 400Mhz
  • 5. FPGA On Chip Ram • FPGA has primarily 2 types of on-chip RAM p y yp p – Block RAM » SRAM memory block of size 9K/18K/36K » S Supports multiple modes of operation: t lti l d f ti ROM/RAM/DPRAM/FIFO etc. » Parameterisable aspect ratios, cascadable » FAST upto 600Mhz t 600Mh – Distributed RAM » LUT configured as memory:4i/p LUT = 16x1 g y p » Localized Very FAST & efficient » Supports multiple modes of operation: ROM/RAM/DPRAM/FIFO » Cascadable, used for shallow /small memory requirement
  • 6. On chip flash - FlashBAK Technology Make Infinite Reads & Write to Flash During Writes to EBR @ Speeds of Programming up to 350MHz Flash JTAG / SPI EBR PORT FPGA Logic Write From Flash to EBRs During Configuration / Write From EBRs to Flash on User Command • Use FlashBAK to Store: – Error Codes, POST Results, Serial Numbers and uP Code • Erase and Reprogram Flash in <3 seconds • sysMEM EBR 166 to 885Kbits • Unlimited Random Read and Write Capability through EBR • Other types are SerialTag,UFM etc.
  • 7. Memory in Typical Networking Application
  • 8. Memory Organization – DDR2 Source:Micron
  • 9. Read Cycle – DDR2
  • 10. DDR2 Access Read from memory R df Write t W it to memory • Source Synchronous Data(DQ) from memory is edge aligned w.r.t. strobe(DQS). g g ( Q ) • Data writes to memory have to be centre aligned • Tight timing budget Timing for data valid window budget. at 266MHz ~1ns. Precise timing control is crucial.
  • 11. DDR2 IO implementation • To capture read data properly data strobe alignment has to be performed in the fpga io’s g p pg which should be compensated for PVT and works on wide range of frequency. Multiple techniques exists to accomplish this.
  • 12. DQSDLL+DQSBUF Method • Dedicated circuitry in the IOB takes care of the data strobe alignment READ DQSI SCLK DQSDLL provides digital delay code for PVT compensated 90 degree shift
  • 13. DDR Registers in IOB • The IOB contains DDR registers to perform – DDR to SDR – Half clock transfer – Synchronization & Clock transfer
  • 14. IOB DDR Data Transfer timing diagram
  • 15. Abstraction • Memory Controllers offer abstraction and ease of use to designer • Can be parameterized to support a many types of memories, data width, speed etc. • Takes care of initializing the memory • Tracks the Read/Write and controls Refresh • Takes care of the memory timing requirements • Offers a complete data/command/add interface to user for integration in the design. • Command queuing and command burst improves bus tili ti b utilization and throughput d th h t • Intelligent bank management to optimize performance
  • 16. Typical DDR Memory Controller Block Diagram
  • 17. Memory Controller User Interface • Local interface signals groups simplify operation – Initialization A I i i li i & Auto Refresh R f h – Command & Addr – Data Write ata te – Data Read • Example command interface p
  • 18. USER Commands & Data R/W Data Write on User Interface USER Commands READ Data on User Interface
  • 19. DDR Memory controller implementation 1. Core generation (Using IPexpress) 2. Simulation (Eval scripts) 3. Implementation (Synthesis & PAR) p ( y ) 4. Result evaluation (Utilization, Static timing) 5. 5 Pinout validation (PCB layout) 6. Backend design
  • 20. Comparison of DDR Memory Standards
  • 21. DDR3 Advantages • Lower Power – 1.5V • Higher Speed – 400MHz ~ 800MHz • Master Reset – Initialization • More Performance – 2x DDR2 • Larger Densities – 8Gb/32GB
  • 22. DDR3 Power Advantage • Supply voltage reduced from 1 8V to1 5V 1.8V to1.5V – More than 15% power saving • Slower core speed – DDR2-800:DDR2 (400MHz) / Core (200MHz) – DDR3-800:DDR3 (400MHz) / Core (100MHz) • Lower I/O buffer power – 34 ohm driver vs. 18 ohm driver (DDR2) • ~25 to 30% lower power than the same performance 25 DDR2
  • 23. DDR3 8n-Prefetch Architecture
  • 24. DDR3 High Speed Signaling • Fly-by routing g • Write and Read Leveling • ZQ Calibration through ZQ resistor • Dynamic ODT for improved WRITE signaling
  • 25. APPENDIX
  • 26. Market Trends-Technology transition Source:iSuppli
  • 27. Market trends-Price per bit Source: Microsoft
  • 28. Key Memory Timing parameters • CAS Latency : CL – The time between sending a column address to the memory and the beginning of the data in response. This is the time it takes to read the first bit of memory from a DRAM with the correct row already open. • ACTIVATE-to-READ or WRITE delay: tRCD – The number of clock cycles required between the opening a row of y q p g memory and accessing columns within it. The time to read the first bit of memory from a DRAM without an active row is TRCD + CL. • PRECHARGE period: tRP – The number of clock cycles required between the issuing of the precharge command and opening the next row. The time to read the first bit of memory from a DRAM with the wrong row open is TRP + TRCD + CL. • ACTIVATE to PRECHARGE delay: tRAS ACTIVATE-to-PRECHARGE – The number of clock cycles required between a bank active command and issuing the precharge command. This is the time needed to internally refresh the row, and overlaps with TRCD. Typically approximately equal to the sum of the previous three numbers. • Others:tRC,tRRD,tRFC,tRTP,tWTR etc.

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