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  • 1. Build It or Buy It - Engineers may be missing what g y g their company actually wants Prepared for FPGA Camp By CJ Clark CEO, Intellitech Corp. , p Ramachandra Gambheer Managing Director Intellitech India Private Ltd. Bangalore May 21, 2010
  • 2. Intellitech Corp. Copyright © Intellitech Corporation 2010 All rights reserved. 2
  • 3. Old methods won’t win customers High-Level Tools show in-system logic levels (“H” and “L” for driving, “0” and “1” for receiving) Copyright © Intellitech Corporation 2010 All rights reserved. 3
  • 4. Manage delivery – don’t risk DDR Interface @ 200- DDR1/2/3 8 Pair @ 3.125Gb/S 535Mhz At-speed Bit Error Rate 8 Pair @ 6.5Gb/S BER design downloaded at Optional time-of-test At-speed MEMBIST-IP MEMBIST IP BERT-IP TX BERT-IP RX BERT-IP TX BERT-IP RX BERT-IP TX BERT-IP RX Sys FPGA SysClk S Clk FPGA FPGA SysClk S Clk Clk JTAG/1149.1 Quick how Quick, fast can you deliver a full at-speed at speed SERDES Test with at-speed DDR and guarantee success? Copyright © Intellitech Corporation 2010 All rights reserved. 4
  • 5. Pre- Pre-engineered Software makes the difference Copyright © Intellitech Corporation 2010 All rights reserved. 5
  • 6. Design Proto Debug Vol. V l PCB T t Test ESS/HASS Functional Repair Field Test Copyright © Intellitech Corporation 2010 All rights reserved. 6 6
  • 7. SystemBIST – Pre-built FPGA Ecosystems CPU or JTAG Mezzanine FPGA w/CPU Altera Xilinx CPLD RESET T WDO O WDI SPI ASH 8 bit Altera Xilinx FLA GPIO/I2C JTAG (in) DC/DC DC/DC Copyright © Intellitech Corporation 2010 All rights reserved. 7
  • 8. Structural test & Standards based Software simplifies tasks Engineers not familiar with the entire system can create complex strategies for FPGA configuration, security, anti-cloning, watchdogs, resets and Built-in-Test outside the anti- Built-in- critical path of Mission mode software development Copyright © Intellitech Corporation 2010 All rights reserved. 8
  • 9. Tool downloads PCB specific Tests to IC A R C H I V E Copyright © Intellitech Corporation 2010 All rights reserved. 9 9
  • 10. Move out of embedded software timelines •Reduces in-house software costs I •Mission Software lightly coupled to N g • reusable FPGA/BIT method through SPI - S P •Less time/cost/skill with Automation Tools H O E •Re-usable Security/Update/Config/BIT U C method S I • 3rd party outsource-able E A • Requires only GUI expertise L S I Y S + S T GUI T Specialist E M All Software Software + SystemBIST Approach Approach Copyright © Intellitech Corporation 2010 All rights reserved. 10
  • 11. Pin Level Diagnostics in the field or repair depot Intellitech Failure map Website w/ SystemBIST FLASH PHY Internet Archive SPI CPU JTAG Diagnostic Results Return to UUT, Email, other FPGA Configuration Copyright © Intellitech Corporation 2010 All rights reserved. 11
  • 12. CEO of Intellitech Corporation since 1988 University of New Hampshire College of Engineering and Physical Science (CEPS) Ph sical Advisory Board (2000 to present) UNH Department of Electrical Engineering IA Board (2000 to present) Chair IEEE 1149.1 JTAG working group from 1996 to present and 2010 editor Active in IEEE 1149.4, 1149.6, 1532, 1500, 1149.7, P1581 and P1687. He is co-inventor on four US patents and over 30 others co inventor He has presented at the USPTO examiner education series, IEEE Lecture series, ITC, BTW, VTS, HOST and DATE. His first job in test was in 1978 with Plantronics/Wilcom.
  • 13. • If further interested to know more and to have a live demo, please get in touch with • ramachandra@intellitech.com Visit www.intellitech.com Thank You