Today's FPGA Ecosystem - Neeraj Varma, Xilinx


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Today's FPGA Ecosystem - Neeraj Varma, Xilinx

  1. 1. Xilinx Overview Neeraj Varma, Country Manager – Sales (India, Australia, New Zealand) May 2010 Page 1
  2. 2. Agenda The Programmable Imperative: The Next Wave Xilinx Product Strategy Technology Roadmap Xilinx in India Page 2
  3. 3. The Programmable Imperative: The Next Wave Page 3
  4. 4. Decline of ASICs, Challenged ASSP Business FPGAs Closing the Gap with ASICs/ASSPs g p ASIC landscape continues to deteriorate With each process node, the ASIC business model is in jeopardy ASSP business model is challenged Suppliers profitability and long term viability is at stake Increasing FPGA penetration by node Excellent FPGA coverage of technology and business Historically the Industry has “Cried Wolf”… y y Now the Industry is Starting to Deliver to Expectations Page 4
  5. 5. FPGA Coverage of ASIC / ASSPs is Growing FPGA Process Node Technology Attribute 90nm 65nm 40nm 28nm Analog Processor System Power Memory Total Cost Gate Count <25% 25%-50% 50%-75% >75% Clock Speed Interface Protocols DSP Capability Pin Count At Each Process Node, FPGAs Address an Increasing % of ASIC/ASSP Designs Source: Xilinx Internal Estimates Page 5
  6. 6. Fiscal Year Revenues $1,825 $568 1997 1998 1999 2000 2001 2002 2003 2004 2005 2006 2007 2008 2009 Page 6
  7. 7. Xilinx Revenue Breakdown Q4 Calendar Year 2009 Revenue by Geography Revenue by End Market Consumer Japan Asia Data & Auto Processing Industrial Pacific & Other Europe 15% 9% 7% 36% 20% 32% 46% 35% North America Communications Source: Xilinx, Inc. Page 7
  8. 8. Programmable Device Market Segment Share Q4 Calendar Year 2009 PLD Segment FPGA Segment Actel L tti Lattice Others: 1% Xilinx 6% 6% 53% 36% 51% 11% 36% Altera All Others Xilinx Altera Xilinx revenues are greater than all other pure-play PLD companies combined. Source: Company reports Latest information available; computed on a 4-quarter rolling basis Page 8 Pag
  9. 9. Xilinx Product Strategy gy Page 9
  10. 10. Xilinx Product Strategy Overview Improve Power / Performance / Price Increase Productivity by riding the leading edge of with Targeted Design process technology Platforms Application Market-Specific Domain-Specific Base Platform Base Platform Provide customers with Raise the starting point for early access to silicon key vertical applications and development tools p at each node Page 10
  11. 11. Targeted Design Platforms Enabling Customers to Innovate Faster Focus on Differentiation Application Communication • Video • AVB C i ti Vid Application Market specific IP, custom tools, custom boards Market‐specific Application pp Embedded • DSP • Connectivity Domain IP, Domain tools, Domain‐specific FMC daughter cards Silicon Family + Base Platform Base IP ISE program, b B IP, base boards b d Page 11
  12. 12. Greater Capacity and Performance at Every Node Virtex-6 Virtex-5 ormance LXT LX SXT Virtex-4 LXT HXT SXT LX Perfo SX FXT FX TXT Spartan-6 Spartan-3 3 LX 3E LXT 3A/N 3ADSP 90nm 65nm 45/40nm Over 1Tbps IO bandwidth Page 12
  13. 13. ARM and Xilinx Collaboration is a Key Enabler Optimized interconnect Industry s Industry’s best embedded standard for FPGAs processor roadmap and – Next-generation AMBA FPGA fabric Enables Socketable IP Embedded Processing Platform Robust ecosystem of tools, IP and programmers ARM Connected Communityy and Xilinx Partners Page 13
  14. 14. Enabling a Vibrant Ecosystem Open, standards-based platforms Licensing / IP protection New business models Page 14
  15. 15. Unparalleled Support, Training and Services Helps You Accelerate FPGA Projects Most services available in India – delivered through local resources Page 15
  16. 16. Technology Roadmap gy p Page 16
  17. 17. Strategy for Sustained Leadership Ride the leading d Rid th l di edge Continued innovation C ti di ti of process technology beyond silicon Unified, power-efficient architecture Page 17
  18. 18. Unified Architecture at 28nm and Beyond 28nm Gen IP Virtex-6 Virtex-5 LXT LX SXT Virtex-4 LXT HXT SXT LX FXT SX FX TXT Spartan-6 Spartan-3 3 LX IP 3E LXT 3A/N 3ADSP 90nm 65nm 45/40nm 28nm Unified Architecture Enables Design and IP Migration Across Families Page 18
  19. 19. Major Focus on Power Reduction at 28nm 1.0 duction 0.8 Relative Power Red 0.6 50% power 0.4 reduction 50% add’l power dd’l 0.2 reduction 90nm 65nm 40nm / 45nm 28nm Page 19
  20. 20. Rapid Progress on 28nm Rigorous Test Vehicle Development Methodology – Confirm product power, functionality, and performance targets 2010 delivery – Software support in mid 2010 mid-2010 – Initial silicon samples in 2010 Page 20
  21. 21. Productivity Improvements in ISE ISE 12.1 (Now!) – Reduced run time Implementation Runtime Runtime for large designs (hrs) 3.8 Normalized to ISE 11.1 24 – Power reduction capability 18 – Design partitioning support 12 2.1 – P ti l Partial reconfiguration 1.0 6 0.7 – Spartan-6 and 330K 330K 330K 330K 330K LCs LCs LCs LCs Virtex-6 QoR LCs 2007 2008 2009 2010 2011 enhancements ISE9.1i ISE10.1 ISE11.1 ISE12.1 Page 21
  22. 22. Xilinx in India Page 22
  23. 23. Expansion of India Development Centre Technical Support Centre – Investments aligned with growing needs of local customer base fl l t b Robust engineering resources – Key contributor to delivery of current and next generation Targeted Design Platforms – IC Design, IP, SW, systems and application development pp p Doubled workforce in last 12 months – Tapping into rich local talent pool – Increasing employee base to 260 g p y Expanding facility – 57,000 sq. ft. total available space – Capacity for up to 456 employees Page 23
  24. 24. Thriving India Ecosystem Leading technology developers for digital convergence – 15 Alliance member companies • IP, design services, EDA, boards – Joint go-to-market programs – Fertile partnership opportunities Key Xilinx vertical solutions delivered by partners in India Establishing scalable and robust 3rd party partner business models Active Xilinx University Program (XUP) – 500 engineering institutes in India and growing – Best practices exchange between universities in India & abroad Page 24
  25. 25. The Programmable Imperative is Here Today Insatiable bandwidth FPGA price/performance/power improving at each node Xilinx is a Fewer ASSPs to choose from, strategic ASICs too risky choice Increasing productivity with Targeted Design Platforms and Xilinx Support Page 25
  26. 26. Thank You Page 26