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DESIGN CHOICES FOR EMBEDDED REAL-TIME CONTROL SYSTEMS @ 4th FPGA Camp
DESIGN CHOICES FOR EMBEDDED REAL-TIME CONTROL SYSTEMS @ 4th FPGA Camp
DESIGN CHOICES FOR EMBEDDED REAL-TIME CONTROL SYSTEMS @ 4th FPGA Camp
DESIGN CHOICES FOR EMBEDDED REAL-TIME CONTROL SYSTEMS @ 4th FPGA Camp
DESIGN CHOICES FOR EMBEDDED REAL-TIME CONTROL SYSTEMS @ 4th FPGA Camp
DESIGN CHOICES FOR EMBEDDED REAL-TIME CONTROL SYSTEMS @ 4th FPGA Camp
DESIGN CHOICES FOR EMBEDDED REAL-TIME CONTROL SYSTEMS @ 4th FPGA Camp
DESIGN CHOICES FOR EMBEDDED REAL-TIME CONTROL SYSTEMS @ 4th FPGA Camp
DESIGN CHOICES FOR EMBEDDED REAL-TIME CONTROL SYSTEMS @ 4th FPGA Camp
DESIGN CHOICES FOR EMBEDDED REAL-TIME CONTROL SYSTEMS @ 4th FPGA Camp
DESIGN CHOICES FOR EMBEDDED REAL-TIME CONTROL SYSTEMS @ 4th FPGA Camp
DESIGN CHOICES FOR EMBEDDED REAL-TIME CONTROL SYSTEMS @ 4th FPGA Camp
DESIGN CHOICES FOR EMBEDDED REAL-TIME CONTROL SYSTEMS @ 4th FPGA Camp
DESIGN CHOICES FOR EMBEDDED REAL-TIME CONTROL SYSTEMS @ 4th FPGA Camp
DESIGN CHOICES FOR EMBEDDED REAL-TIME CONTROL SYSTEMS @ 4th FPGA Camp
DESIGN CHOICES FOR EMBEDDED REAL-TIME CONTROL SYSTEMS @ 4th FPGA Camp
DESIGN CHOICES FOR EMBEDDED REAL-TIME CONTROL SYSTEMS @ 4th FPGA Camp
DESIGN CHOICES FOR EMBEDDED REAL-TIME CONTROL SYSTEMS @ 4th FPGA Camp
DESIGN CHOICES FOR EMBEDDED REAL-TIME CONTROL SYSTEMS @ 4th FPGA Camp
DESIGN CHOICES FOR EMBEDDED REAL-TIME CONTROL SYSTEMS @ 4th FPGA Camp
DESIGN CHOICES FOR EMBEDDED REAL-TIME CONTROL SYSTEMS @ 4th FPGA Camp
DESIGN CHOICES FOR EMBEDDED REAL-TIME CONTROL SYSTEMS @ 4th FPGA Camp
DESIGN CHOICES FOR EMBEDDED REAL-TIME CONTROL SYSTEMS @ 4th FPGA Camp
DESIGN CHOICES FOR EMBEDDED REAL-TIME CONTROL SYSTEMS @ 4th FPGA Camp
DESIGN CHOICES FOR EMBEDDED REAL-TIME CONTROL SYSTEMS @ 4th FPGA Camp
DESIGN CHOICES FOR EMBEDDED REAL-TIME CONTROL SYSTEMS @ 4th FPGA Camp
DESIGN CHOICES FOR EMBEDDED REAL-TIME CONTROL SYSTEMS @ 4th FPGA Camp
DESIGN CHOICES FOR EMBEDDED REAL-TIME CONTROL SYSTEMS @ 4th FPGA Camp
DESIGN CHOICES FOR EMBEDDED REAL-TIME CONTROL SYSTEMS @ 4th FPGA Camp
DESIGN CHOICES FOR EMBEDDED REAL-TIME CONTROL SYSTEMS @ 4th FPGA Camp
DESIGN CHOICES FOR EMBEDDED REAL-TIME CONTROL SYSTEMS @ 4th FPGA Camp
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DESIGN CHOICES FOR EMBEDDED REAL-TIME CONTROL SYSTEMS @ 4th FPGA Camp

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DESIGN CHOICES FOR EMBEDDED REAL-TIME CONTROL SYSTEMS @ 4th FPGA Camp. Endric Schubert, Missing Link Electronics …

DESIGN CHOICES FOR EMBEDDED REAL-TIME CONTROL SYSTEMS @ 4th FPGA Camp. Endric Schubert, Missing Link Electronics
Glenn Steiner, Xilinx
Visit http://www.fpgacentral.com/fpgacamp for details

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  • readable!
  • mention: multiple boards w/ multiple processors – but expensive
  • exception handling, with embedded micro-processors
  • mention Linux and ANDROID
  • ARM SITARA
  • TI Sitara – AM 1810 – ARM 9
  • Transcript

    • 1. Design Choices for Embedded Real-Time Control Systems
      FPGA Camp, April 6, 2011
      Endric Schubert, Missing Link Electronics
      Glenn Steiner, Xilinx
      4/6/2011
      1
      FPGA Camp 2011
    • 2. Real-Time Closed-Loop Control Systems
      4/6/2011
      2
      FPGA Camp 2011
    • 3. Embedded Real-Time Control Systems- A Quadruple Whammy
      Wide variety of I/O
      Processing in Real-Time
      Safety Regulations
      Device Obsolescence
      4/6/2011
      FPGA Camp 2011
      3
    • 4. Processing Steps in Real-Time Control Systems
      4/6/2011
      4
      FPGA Camp 2011
      An I/O connectivity problem
      Processing problem
      Customization problem
      Processing problem
      Reliability problem
      Another I/O Connectivity problem
    • 5. Real-Time Processing on a Microcontroller
      Like packet / video streaming …
      BUT: must not loose any data!
      4/6/2011
      FPGA Camp 2011
      5
    • 6. Scalability Problems in Multi-Channel Systems
      4/6/2011
      6
      FPGA Camp 2011
    • 7. Von Neumann Needs a Companion!
      Sequential Processing with CPU
      C, C++ Program
      Parallel Processing with Logic Gates
      VHDL, Verilog "Program"
      4/6/2011
      FPGA Camp 2011
      7
      Courtesy: Dr. Andre DeHon, UPenn
    • 8. Proposal: FPGA-Based Real-Time Control System
      4/6/2011
      8
      FPGA Camp 2011
      How to do:
      I/O connectivity (read sensors, drive actuators)
      Signal conditioning
      Closed-loop control
    • 9. FPGA I/O Interfaces & Communication Peripherals
      Covers almost all relevant I/O standards
      And CommunicationInterfaces
      4/6/2011
      9
      FPGA Camp 2011
    • 10. FPGA-Based Signal Conditioning
      4/6/2011
      10
      FPGA Camp 2011
      Today: Digital Signal Processing
      Old School: Analog
    • 11. Closed-Loop PID Control
      4/6/2011
      11
      FPGA Camp 2011
      Courtesy: Dr. GiulioCorradi, Xilinx
    • 12. PID Control in an FPGA
      Delay Optimized
      Area Optimized
      4/6/2011
      FPGA Camp 2011
      12
      Zhao et al.: FPGA Implementation of Closed-Loop Control System for Small Scale Robot, IEEE, July 2005
    • 13. Scale-up Multi-Channel Control with Parallel Processing in the FPGA
      4/6/2011
      13
      FPGA Camp 2011
    • 14. The Need to Run (Sequential) Software
      4/6/2011
      14
      FPGA Camp 2011
    • 15. History Lesson: FPGAs Continue to Evolve to Meet Processing System Requirements
      Co-processing
      EmbeddedProcessing
      ComplexControl
      Increasing FPGA Capability
      Processors tightly coupled
      to FPGA fabric
      enable extendibility with
      co-processing to meet
      real-time system requirements
      Control
      Logic
      Glue
      Logic
      2011
      1985
      1990
      1995
      2000
      4/6/2011
      15
      FPGA Camp 2011
    • 16. Yesterday’s FPGA Designs
      Hardware-Centric Design Flow With FPGAs
      4/6/2011
      FPGA Camp 2011
      16
    • 17. It's the Software, Dude!Embedded Processing Today
      Software-Centric Design Flow With FPGAs
      4/6/2011
      FPGA Camp 2011
      17
    • 18. FPGA-to-CPU Connectivity
      Companion Chips
      Integrated Solutions
      "A symbiosis of CPU and FPGA on one die to reduce cost and PCB space!"
      4/6/2011
      18
      FPGA Camp 2011
    • 19. A Convergence of Processing Solutions
      General Purpose
      Processors
      FPGA Soft
      Processors
      ASSP
      Processors
      FPGA Hard
      Processors
      4/6/2011
      19
      FPGA Camp 2011
    • 20. A Convergence of Processing Solutions
      Extensible
      Processing
      Platform
      General Purpose
      Processors
      FPGA Soft
      Processors
      Memory
      Interfaces
      7 Series
      ProgrammableLogic
      ProcessingSystem
      Common
      Peripherals
      Common Peripherals
      Custom
      Peripherals
      ARM®
      Dual Cortex-A9 MPCore™ System
      Common Accelerators
      Custom Accelerators
      ASSP
      Processors
      FPGA Hard
      Processors
      4/6/2011
      20
      FPGA Camp 2011
    • 21. Zynq-7000 Extensible Processing Platform
      • Complete ARM®-based Processing System
      • 22. Dual ARM Cortex™-A9 MPCore™, processor centric
      • 23. Integrated memory controllers & peripherals
      • 24. Fully autonomous to the Programmable Logic
      • 25. Tightly Integrated Programmable Logic
      • 26. Used to extend Processing System
      • 27. Scalable density and performance
      • 28. Over 3000 internal interconnects
      • 29. Flexible Array of I/O
      • 30. Wide range of external multi-standard I/O
      • 31. High performance integrated serial tranceivers
      • 32. Analog-to-Digital Converter inputs
      Memory
      Interfaces
      7 Series
      ProgrammableLogic
      ProcessingSystem
      Common
      Peripherals
      Common Peripherals
      Custom
      Peripherals
      ARM®
      Dual Cortex-A9 MPCore™ System
      Common Accelerators
      Custom Accelerators
      Software & Hardware Programmable
      4/6/2011
      21
      FPGA Camp 2011
    • 33. Zynq-7000 Extensible Processing System
      Processing System
      Dynamic Memory Controller
      DDR3, DDR2, LPDDR2
      Static Memory Controller
      Quad-SPI, NAND, NOR
      Programmable
      Logic:
      System Gates,
      DSP, RAM
      AMBA® Switches
      AMBA® Switches
      2x SPI
      ARM® CoreSight™ Multi-core & Trace Debug
      2x I2C
      NEON™/ FPU Engine
      NEON™/ FPU Engine
      2x CAN
      Cortex™-A9 MPCore™
      32/32 KB I/D Caches
      2x UART
      Cortex™-A9 MPCore™
      32/32 KB I/D Caches
      MIO
      I/O
      MUX
      GPIO
      512 KB L2 Cache
      Snoop Control Unit (SCU)
      Multi-Standards I/Os (3.3V & High Speed 1.8V)
      ACP
      2x SDIO
      with DMA
      Timer Counters
      256 KB On-Chip Memory
      DMA
      General Interrupt Controller
      Configuration
      2x USB
      with DMA
      2x GigE
      with DMA
      AMBA® Switches
      AMBA® Switches
      PCIe
      AMS
      Multi-Standards I/Os (3.3V & High Speed 1.8V)
      Multi Gigabit Transceivers
      4/6/2011
      22
      FPGA Camp 2011
    • 34. Zynq-7000 EPP Processors
      Processing System
      Dynamic Memory Controller
      DDR3, DDR2, LPDDR2
      Static Memory Controller
      Quad-SPI, NAND, NOR
      Programmable
      Logic:
      System Gates,
      DSP, RAM
      AMBA® Switches
      AMBA® Switches
      2x SPI
      ARM® CoreSight™ Multi-core & Trace Debug
      2x I2C
      NEON™/ FPU Engine
      NEON™/ FPU Engine
      2x CAN
      Cortex™-A9 MPCore™
      32/32 KB I/D Caches
      2x UART
      Cortex™-A9 MPCore™
      32/32 KB I/D Caches
      MIO
      I/O
      MUX
      GPIO
      512 KB L2 Cache
      Snoop Control Unit (SCU)
      Multi-Standards I/Os (3.3V & High Speed 1.8V)
      ACP
      2x SDIO
      with DMA
      Timer Counters
      256 KB On-Chip Memory
      DMA
      General Interrupt Controller
      Configuration
      2x USB
      with DMA
      2x GigE
      with DMA
      AMBA® Switches
      AMBA® Switches
      PCIe
      AMS
      Multi-Standards I/Os (3.3V & High Speed 1.8V)
      Multi Gigabit Transceivers
      4/6/2011
      23
      FPGA Camp 2011
    • 35. Zynq-7000 EPP Memory Interfaces
      Processing System
      Dynamic Memory Controller
      DDR3, DDR2, LPDDR2
      Static Memory Controller
      Quad-SPI, NAND, NOR
      Programmable
      Logic:
      System Gates,
      DSP, RAM
      AMBA® Switches
      AMBA® Switches
      2x SPI
      ARM® CoreSight™ Multi-core & Trace Debug
      2x I2C
      NEON™/ FPU Engine
      NEON™/ FPU Engine
      2x CAN
      Cortex™-A9 MPCore™
      32/32 KB I/D Caches
      2x UART
      Cortex™-A9 MPCore™
      32/32 KB I/D Caches
      MIO
      I/O
      MUX
      GPIO
      512 KB L2 Cache
      Snoop Control Unit (SCU)
      Multi-Standards I/Os (3.3V & High Speed 1.8V)
      ACP
      2x SDIO
      with DMA
      Timer Counters
      256 KB On-Chip Memory
      DMA
      General Interrupt Controller
      Configuration
      2x USB
      with DMA
      2x GigE
      with DMA
      AMBA® Switches
      AMBA® Switches
      PCIe
      AMS
      Multi-Standards I/Os (3.3V & High Speed 1.8V)
      Multi Gigabit Transceivers
      4/6/2011
      24
      FPGA Camp 2011
    • 36. I/O Connectivity in Zynq-7000 EPP
      Processing System
      Dynamic Memory Controller
      DDR3, DDR2, LPDDR2
      Static Memory Controller
      Quad-SPI, NAND, NOR
      Programmable
      Logic:
      System Gates,
      DSP, RAM
      AMBA® Switches
      AMBA® Switches
      2x SPI
      ARM® CoreSight™ Multi-core & Trace Debug
      2x I2C
      NEON™/ FPU Engine
      NEON™/ FPU Engine
      2x CAN
      Cortex™-A9 MPCore™
      32/32 KB I/D Caches
      2x UART
      Cortex™-A9 MPCore™
      32/32 KB I/D Caches
      MIO
      I/O
      MUX
      GPIO
      512 KB L2 Cache
      Snoop Control Unit (SCU)
      Multi-Standards I/Os (3.3V & High Speed 1.8V)
      ACP
      2x SDIO
      with DMA
      Timer Counters
      256 KB On-Chip Memory
      DMA
      General Interrupt Controller
      Configuration
      2x USB
      with DMA
      2x GigE
      with DMA
      AMBA® Switches
      AMBA® Switches
      PCIe
      AMS
      Multi-Standards I/Os (3.3V & High Speed 1.8V)
      Multi Gigabit Transceivers
      4/6/2011
      25
      FPGA Camp 2011
    • 37. Agile Mixed Signal (AMS) for Data Acquisition
      Processing System
      Dynamic Memory Controller
      DDR3, DDR2, LPDDR2
      Static Memory Controller
      Quad-SPI, NAND, NOR
      Programmable
      Logic:
      System Gates,
      DSP, RAM
      AMBA® Switches
      AMBA® Switches
      2x SPI
      ARM® CoreSight™ Multi-core & Trace Debug
      2x I2C
      NEON™/ FPU Engine
      NEON™/ FPU Engine
      2x CAN
      Cortex™-A9 MPCore™
      32/32 KB I/D Caches
      2x UART
      Cortex™-A9 MPCore™
      32/32 KB I/D Caches
      MIO
      I/O
      MUX
      GPIO
      512 KB L2 Cache
      Snoop Control Unit (SCU)
      Multi-Standards I/Os (3.3V & High Speed 1.8V)
      ACP
      2x SDIO
      with DMA
      Timer Counters
      256 KB On-Chip Memory
      DMA
      General Interrupt Controller
      Configuration
      2x USB
      with DMA
      2x GigE
      with DMA
      AMBA® Switches
      AMBA® Switches
      PCIe
      AMS
      Multi-Standards I/Os (3.3V & High Speed 1.8V)
      Multi Gigabit Transceivers
      4/6/2011
      26
      FPGA Camp 2011
    • 38. Agile Mixed Signal (AMS) Processing
      • Dual 12-bit 1 Msps Analog-to-Digital Converters
      • 39. ADCs carry out a 16-bit resolution conversion
      • 40. Factory tested and specified 12-bit accuracy with 1V input range
      • 41. Built in digital gain and offset correction / calibration
      • 42. Dual Independent Track & Hold (T/H) Amplifiers
      • 43. Separate Track/Hold amplifier ensures maximum throughput using multiplexed analog input channels
      • 44. On-chip Voltage Reference
      • 45. External reference input option
      • 46. On-Chip Thermal and Supply Sensors
      • 47. Flexible External Analog Inputs
      • 48. Differential analog inputs with high common mode noise rejection
      • 49. Support for unipolar, bipolar, and true differential input signal types
      4/6/2011
      27
      FPGA Camp 2011
    • 50. On-Chip and External Environmental Monitoring
      Monitoring for higher reliability in industrial applications
      Factory tested on-chip monitoring
      Easier to implement than external solutionse.g., thermal diode monitor
      Counter measures against physical attack / tampering in A&D
      US government mandate: Cryptographic model must have built in counter measures against manipulation of power supplies and operating temperatures
      Protection against reverse engineering and IP theft
      Diagnostics for HW design and verification
      Easy to use JTAG access with ChipScope support
      Especially difficult to access places e.g., in enclosures / cabinets
      JTAG
      4/6/2011
      28
      FPGA Camp 2011
    • 51. Integrating It All Together:An Industrial Motor Control Application
      4/6/2011
      29
      FPGA Camp 2011
    • 52. Put the Burden Where it Fits Best!
      Extensible Processing Platforms
      Allow optimum system partitioning between software and hardware
      Build configurable systems that match your application!
      4/6/2011
      FPGA Camp 2011
      Page 30
    • 53. Modern Implementation
      4/6/2011
      31
      FPGA Camp 2011
      Extensible Processing Platform
      Memory
      Interfaces
      7 Series
      ProgrammableLogic
      ProcessingSystem
      Common
      Peripherals
      Common Peripherals
      Custom
      Peripherals
      ARM®
      Dual Cortex-A9 MPCore™ System
      Common Accelerators
      Custom Accelerators

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