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Howto implement a boolean logic function into hardware silicon? The hardware silicon used in this presentation is an FPGA (Xilinx Spartan3E starter kit). The software used is LabVIEW with the LabVIEW …

Howto implement a boolean logic function into hardware silicon? The hardware silicon used in this presentation is an FPGA (Xilinx Spartan3E starter kit). The software used is LabVIEW with the LabVIEW FPGA module and the SPARTAN3E driver.

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  • Transcript

    • 1. Regeltechniek (LabVIEW) 3pBA EA LabVIEW FPGA Implementing a Boolean function Vincent Claes
    • 2. LabVIEW FPGA
      • This presentation
        • Starting a project
        • Creating a LabVIEW FPGA VI
        • Running the VI from SPARTAN3E Flash
        • Creating a HOST VI that communicates with LabVIEW FPGA VI in Xilinx Spartan3E starter kit
      Vincent Claes
    • 3. Xilinx SPARTAN3E Starter kit
      • Board Information
      • User guide
      Vincent Claes
    • 4. Xilinx SPARTAN3E Starter kit Vincent Claes
    • 5. Xilinx SPARTAN3E Starter kit
      • Xilinx XC3S500E Spartan-3E FPGA
      • Up to 232 user-I/O pins
      • 320-pin FBGA package
      • Over 10,000 logic cells
      • Xilinx 4 Mbit Platform Flash configuration PROM
      • Xilinx 64-macrocell XC2C64A CoolRunner CPLD
      • 64 MByte (512 Mbit) of DDR SDRAM, x16 data interface, 100+ MHz
      • 16 MByte (128 Mbit) of parallel NOR Flash (Intel StrataFlash)
      • FPGA configuration storage
      • MicroBlaze code storage/shadowing
      • 16 Mbits of SPI serial Flash (STMicro)
      • FPGA configuration storage
      • MicroBlaze code shadowing
      • 2-line, 16-character LCD screen
      • PS/2 mouse or keyboard port
      • VGA display port
      • 10/100 Ethernet PHY (requires Ethernet MAC in FPGA)
      • Two 9-pin RS-232 ports (DTE- and DCE-style)
      • On-board USB-based FPGA/CPLD download/debug interface
      • 50 MHz clock oscillator
      • SHA-1 1-wire serial EEPROM for bitstream copy protection
      • Hirose FX2 expansion connector
      • Three Digilent 6-pin expansion connectors
      • Four-output, SPI-based Digital-to-Analog Converter (DAC)
      • Two-input, SPI-based Analog-to-Digital Converter (ADC) with programmable-gain pre-amplifier
      • ChipScope™ SoftTouch debugging port
      • Rotary-encoder with push-button shaft
      • Eight discrete LEDs
      • Four slide switches
      • Four push-button switches
      • SMA clock input
      • 8-pin DIP socket for auxiliary clock oscillator
      Vincent Claes
    • 6. Before you start
      • Install LabVIEW 8.5
      • Install LabVIEW FPGA module
      • Download and install the LabVIEW FPGA for Xilinx SPARTAN-3E XUP Driver (read the license agreement)
      • Connect USB Cable with board
      • Put SWP of board to ON
      Vincent Claes
    • 7. Starting an Empty Project
      • Start LabVIEW 8.5
      • Choose “Empty Project”
      Vincent Claes
    • 8. Project Explorer
      • The Project Explorer window should open
      • Be sure to have a look at the tree of the project
      Vincent Claes
    • 9. Add the SPARTAN3E board as a hardware target to your project
      • Right click on “My computer”
      • Select New
      • Select Targets and Devices
      • A new window should open
      Vincent Claes
    • 10. Select the Spartan-3E Starter Board
      • Click the option “New target or device”
      • Select the “Spartan-3E Starter board” under the “Xilinx University Program” option
      Vincent Claes
    • 11. Project Explorer view
      • Look now at the Project Explorer
      • FPGA Target should be added
      • The next step is to add peripherals to the FPGA target
      Vincent Claes
    • 12. Add FPGA target Peripherals
      • Right click on the FPGA target
      • Select “New”
      • Click FPGA IO (Input/Output Peripherals)
        • You could also add a FIFO or Memory block at this location
      Vincent Claes
    • 13. Adding new FPGA I/O
      • This Window shows all the FPGA I/O of the SPARTAN3E Starter Kit
      • You can click the “+” to have more details
      • Select the I/O you want and push “Add”
      • You should see the FPGA I/O on the right side that you wanted to add
      • Be sure for this exercise to add the LED’s and Slide Switches
      Vincent Claes
    • 14. Project Explorer View
      • In the Project Explorer view you should see all the peripherals you have added
      • Now we are ready to program a VI on the FPGA
      Vincent Claes
    • 15. Create a VI for the FPGA target
      • Right Click on the FPGA target you added
      • Select “New”
      • Select “VI”
      Vincent Claes
    • 16. Overview
      • Project Explorer
      • Front Panel
      • Block Diagram
      Vincent Claes
    • 17. LabVIEW Functions for FPGA targets
      • Memory & FIFO
      • FPGA I/O
      • FPGA Math & Analysis
      Vincent Claes
    • 18. Implementing Boolean logic
      • On the Block diagram you can now add the functions you want to use
      • Be sure to put them into a loop
      Vincent Claes
    • 19. FPGA I/O
      • Next step: getting I/O
      • Select “Functions”
      • “ Programming”
      • “ I/O Node”
      • Place this on the block diagram
      Vincent Claes
    • 20. FPGA I/O
      • Right mouse click
      • You can select and FPGA I/O
      • You can add more I/O’s
      Vincent Claes
    • 21. FPGA I/O
      • For this exercise:
      • Put 2 I/O nodes on the block diagram
      • Select SW0 untill SW3
      • Select LED0 untill LED 3
      • Connect as in the screenshot
      Vincent Claes
    • 22. Indicators on Front Panel
      • If we put Indicators in the code we can watch the value of the wires over the JTAG interface on the Front Panel on our PC
      Vincent Claes
    • 23. Indicators on Front Panel Vincent Claes
    • 24. Running the Example
      • Press the Run arrow
      Vincent Claes
    • 25. Running the Example
      • Be sure to save your VI first otherwise you get this message
      Vincent Claes
    • 26. Compile report
      • After you pressed “Run arrow”
      • The PC start compiling and synthesizing your code
      • When this process is finished you see the Compiler Report
      • You have to press “OK”
      • Now you should see the code running on your FPGA (try it!)
      • And you can watch the indicators on your computer too.
      Vincent Claes
    • 27. To Flash
      • The following slides show you howto put the code into the flash
      • Right click on the FPGA target
      • Select “Properties”
      Vincent Claes
    • 28. To Flash
      • You have to check the option “Run when loaded to FPGA”
      • Otherwise the FPGA will not start running your program when you download it to the Flash
      Vincent Claes
    • 29. To Flash
      • To download the bitfile to the Flash right click on the FPGA VI in the Project Explorer View
      • Select the “Download VI to Flash Memory”
      Vincent Claes
    • 30. To Flash
      • It could happen that this message is appearing
      • You have to recompile
      • This is because you first compiled (synthesized  remember we are talking in hardware not software !!!) and afterwards did the run when loaded setting.
      • So solution: “Recompile it!”
      • When you try the download to Flash option again the is says everything is downloaded successful and you have to see the VI running on the FPGA board.
      Vincent Claes
    • 31. Setting up HOST VI
      • The next slides show you how to create a host VI that communicates with the LabVIEW FPGA VI on the SPARTAN3E Starter board over JTAG interface (“USB Programming Cable”)
      • Click “My Computer”
      • Select “New”
      • Select “VI”
      • Watch where LabVIEW places it in the Project Explorer Tree
      Vincent Claes
    • 32. HOST VI
      • Option for “FPGA Interfacing” on Host VI
      Vincent Claes
    • 33. HOST VI
      • Select “Open FPGA VI Reference”
      • Place in on the Block Diagrom of the HOST VI
      • Right Click on the icon
      • You can choose to “select the FPGA VI” or “Select Bitfile” if you already compiled it.
      Vincent Claes
    • 34. HOST VI
      • This is an example HOST VI
      • Read/Write Control is placed in a Loop
      • You can select all indicators/controls of the FPGA VI from this function
      Vincent Claes
    • 35. HOST VI
      • Create indicators from the Read/Write Control to create indicators on the HOST VI
      Vincent Claes
    • 36. HOST VI
      • Finished HOST VI
      • Now you can run this HOST VI; this is executed on your computer!
      Vincent Claes
    • 37. Running HOST VI  FPGA VI example Vincent Claes
    • 38.
      • Contact information
      • claesvincent @
      Vincent Claes