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Zpu
Zpu
Zpu
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Zpu

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  • 1. Zylin CPU Øyvind Harboe, General Manager, Zylin AS
  • 2. Motivation <ul><li>Provide a 32 bit core with standard tools while taking up a minimum of real estate </li></ul><ul><li>Flexible core and architecture that can be used with any FPGA brand/type, memory and IO subsystem </li></ul><ul><li>Leave FPGA resources to HDL paradigm </li></ul>
  • 3. What the ZPU is not <ul><li>Not ARM9, XScale, etc. type CPU </li></ul><ul><li>Not for sustained processing </li></ul><ul><li>Not for running Linux – no MMU </li></ul><ul><li>Unlikely to run uCLinux </li></ul>
  • 4. ZPU - performance <ul><li>DMIPS – popular performance index for deeply embedded processors </li></ul><ul><li>Easy to measure with working GCC and Dhrystone v2.1 </li></ul><ul><li>1 – 10 DMIPS depending configuration and memory subsystem </li></ul><ul><li>The ZPU is for light administrative tasks </li></ul><ul><li>The ZPU punches above its weight </li></ul><ul><ul><li>Leaves resources to HDL paradigm </li></ul></ul><ul><ul><li>eCos performance tests are relatively better and more relevant </li></ul></ul>
  • 5. ZPU – real estate <ul><li>LUT - FPGA MIPS. A popular index of real estate usage </li></ul><ul><li>Must be measured using actual tools and part </li></ul><ul><li>Xilinx XC3S400 – 440 LUT with 32 bit data path </li></ul>
  • 6. ZPU - codesize <ul><li>80% of ARM7 Thumb. Measured on eCos applications. </li></ul><ul><li>There exists no MIPS equivalent for code size </li></ul>
  • 7. ZPU programming model <ul><li>Standard programming model </li></ul><ul><li>A single linear 32 bit address space </li></ul><ul><li>Unused address bits are optimized away by synthesis optimisation </li></ul><ul><li>IO is memory mapped </li></ul>
  • 8. GCC toolchain <ul><li>GCC </li></ul><ul><li>GDB </li></ul><ul><li>newlib/libgloss – OS less applications </li></ul><ul><li>Zylin Embedded CDT debug GUI </li></ul>
  • 9. SoPC <ul><li>System On a Programmable Chip </li></ul><ul><li>ZPU core running </li></ul><ul><ul><ul><li>eCos </li></ul></ul></ul><ul><ul><ul><li>Applications and drivers (TCP/IP, Flash-file system,...) </li></ul></ul></ul><ul><li>Memory interfaces (Internal/external memory) </li></ul><ul><li>Peripheral interface/controllers </li></ul><ul><ul><ul><li>Ethernet MAC (opencores) </li></ul></ul></ul><ul><ul><ul><li>Standard 16550 or simple UARTs (opencores) </li></ul></ul></ul><ul><ul><ul><li>DDR SDRAM controller (Zylin) </li></ul></ul></ul><ul><ul><ul><li>I2C, USB, SDIO, GPIO....... </li></ul></ul></ul>
  • 10. eCos – RTOS Real Time OS <ul><li>eCos – open source free deeply embedded operating system </li></ul><ul><ul><li>eCos is not Linux </li></ul></ul><ul><ul><li>Small footprint </li></ul></ul><ul><ul><li>TCP/IP </li></ul></ul><ul><ul><li>USB function drivers </li></ul></ul><ul><ul><li>Flash drivers </li></ul></ul><ul><ul><li>GDB stubs – target debugging via simple UART </li></ul></ul><ul><ul><li>The list goes on and on </li></ul></ul><ul><ul><li>eCos is the rising star for deeply embedded </li></ul></ul>
  • 11. eCos HAL <ul><li>A ZPU comes with a variant eCos HAL configured to a ZPU port and peripherals </li></ul><ul><li>Special drivers? Drivers are CPU independent. </li></ul><ul><li>Opencores ethermac driver runs unmodified on SPARC, ARM and the ZPU </li></ul><ul><li>Check eCos repository for your peripherals/driver stack </li></ul>
  • 12. ZPU HDL <ul><li>ZPU's key strength is small footprint </li></ul><ul><li>Starts at 300-500 LUT </li></ul><ul><li>16/32 bit datapath </li></ul><ul><li>Core choice depends on memory and IO subsystem </li></ul><ul><li>Dual port, single port, wishbone, custom </li></ul>
  • 13. Custom ZPU <ul><li>Size optimisation for particular memory and IO subsystem </li></ul><ul><li>More instructions? There are various instructions that can be enabled and disabled without changing compiler or binaries </li></ul><ul><li>Even more instructions? May require GCC support </li></ul><ul><li>Special machine code only instructions? Instructions tightly integrated with peripherals? </li></ul><ul><li>Peripherals? </li></ul>
  • 14. ISS – instruction set simulator <ul><li>Simulates ZPU to run binaries from GCC </li></ul><ul><li>Takes simulator trace output for verification and cycle accurate statistics/debugging </li></ul><ul><li>GDB server interface </li></ul><ul><li>Simple peripheral simulation – timer, UART, etc. </li></ul><ul><li>Does not replace debugging real target </li></ul><ul><li>Custom ZPU verification/profiling </li></ul><ul><li>Early development/training before target PCB is available </li></ul><ul><li>Used for debugging eCos HAL </li></ul>
  • 15. ZPU – roadmap <ul><li>Stay away from 50-500 DMIPS range </li></ul><ul><li>Reduce footprint – obviously not a large potential </li></ul><ul><li>Performance increases without sacrificing area or code density </li></ul><ul><li>Improve code density – possibly at FPGA resource cost, SRAM and flash is real-estate too </li></ul><ul><li>Improve GCC code quality </li></ul><ul><li>Improve debug tools </li></ul><ul><li>Optional peripherals? </li></ul>
  • 16. ZPU – summary <ul><li>1-10 MIPS </li></ul><ul><li>16 or 32 datapath </li></ul><ul><li>Codesize 80% of ARM7 Thumb </li></ul><ul><li>GCC toolchain </li></ul><ul><li>eCos HAL </li></ul><ul><li>Various HDL cores available </li></ul><ul><li>400 LUTs – 32 bit datapath </li></ul>
  • 17. Questions?

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