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IEEE 2011-12 vlsi-vhdl-verilog-low-power-spartan-spartan3-spartan-3 an-matlab-matlab-simultion-vlsi-simulation-l-ive-real-timefinal-year-ieee-projects-2011-2012-for
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IEEE 2011-12 vlsi-vhdl-verilog-low-power-spartan-spartan3-spartan-3 an-matlab-matlab-simultion-vlsi-simulation-l-ive-real-timefinal-year-ieee-projects-2011-2012-for

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PANTECH SOLUTIONS Provides Project Guidance for B.E,B.Tech,M.E,M.Tech,MCA,B.Sc & M.Sc Electronic Science and for all Electrical Students …

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  • 1. VLSI email:vlsi@pantechmail.com SI.No Topics Field IEEE 2010 (Image Processing ,System IEEE 2011 (Low Power Design, Image Processing, System GeneratorPSVLS 1 New Adaptive Weight Algorithm For Salt & Pepper Noise Removal (2011C)PSVLS 2 Removal Of High Density Salt & Pepper Noise Through Modified Decision Based Un- Symmetric Trimmed Median FilterPSVLS 3 Operation Improvement Of Indoor Robot By Gesture RecognitionPSVLS 4 Adiabatic Technique For Energy Efficient Logic Circuits DesignPSVLS 5 Enhancing Efficiency In SRAM Arrays Through Recovery BoostingPSVLS 6 Design And FPGA Implementation Of Modified Distributive Arithmetic Based DWT – IDWT ,Signal Processing) Processor For Image CompressionPSVLS 7 Enhancing NBTI Recovery In SRAM Arrays Through Recovery BoostingPSVLS 8 Optimization Of Processor Architecture For Image Edge Detection FilterPSVLS 9 Design And Analysis Of Two Low-Power SRAM Cell StructuresPSVLS 10 A Novel Column-Decoupled 8T Cell For Low-Power Differential And Domino-Based SRAM DesignPSVLS 11 CMOS Full-Adders For Energy-Efficient Arithmetic ApplicationsPSVLS 12 Pipelined Architecture For FPGA Implementation Of Lifting-Based DWTPSVLS 13 Parallel Architecture For Hierarchical Optical Flow Estimation Based On FPGAPSVLS 14 A VLSI Architecture Of SVC Encoder For Mobile SystemPSVLS 15 Variability Resilient Low-Power 7T-SRAM Design For Nano - Scaled Technologies (2010C)PSVLS 16 Design And Implement Of The Embedded Elevator Monitor System Based On Wireless Generator ,Signal Processing) CommunicationPSVLS 17 A real time implementation of Finger- Robot interaction using FPGAPSVLS 18 Power Estimation Of Embedded Multiplier Blocks In FPGAsPSVLS 19 Flexible Hardware Architecture Of Hierarchical K-Means Clustering For Large Cluster NumberPSVLS 20 Keyless Car Entry Through Face Recognition Using FPGAPSVLS 21 An FPGA-Based Architecture For Linear And Morphological Image FilteringPSVLS 22 Image Edge Detection Based On FPGAPSVLS 23 Ground Bounce Noise Reduction Of Low Leakage 1-Bit Nano - CMOS Based Full Adder Cells For Mobile ApplicationsPSVLS 24 Design Of A Low Power Flip-Flop Using CMOS Deep Submicron Technology IEEE 2011PSVLS 25 Low-Power And Area-Efficient Carry Select AdderPSVLS 26 A Pipeline VLSI Architecture For High-Speed Computation Of The 1-D Discrete Wavelet TransformPSVLS 27 FPGA Based Inexpensive Automobile Refuge SystemPSVLS 28 SIM Card Based Smart Banking Using FPGAwww.pantechsolutions.net | ©2011Pantech Solutions Pvt Ltd | www.pantechprojects.com 21
  • 2. VLSI email:vlsi@pantechmail.com Reconfigurable Hardware For Median Filtering For Image Processing Applications IEEE 2011 (Low Power Design, Image Processing, System Generator, Signal Processing)PSVLS 29PSVLS 30 Design Of FFT Processor Based On FPGAPSVLS 31 A Color Image Segmentation Based On Region GrowingPSVLS 32 Message Encoding In Images Using Lifting SchemesPSVLS 33 Dual Stack Method: A Novel Approach To Low Leakage And Speed Power Product VLSI DesignPSVLS 34 Standby Leakage Power Reduction Technique For Nano - scale CMOS VLSI SystemsPSVLS 35 Implementation Of Convolutional Encoder And Viterbi Decoder Using VHDLPSVLS 36 An FPGA Implementation Of The Time Domain Deadbeat Algorithm For Control ApplicationsPSVLS 37 A New VLSI Architecture Of Parallel Multiplier–Accumulator Based On Radix-2 Modified Booth AlgorithmPSVLS 38 A High Performance Binary To BCD Converter For Decimal MultiplicationPSVLS 39 A Wide-Range All-Digital Delay-Locked Loop In 65nm CMOS TechnologyPSVLS 40 Motion Human Detection Based On Background SubtractionPSVLS 41 System Level Simulation Guided Approach To Improve The Efficacy Of Clock-GatingPSVLS 42 Design And Sensitivity Analysis Of A New Current-Mode Sense Amplifier For Low-Power SRAMPSVLS 43 An Enhanced Railway Transport System Using FPGA Through GPS & GSMPSVLS 44 Design Of Low-Power High-Speed Truncation-Error-Tolerant Adder And Its Application In Digital Signal ProcessingPSVLS 45 Adaptive 2-D Wavelet Transform Based On The Lifting Scheme With Preserved Vanishing MomentsPSVLS 46 System Level Simulation Guided Approach To Improve The Efficiency Of Clock-GatingPSVLS 47 An Integrated Library Management System For Book Search And Placement Tasks IEEE 2011PSVLS 48 Energy-Efficient Design Methodologies: High-Performance VLSI AddersPSVLS 49 FPGA-Based Implementation Of A Low Cost And Area Real-Time Motion DetectionPSVLS 50 Design And Implementation Of Different Multipliers Using VHDLPSVLS 51 Hellfire: A Design Framework For Critical Embedded Systems’ ApplicationsPSVLS 52 FPGA-Based GPS Application System Design IEEE 2011 (Low PowerPSVLS 53 Performance Evaluation Of DES And Blowfish Algorithms Design, Image Processing)PSVLS 54 A New And Efficient Algorithm For The Removal Of High Density Salt And Pepper Noise In Images And VideosPSVLS 55 Flexible Hardware Architecture Of Hierarchical K-Means Clustering For Large Cluster NumberPSVLS 56 GPS-GSM Based Bus Stop Automationwww.pantechsolutions.net | ©2011Pantech Solutions Pvt Ltd | www.pantechprojects.com 22
  • 3. VLSI email:vlsi@pantechmail.comPSVLS 57 Low-Power Leading-Zero Counting And Anticipation Logic For High-Speed Floating Point Units (Verilog)PSVLS 58 Comprehensive Analysis And Control Of Design Parameters For Power Gated CircuitsPSVLS 59 Design & Implementation Of A Low Power Differential AmplifierPSVLS 60 VLSI Implementation Of WIMAX Convolutional Code Encoder And DecoderPSVLS 61 An Optimized Tag Sorting Circuit In WFQ Scheduler Based On Leading Zero CountingPSVLS 62 Removal Of Sign-Extension Circuitry From Booths Algorithm Multiplier-AccumulatorsPSVLS 63 Design Optimization Of FPGA Based Viterbi DecoderPSVLS 64 A Novel Cost-Effective Combine Generation And Cross-Talk Mitigation In Optical OFDM Signal Using Optical IFFT CircuitsPSVLS 65 Transistor Count Optimization Of Conventional CMOS Full Adder & Optimization Of Power And Delay Of New Implementation Of 18 Transistor 1-V, High Speed, Low Leakage CMOSPSVLS 66 CML Multiplexer Full Adder By Dual Threshold Node Design With Submicron Channel A High Performance Reconfigurable Motion Estimation Hardware ArchitecturePSVLS 67 Image Coprocessor: A Real-Time Approach Towards Object Tracking IEEE 2011 ( Image Processing, System Generator, Signal Processing)PSVLS 68 Significance Of Tree Structures For Zero Tree-Based Wavelet Video CODECSPSVLS 69 HW/SW Co-Simulation Platforms For VLSI DesignPSVLS 70 A New Digital Watermarking Scheme Based On TextPSVLS 71 VLSI Architectures Of Perceptual Based Video Watermarking For Real-Time Copyright ProtectionPSVLS 72 Real-Time Invariant Textural Object Recognition With FPGAsPSVLS 73 Throughput Efficient Parallel Implementation Of SPIHT AlgorithmPSVLS 74 FPGA Based Remote Integrated Security System Based WAPPSVLS 75 High-Speed FPGA Implementation For DWT Of Lifting SchemePSVLS 76 Dynamic Power Analysis For Custom DesignsPSVLS 77 Design And Implementation Of Mobile Based Electrical Appliances Control For Industrial AutomationPSVLS 78 On Line Wavelets Transform On A Xilinx FPGA Circuit To Medical Images CompressionPSVLS 79 Design Of Video Compression System Based On DSP-FPGAPSVLS 80 A Measurement System For The Performance Assessment Of Car-Integrated GSM Mobile Communications SystemsPSVLS 81 A Design Of Bi-Verification Vehicle Access Intelligent Control System Based On RFIDPSVLS 82 Full Coverage Manufacturing Testing For SRAM-Based FPGAPSVLS 83 High Speed VLSI Implementation Of A Finite Field Multiplier Using Redundant RepresentationPSVLS 84 Implementation Of A Hardware Functional Verification System Using System C Infrastructurewww.pantechsolutions.net | ©2011Pantech Solutions Pvt Ltd | www.pantechprojects.com 23
  • 4. VLSI email:vlsi@pantechmail.comPSVLS 85 Design And Development Of Activation And Monitoring Of Home Automation System Via Design, Image Processing) SMS Through Microcontroller IEEE 2011 (Low PowerPSVLS 86 Design Of Reconfigurable LED Illumination Control System Based On FPGAPSVLS 87 Improved Method To Increase AES System SpeedPSVLS 88 Design And Implementation Of Mobile Based Electrical Appliances Control For Industrial AutomationPSVLS 89 Hand Gesture Recognition System Based On Associative Processors Real TimePSVLS 90 Experiences Using The Xilinx Micro Blaze Soft Core Processor And µCLinux In Computer Engineering Capstone Senior Design Projects.PSVLS 91 Mean-Square Performance Of Selective Partial Update Sub-Band Adaptive Filters IEEE 2009 (Communication, Power Analysis)PSVLS 92 A Framework Of Transaction-Based HW/SW Co-Simulation For IC VerificationPSVLS 93 Research On Image Median Filtering Algorithm And Its FPGA ImplementationPSVLS 94 On Line Wavelets Transform On A Xilinx FPGA Circuit To Medical Images CompressionPSVLS 95 Medical Image Fusion Based On An Improved Wavelet Coefficient ContrastPSVLS 96 Embedded A Low Area 32-Bit AES For Image Encryption/Decryption ApplicationPSVLS 97 Broadband Receiver Design On FPGAPSVLS 98 Low Power And Area Efficient Image Segmentation VLSI Architecture Using 2-Dimensional Pixel-Block ScanningPSVLS 99 Quadrature Phase Shift Keying Modulator &Demodulator For Wireless ModemPSVLS 100 Low-Power Clocked-Pseudo-NMOS Flip-Flop For Level Conversion In Dual Supply SystemsPSVLS 101 A Low-Power Delay Buffer Using Gated Driver TreePSVLS 102 A Dynamically Reconfigurable Arithmetic Circuit For Complex Number And Double Precision NumberPSVLS 103 An Efficient Hardware Architecture For Multimedia Encryption And Authentication Using The Discrete Wavelet TransformPSVLS 104 Transaction Level Modeling For Early Verification On Embedded System DesignPSVLS 105 A Low Overhead Fault Detection And Recovery Method For The Faults In Clock GeneratorsPSVLS 106 A Framework Of Transaction-Based HW/SW Co-Simulation For IC VerificationPSVLS 107 A HW/SW Co-Verification Technique For Field Programmable Gate Array (FPGA) Test IEEE 2009PSVLS 108 High Throughput One Dimensional Median And Weighted Median Filters On FPGAPSVLS 109 Designing Of VGA Character String Display Module Based On FPGAPSVLS 110 Implementation Of Tsunami Alert System Using FPGAPSVLS 111 Finger Print Based Authentication and Controlling System of Devices using FPGAPSVLS 112 An efficient FPGA implementation of secure cryptographic technique using Wireless Body Area Network.PSVLS 113 Pulse Propagation Along Single-Wire Electric Fences(2008T)www.pantechsolutions.net | ©2011Pantech Solutions Pvt Ltd | www.pantechprojects.com 24
  • 5. VLSI email:vlsi@pantechmail.comPSVLS 114 Multi-sensory system for obstacle detection on railwaysPSVLS 115 Pulse Propagation Along Single-Wire Electric FencesPSVLS 116 FPGA based System for Enhancing Medication Safety and Healthcare for Inpatients Using IEEE 2009 RFIDPSVLS 117 An Optimized RFID-Based Academic LibraryPSVLS 118 Real-time Binary Shape Matching System Based on FPGAPSVLS 119 An RFID Based Solution for Real-Time Patient Surveillance and data Processing Bio-Metric System using FPGAwww.pantechsolutions.net | ©2011Pantech Solutions Pvt Ltd | www.pantechprojects.com 25