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Resource to Performance Tradeoff
Adjustment for Fine-Grained Architectures
─A Design Methodology
When implementing computation-intensive algorithms on finegrained
parallel architectures, adjustment of resource to
performance tradeoff is a big challenge. This paper proposes a
methodology for dealing with some of these performance tradeoffs
by adjusting parallelism at different levels. In a case study,
interpolation kernels are implemented on a fine-grained
architecture (FPGA) using a high level language (Mitrion-C).
For both cubic and bi-cubic interpolation, one single-kernel, one
cross-kernel and two multi-kernel parallel implementations are
designed and evaluated. Our results demonstrate that no single
level of parallelism can be used for trade-off adjustment. Instead,
the appropriate degree of parallelism on each level, according to
available resources and the performance requirements of the
application, needs to be found. Basing the design on high-level
programming simplifies the trade-off process. This research is a
step towards automation of the choice of parallelization based on
a combination of parallelism levels.
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