Cypress SONOS Technology
By Krishnaswamy Ramkumar
Executive Summary Introduction
This white paper discusses the key The demand for embedded Flash memory in system-on-chip (SOC) designs
features of Cypress SONOS has grown steeply in recent years as newer applications evolve in
technology, its performance, and communications and consumer electronics. The memory content of complex
reliability. It also presents a SOC has increased due to increased demand on system performance. Flash
comparison between the SONOS memory is highly desirable in most applications to store critical data and code.
technology and other Flash However, SOC designers require a Flash memory that is easily integrated with
technologies. the rest of the circuitry at a low cost. This requirement is challenging and was a
barrier for the growth of SOCs with Flash memory.
SONOS (Silicon-Oxide-Nitride-Oxide-Silicon) technology has been known as a
Flash technology since the 1980s. However, in the past it was not very
successful in competing against the floating gate technology for standalone
nonvolatile memories. In recent years, with the increasing demand for
embedded nonvolatile memory, SONOS, being more compatible with the logic
technology, is becoming very attractive.
This document provides an overview of the Cypress SONOS technology, its
features, and its integration into a logic process flow.
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Cypress SONOS Technology
Nonvolatile memories (NVM) retain stored information even if the power supply to the memory is switched off. There are
different types of nonvolatile memories including Flash, Read Only Memories (ROM), One Time Programmable (OTP), and
Multiple Time Programmable (MTP) memories. Flash memory is the most versatile because it can be programmed and erased
thousands of times with no degradation in the sense margin and data retention performance.
Floating Gate Flash Memory Technology
Flash memory technology has evolved over the last 30 years to meet the demand for higher density and improved
performance. Starting from UV erased PROMs, they have now evolved into page erased EEPROMs. Figure 1 shows the cross
section structures of key Flash memory cells developed in the last 30 years. The charge storage layer is the same in all the
generations. A floating gate in a MOS FET is used to store the charge. The floating gate is packed in between the channel and
the control gate. It is separated from the channel by a thin tunnel oxide and from the control gate by an ONO dielectric. The
method of injecting (programming of memory) and removing (erasing of memory) charge from the floating gate can be different
and has led to different families of Flash memory.
The charge is injected from the channel to the floating poly through the “tunnel oxide.” The injection is either by direct Fowler–
Nordheim (FN) tunneling or Channel Hot Electron Injection (CHEI). The erasing is typically done by FN tunneling of the
required type of charge from the channel to the floating gate. The FLOTOX cell uses a thin tunnel oxide at one end of the
channel to enable FN tunneling of carriers. The more typical Flash cell has a device with thicker tunnel oxide but uses CHEI
for programming. The split gate cell uses the same mechanism to program or erase but has a different structure.
Figure 1. Cross Section Structures of Flash Memory Cells
Gate Gate Gate
ONO ONO ONO
S D S D D
P substrate P substrate
FLOTOX Typical Flash Split Gate
There are two types of Flash memory depending on the memory cell: NAND and NOR. The comparison of the two types is
given in the following table. Floating gate Flash memory of both types is available from many manufacturers.
Table 1. Comparison between NAND and NOR Memory Cells
Read Access Serial Random
P/E Methods CHEI/FN CHEI/FN
Cell Size (F ) 5–6 10–12
Application Data Storage Code Storage
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Cypress SONOS Technology
SONOS or Charge Trap Memory Technology
Interest in SONOS has increased in recent years because the scalability of floating gate NVM technology is reaching its limits
beyond the 45 nm node. One of the challenges stems from the need to isolate the floating gate from surrounding layers. When
device dimensions shrink, the insulating layers surrounding the gate must also shrink. This leads to increased capacitive
coupling between memory bits and greater likelihood of small quot;pinholequot; manufacturing defects in the insulating layers, creating
a discharge path. The second challenge that arises from shrinking dimensions is the increasing mismatch between the voltage
needed to cause tunneling and the normal circuit operating voltage. As lithography shrinks, circuits must operate at lower
voltages to avoid damage, but the voltage needed to induce tunneling does not drop proportionately. This makes it
increasingly difficult to integrate erase and write circuitry into the rest of the memory device. The voltage mismatch also
increases the likelihood of long term damage to the floating gate transistor with each write/erase cycle, an effect known as
In contrast to the floating gate type, a SONOS memory uses an insulating layer such as silicon nitride with traps as the charge
storage layer. The traps in the nitride capture the carriers injected from the channel and retain the charge. This type of memory
is also known as “Charge Trap Memory.” This storage mechanism is inherently less sensitive to the “pinhole” defects and
more robust for data retention. A very significant research effort is underway the last 5–10 years to further improve the
reliability of SONOS and develop multi-level and multi-bit capability. Much of the research effort is focused on the SONOS
stack, where high K dielectrics and metal gates are evaluated at the 32 nm node. However, most of the SONOS technology in
volume production still uses conventional materials such as silicon dioxide and silicon nitride.
Overview of Cypress SONOS Technology
Cypress’ SONOS technology is an embedded nonvolatile technology that integrates the highly reliable SONOS transistor into
a CMOS process flow with minimum additional mask layers and minimal impact on the electrical parameters of the CMOS
FETs. Cypress uses a unique process for the SONOS transistor to achieve superior reliability. With integration simpler than
that of floating gate Flash, the Cypress SONOS technology can enable a faster ramp to a high yield process flow. This
technology is qualified in Cypress manufacturing plants and in a foundry. The Cypress SONOS cell is highly suitable for
designing and manufacturing EEPROM and embedding Flash memory into logic integrated circuits. The Cypress SONOS
technology uses fewer mask layers than floating gate technology. It is very compatible with CMOS logic technology, which
makes it ideal for embedded Flash. It is also scalable to more advanced technology nodes such as 65 nm and 45 nm.
Cypress SONOS Transistor and Cell
The heart of the Cypress SONOS technology is the SONOS FET shown in Figure 2. This is a MOS transistor with ONO stack
as the gate dielectric. The ONO stack is designed to provide the required program or erase speeds and excellent reliability.
The stack is engineered to yield a memory cell with outstanding endurance and retention characteristics. Further, the stack is
suitable for high volume manufacturing with high Cpk. The SONOS transistor shares many of the key process steps with the
CMOS transistors. Hence, many regions of the SONOS transistor, such as source, drain, and gate, are identical to those of
the CMOS transistors. This makes the process architecture of the embedded SONOS technology significantly simpler.
Figure 2. SONOS Transistor Schematic
Source Well Drain
The schematic shown in Figure 2 is a SONOS transistor that is fabricated using a typical logic CMOS process flow. The device
has salicided gate, source, and drain regions and the gate stack is made up of salicided polysilicon. The device structure is
slightly different in an SRAM flow with the gate stack having an insulator on top of the polysilicon to enable formation of self-
aligned contacts. The source and drain regions are typically not salicided in an SRAM process.
The Cypress SONOS technology currently offers multiple cell options to fit into different application focuses, without
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Cypress SONOS Technology
SONOS Cell Operation
The SONOS cell is programmed by raising the gate voltage of the SONOS transistor to the required positive value . Electrons
are injected from the substrate into the charge storage layer of the ONO stack by FN tunneling. The device is erased by
applying the required negative voltage to the gate, which causes FN tunneling of holes from the substrate to the charge
storage layer. The required program and erase voltage between the gate and substrate is obtained by applying appropriate
voltages to the gate and the p-well. Typical voltages for a 10V program and erase are shown in Table 2.
Table 2. Voltages for 130 nm SONOS Operation
Program Erase Read
Vg 7V -7V 0
Vpw -3V 3V 0
Vs -3V 3V 0
Vd -3V 3V 1.8V
A typical program and erase characteristic of the Cypress SONOS device at 85°C is shown in Figure 3. High voltages required
for program and erase are generated by on-chip charge pump circuits.
Figure 3. Program and Erase Characteristics of Cypress SONOS FET
The current program speed is 1–3 ms and erase speed is 5–10 ms depending on cell option and macro architecture.
Cypress 130 nm SONOS Performance Specifications
The optimized Cypress SONOS technology guarantees the following specifications, which are all proved on silicon:
Program Time: 1–5 msec; Erase Time: 3–10 msec
Program Vt (BOL): ~1V; Erase Vt (BOL): ~–1V
Minimum Selected Erased Cell Read Current: 8 µA/cell
Maximum Selected Programmed Cell Read Current: 100 nA/cell
Maximum Unselected Cell Leakage at 100°C: 4 nA/cell
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Cypress SONOS Technology
SONOS Cell Reliability
A key requirement for an NVM cell is reliability. The End-of-Life (EOL) Vt window is determined by the degradation caused by
program/erase cycles (Endurance) and Vt decay during storage (Data retention). Endurance is typically characterized by
cycling a SONOS cell through the required number of program/erase cycles and measuring the shift of program and erase Vts.
Retention is characterized by taking the SONOS cell through a fixed number of program/erase cycles and then measuring the
change of Vt (program or erase) with time at an elevated temperature. Cypress SONOS technology guarantees retention of 20
years after 100K cycles. Figure 4 and Figure 5 illustrate the typical endurance and retention characteristics.
Figure 4. Endurance Characteristics of Cypress SONOS FET
The endurance characteristics show that Vt shifts less than 100 mV after 100K program/erase cycles at 85°C
Figure 5. Retention Characteristics of Cypress SONOS FET
The retention characteristics show that the Cypress SONOS device has an EOL window greater than 1.5V after 10 years at
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Cypress SONOS Technology
The memory macro is also characterized for reliability. Both at the device level and the macro level, the Cypress SONOS cell
shows the EOL window greater than 1V. The reliability specifications fro Cypress SONOS technology, are given in Table 3.
Table 3. Reliability Specifications for SONOS Technology
Specification Type of NVM Endurance (Cycles) Data Temperature
Commercial Flash 100K 15 -40 to +85
EEPROM 1M 15 -40 to +85
Automotive Flash 10K 10 -40 to +125
The SONOS module can easily be embedded into a logic process flow or an SRAM process flow with the addition of three to
five masking layers. The integration scheme includes a dual gate oxide process, which enables the chip to be compatible with
multiple supply voltages. The SONOS can also be integrated into a state-of-the-art logic process flow, which includes salicided
junctions, stress layers, and Cu-low K interconnects. The integration can be done at many of the technology nodes such as
130 nm, 90 nm, or 65 nm with very few changes except for cell shrink with more aggressive design rules. The optimized
thermal budget of SONOS integration ensures a negligible impact on the electrical parameters of existing CMOS devices. This
is proven even on very sensitive devices in the 65 nm technology. This means that with minimal changes, all the design IP of
the original CMOS platform can be used in the embedded ICs. The integration of SONOS into a logic process flow uses
significantly fewer masks than FG Flash, as shown in Table 4.
Table 4. Comparison of Additional Masks for FG Flash and SONOS Embedded into Logic Flow
Process Step Embedded Floating CY Embedded
Gate NVM SONOS
Wells +3 Masks +1 Mask
Floating Gate Patterning +1 Mask
Other NVM Related Patterning +2 Masks +1 Mask
High Voltage Oxidation/Patterning +1 Mask +1 Mask
NVM /Source/Drain Implants +2 Masks + 1 Mask
High Voltage Source/Drain Implant +2 Masks
Masking Step Adder +11 +4
Compared to the split gate Flash technology, it is simpler and easier to integrate the Cypress SONOS into a logic CMOS
process flow with fewer additional steps (see Table 5). Further, the yield on a SOC with SONOS is limited almost entirely by
the CMOS portion of the die.
Table 5. Comparison of FG Flash, Split Gate Flash, and SONOS
Issue Stack FG Split Gate CY SONOS
Poly Layers Double Triple Single
Floating Gate Patterning Yes Yes No
Word Line Poly Patterning Yes Yes Yes
Steps for Floating Gate Formation 4 to 5 10 to 12 0
Yield Impacting Additional Process Steps 2 3 to 5 1
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