Microchip NANOWatt Technology
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Microchip NANOWatt Technology

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Low Power in PICMICRO

Low Power in PICMICRO

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  • Announce class Intro BD and CV

Microchip NANOWatt Technology Presentation Transcript

  • 1. 704 NWF Low Power Features of the nanoWatt Family Devices
  • 2. Introduction
    • Presenters
      • PIC16 nanoWatt
        • PIC16F87/88, PIC16F818/819
      • PIC18 nanoWatt
        • PIC18F1220/1320, PIC18F2220/2320/4220/4320
    • Feel free to ask questions!
  • 3. Agenda
    • This 4 hour class will consist of
      • 2 Hours of lecture
        • Ask questions at any time
        • A short break during the lecture
      • 2 Hours of lab time
        • Take a break any time
        • Feel free to experiment
        • Use either PIC16F88 or PIC18F1320 (Students choice)
  • 4. Topics
    • What is nanoWatt Technology?
    • Clock System
    • 2-Speed Start-up
    • Fail-Safe Clock Monitor (FSCM)
    • Watch Dog Timer (WDT)
    • Power Managed Modes
      • Clock Sources and Clock Status Flags
      • Entry and Exit from Power Managed Modes
      • Discuss each mode
  • 5. What is nanoWatt Technology?
    • Microchip took the existing portfolio of products and made several improvements
      • Redesigned existing modules for lower current operation
      • Added a new Internal Oscillator and Oscillator modes
      • Added new Power Managed features and modes to PIC16 and PIC18 devices
  • 6. nanoWatt Family Devices
    • PIC16 Family
      • PIC16F87 / 88
      • PIC16F628A
      • PIC16F630
      • PIC16F676
      • PIC16F818
    • PIC18 Family
      • PIC18F1220 / 1320
      • PIC18F2220 / 2320
      • PIC18F4220 / 4320
    • This class focuses on PIC16F88 and PIC18F1320 devices
    • PIC12 Family
      • PIC12F629
      • PIC12F675
  • 7. Clock System
    • PIC16 and PIC18 clock systems
      • Clock Sources
        • Primary
        • Secondary
        • Internal Oscillator Block (8 MHz)
        • INTRC (31 kHz)
      • OSCTUNE Register
  • 8. Clock System: PIC16 Prescaler Timer1 Oscillator Primary Oscillator (EC, RC, LP, XT, HS) Timer 1 Enable To CPU and Peripherals To Timer 1 INTRC (31kHz) Post- 1:2 scaler 1:4 1:8 1:16 1:32 1:64 INTOSC (8 MHz) OSCCON CONFIG1 & OSCCON WDTPS WDT / TMR0 Multiplexer 1ms - 2.1sec 32us FS Clock Monitor Bias Prescaler 1:32 to 1:65536
  • 9. Clock System: PIC18 Prescaler Timer1 Oscillator Primary Oscillator (RC, EC, LP, XT, HS, HSPLL) IDLE Mode Timer 1 Enable To CPU Clock To Peripherals To Timer 1 INTRC (31kHz) Post- 1:2 scaler 1:4 1:8 1:16 1:32 1:64 INTOSC (8 MHz) CONFIG1H & OSCCON 32us 1:125 4ms WDT Time-out FS Clock Monitor WDT Postscaler 1:1 to 1:32768 Bias
  • 10. Clock System: Primary Clocks
    • Config Word defines Primary Clock Source
    • 10 Modes - 4 mode bits (3 bits for PIC16)
    • FOSC3:FOSC0 (_CONFIG1H<3:0>)
      • External Clock - EC, ECIO
      • Crystal Oscillator - LP, XT, HS, HSPLL *
      • External RC Oscillator - RC, RCIO
      • Internal Oscillator Block (IOB) - INTIO1, INTIO2
      • *PIC18 family only
  • 11. Clock System: Primary Clocks
    • When the Internal Oscillator Block is selected as primary clock source:
      • OSC1 pin functions as RA7 for input and output
      • OSC2 pin
        • Outputs F OSC /4 or
        • Functions as RA6 for input and output
  • 12. Clock System: Secondary Clock
    • Legacy Timer1 Oscillators
      • Legacy devices do not control oscillator amplitude
      • Amplitude varies when V DD and Temperature change
      • Loading capacitors are critical
      • Oscillator current is 20-30 uA
  • 13. Clock System: Secondary Clock
    • New Low Power Timer1 Oscillator
      • About 3ua vs 30ua in other devices
      • Oscillator amplitude is regulated
      • Constant current across V DD and Temperature
      • Loading capacitors are not as critical
      • Robust operation
  • 14. Clock System: Secondary Clock
    • Secondary Oscillator (Timer1 Oscillator)
      • Enabled by T1OSCEN (T1CON<3>)
      • Commonly 32.768 kHz for a RTC time base
      • User code is responsible for determining when Secondary Clock is ready
  • 15. Clock System: Internal Oscillator Block
    • Internal 8MHz Oscillator (INTOSC)
      • Calibrated to 8 MHz, 1% Typ, 2% Max at 25C ‘F’ parts calibrated at 5V, ‘LF’ at 3V
      • Drives postscaler
      • Multiplexer selects 8, 4, 2, 1 MHz, 500, 250, 125 kHz, or 31 kHz clock sources
    INTRC (31kHz) Post- 1:2 scaler 1:4 1:8 1:16 1:32 1:64 INTOSC (8 MHz) System Clock
  • 16. Clock System: Internal Oscillator Block
    • Internal Oscillator Block (IOB) (INTOSC 8 MHz output)
      • Requires 1ms to 4ms to become stable (check datasheet)
      • Code execution continues while stabilizing
      • IOFS flag (OSCCON<2>) is set when INTOSC 8MHz output becomes stable
        • Time critical code should wait for IOFS flag to be set
  • 17. Clock System: INTRC
    • Internal RC oscillator (INTRC)
      • Nominally 31 kHz (32us) Fixed within 28 - 34 kHz range
        • Relatively insensitive to changes in Temp or V DD compared to external RC Oscillator
      • Instantly ready
      • When INTRC (31 kHz) is selected as system clock source
        • INTOSC output is disabled - saves current
        • Postscaler is disabled - saves current
  • 18. Clock System: INTRC
    • INTRC enabled for
      • Watch Dog Timer (check datasheet for periods)
        • PIC16 - T WDT = 1ms (Nom.)
        • PIC18 - T WDT = 4ms (Nom.)
      • Two-Speed Startup (Resets and Wake from SLEEP mode)
      • Fail-Safe Clock Monitor
  • 19. Clock System: OSCTUNE
    • OSCTUNE register
      • User adjustable FREQUENCY
        • 6-bits, range is up to ±12.5%, 0.4% / step
        • Affects
          • 8MHz INTOSC output frequency
          • 31kHz INTRC output frequency
          • WDT period
          • Fail-Safe Clock Monitor period
          • 2-Speed Start-up frequency
  • 20. Clock System: INTOSC Freq and Status
    • When clocking from the INTOSC block, code can select a higher clock frequency when required for
      • Greater workload - CPU must do more work
      • Peripherals need higher speed clock
    • Code can select lower frequency
      • Light workload
      • Peripherals can use lower resolution clock
      • Reduce current consumption
  • 21. Clock System: INTOSC Freq and Status
    • Select desired INTOSC Frequency
      • IOFS gets set when INTOSC becomes stable
  • 22. Clock System: OSCCON Register IDLEN Controls CPU clocking (PIC18 Only) IRCF<2:0> Selects tap from INTOSC Postscaler OSTS =1 if Primary clock is currently providing the system clock IOFS =1 if INTOSC (8 MHz) output is stable SCS<1:0> Selects the power managed mode clock source
  • 23. Clock System: Clock Switching
    • Modifying IRCF<2:0> bits immediately selects a different INTOSC postscaler tap
    • If V DD <2.9V, care must be taken to avoid selecting the 8MHz output by mistake
      • CPU may not operate properly outside specified Frequency / V DD limits
    • Recommended Procedure
      • Read OSCCON to shadow register
      • Modify shadow
      • Write shadow back to OSCCON
  • 24. Clock System: INTOSC Frequency Switch
    • ; This code safely modifies OSCCON
    • movf OSCCON,W ; copy OSCCON to WREG
    • andlw B’10001111’ ; clear IRCF bits
    • iorlw B’01010000’ ; new IRCF bits (2MHz)
    • movwf OSCCON ; copy result to OSCCON
    • ; This eliminates the possibility of selecting ; 8MHz even for one instruction cycle.
    • ; Operations on OSCCON,IRCF bits have ; immediate effects!
  • 25. Topics
    • What is nanoWatt Technology?
    • Clock System
    • 2-Speed Start-up
    • Fail-Safe Clock Monitor (FSCM)
    • Watch Dog Timer (WDT)
    • Power Managed Modes
      • Clock Sources and Clock Status Flags
      • Entry and Exit from Power Managed Modes
      • Discuss each mode
  • 26. Two Speed Start-up: Overview
    • Allows code execution to start before the Primary clock source becomes ready
    • Internal Oscillator Block (IOB) provides clocks before Primary clock source becomes ready
    • Automatically switches to Primary when it becomes ready
    • Used for
      • Start from Reset
      • Wake from SLEEP Mode
  • 27. Two Speed Start-up: Operation
    • Primary clocks might not be available due to startup delays
      • Crystal / Resonator oscillator start time
      • OST delay (counts 1024 oscillator cycles)
      • PLL delay (additional 2ms delay for HS/PLL)
    • The IOB can provide system clocks during this time
      • Code can select operating frequency
      • Code may finish work quickly and go back to SLEEP before Primary is ready
  • 28. Two Speed Start-up: Operation
    • When primary becomes ready
      • Clock source switched to Primary clock
      • OSTS (OSCCON<3>) is set
      • IOB may shut down
        • INTRC may be required for other features
          • Watch Dog Timer (WDT)
          • Fail-Safe Clock Monitor (FSCM)
  • 29. Two Speed Start-up: Operation
    • Enable by setting the IESO bit (_CONFIG2<1>) (PIC16) (_CONFIG1H<7>) (PIC18) (Internal External Switch Over)
    • Used with crystal based modes only
      • OST delay used with crystal modes (LP, XT, HS, and HS/PLL modes)
      • HS/PLL (PIC18) adds 2ms
      • Other oscillator modes do not require 2-speed startups
  • 30. Two Speed Start-up: Assumptions
    • Compare INTRC speed to typical crystal startup times and delays
      • LP mode oscillators start in 100’s of mS
      • XT mode oscillators start in 1’s of mS
      • HS mode oscillators start in 10’s of uS
      • HS/PLL mode starts in 2ms (PLL start delay)
    • CPU requires 5 - 10 uS following wake event to become ready to execute code
      • Assume 7us
  • 31. Two Speed Start-up: Assumptions
    • Wake from SLEEP mode
    • OSCCON register loaded before entering SLEEP mode
      • 31 kHz for LP mode (same as crystal)
      • 4 MHz for XT mode (same as crystal)
      • 8 MHz for HS and HS/PLL modes
  • 32. Two Speed Start-up: What to expect
    • 32.7 kHz LP mode (30.5us, 1T CY =122 us)
    • Without Two-Speed Start
      • Crystal oscillator starts in about 750 ms
      • OST adds 31.3 ms (1024 * 30.5 us = 31.3 ms)
      • 781 ms before instructions begin executing
    • With Two-Speed Start (INTRC @ 31 kHz, 1 T CY = 128 us)
      • CPU requires 7us to start from wake
      • In 774 ms, 6.0k instructions could be executed before clock switch occurs
  • 33. Two Speed Start-up: What to expect
    • 4 MHz XT mode (250ns, 1T CY =1us)
    • Without Two-Speed Start
      • Crystal oscillator starts in about 1 ms
      • OST adds 256 us (1024 * .25 us = 256 us)
      • 1.26 ms before instructions begin executing
    • With Two-Speed Start (INTOSC @ 4MHz, T CY = 1us)
      • In 1.25 ms, 1.25K instructions could be executed before clock switch occurs
  • 34. Two Speed Start-up: What to expect
    • 20MHz HS mode (T OSC =50ns, 1T CY =200ns)
    • Without Two-Speed Start
      • Crystal oscillator starts in about 10 us
      • OST adds 51.2 us (1024 * .05 us = 51.2 us)
      • 61.2 uS before instructions begin executing
    • With Two-Speed Start (INTOSC @ 8MHz, 1 T CY = 500 ns)
      • CPU requires 7us to start from wake
      • In 54.4 uS, 109 instructions could be executed before clock switch occurs
  • 35. Two Speed Start-up: What to expect
    • 40MHz HS/PLL mode (25ns , 1T CY =100ns)
    • Without Two-Speed Start
      • Crystal oscillator (10MHz) starts in about 10 us
      • OST adds 102 us (1024 * 0.1 us = 102 us)
      • PLL adds 2ms (dominates startup delays)
      • 2.1 ms before instructions begin executing
    • With Two-Speed Start (INTOSC @ 8MHz, 1 T CY = 500 ns)
      • CPU requires 7us to start from wake
      • In 2.1 ms, 4.2k instructions could be executed before clock switch
  • 36. Topics
    • What is nanoWatt Technology?
    • Clock System
    • 2-Speed Start-up
    • Fail-Safe Clock Monitor (FSCM)
    • Watch Dog Timer (WDT)
    • Power Managed Modes
      • Clock Sources and Clock Status Flags
      • Entry and Exit from Power Managed Modes
      • Discuss each mode
  • 37. Fail-Safe Clock Monitor (FSCM)
    • How Does It Work?
    • How To Enable It
      • When is it used
    • Operation During
      • Clock Source Failure
      • System Start-Up
      • Wake from SLEEP mode
  • 38. FSCM: How Does It Work? Sample Clock (INTRC/64 - Clear) Peripheral Clock (Clock/4 - Set) CM F/F Q Output OSCFIF Oscillator Failure Failure Detected Set OSCFIF INTRC (32 us)  64 Set Q Clear !Q Peripheral clock Clock Monitor F/F ~2ms period CM F/F Tested CM F/F Tested CM F/F Tested
  • 39. FSCM: How To Enable
    • Enable by setting the FSCMEN bit (_CONFIG2<0>) (PIC16) (_CONFIG1H<6>) (PIC18) (Fail-Safe Clock Monitor ENable)
    • Used to detect a loss of externally based clocked sources
      • Only IOB is fully internal
  • 40. FSCM: During Failure
    • On Primary or Secondary clock failure
      • Clears WDT (may not be enabled)
      • Clock source switched to IOB
        • OSTS is cleared if Primary failed
        • T1RUN (T1CON<6>) cleared if Secondary failed
        • OSCCON is NOT updated
      • OSCFIF (PIR2<7>) is set
        • If interrupts enabled, causes wake without clock switch to Primary clock source
  • 41.
    • When clocked by internal RC clock source
      • If IRCF bits are = 000
        • Clocked from INTRC at 31kHz
      • If IRCF bits are  000
        • Clocked from INTOSC at higher speed
        • The IRCF bits may be set prior to the clock failure, i.e. during device startup
    FSCM: During Failure
  • 42. FSCM: Normal Startup (Reset or Wake from SLEEP)
    • During start-up (reset or wake from sleep)
      • Internal Oscillator Block provides system clocks until Primary clock is ready (similar to 2-speed start)
      • When the primary is ready, an automatic clock switch selects the primary clock
      • FSCM then becomes active, and OSTS is set
      • INTOSC (8MHz) is disabled
        • INTRC (31 kHz) runs for FSCM (and WDT)
      • This prevents false fails at startup
  • 43. FSCM: Startup with Failed Primary
    • During start-up (reset or wake from sleep)
      • If the Primary clock never becomes ready, no clock failure will be detected
        • Firmware will need to detect this condition
          • Check OSTS flag after suitable delay
        • FSCM becomes active if SEC_(mode) is selected before Primary becomes ready
  • 44. Topics
    • What is nanoWatt Technology?
    • Clock System
    • 2-Speed Start-up
    • Fail-Safe Clock Monitor (FSCM)
    • Watch Dog Timer (WDT)
    • Power Managed Modes
      • Clock Sources and Clock Status Flags
      • Entry and Exit from Power Managed Modes
      • Discuss each mode
  • 45. Watch Dog Timers
    • General WDT
      • PIC16 WDT
      • PIC18 WDT
  • 46. Watch Dog Timers
    • Clocked by INTRC (32us period)
    • Has same characteristics as INTRC across temperature and V DD
      • Greatly improved stability compared with previous WDTs
    • WDT may be enabled by firmware if configured disabled by configuration word
      • SWDTEN (WDTCON<0>)
  • 47. Watch Dog Timer: PIC16
    • PSA = 0
      • OPTION postscaler assigned to TMR0
      • WDT uses only WDTCON postscaler
    • PSA = 1
      • OPTION postscaler assigned to WDT
      • WDT uses both postscalers
    1ms - 2.097s INTRC (31kHz) 16-bit Postscaler WDT Time-out TMR0 Sync TMR0 Register RA4 / T0CKI Fosc/4 TMR0IF PSA T0CS 0 1 1 1 1 8-bit Postscaler 0 0 0 OPTION PS<2:0> WDTCON WDTPS<3:0> 32us INTOSC (8MHz) PSA PSA (resets to 1:512) (16.4ms)
  • 48. Watch Dog Timer: PIC16
    • WDTCON controls WDTCON postscaler
      • Ratios 1:32 to 1:64K (1ms to 2.1s)
      • Resets to 1:512 (16.4ms)
    • OPTION_REG controls OPTION postscaler
      • Ratios 1:1 to 1:128
      • Timer0 and WDT share postscaler
    • Postscalers may be used in series
      • Ratios 1:1 to 1:8.4M
      • Time-out range: 1ms to 268 sec / 4.5 min
  • 49. Clock System: PIC18 Prescaler Timer1 Oscillator Primary Oscillator (RC, EC, LP, XT, HS, HSPLL) IDLE Mode Timer 1 Enable To CPU Clock To Peripherals To Timer 1 INTRC (31kHz) Post- 1:2 scaler 1:4 1:8 1:16 1:32 1:64 INTOSC (8 MHz) CONFIG1H & OSCCON 32us 1:125 4ms WDT Time-out FS Clock Monitor WDT Postscaler 1:1 to 1:32768 Bias
  • 50. Watch Dog Timer: PIC18
    • WDT postscaler offers more ratios
      • WDT period is 4.0 ms (125 * 32us)
      • 1:1 to 1:32,768 (4 ms to 131 sec / 2.2 min)
      • Ratio selected by CONFIG2H (fixed)
  • 51. Topics
    • What is nanoWatt Technology?
    • Clock System
    • 2-Speed Start-up
    • Fail-Safe Clock Monitor (FSCM)
    • Watch Dog Timer (WDT)
    • Power Managed Modes
      • Clock Sources and Clock Status Flags
      • Entry and Exit from Power Managed Modes
      • Discuss each mode
  • 52. Power Managed Modes
    • How to reduce current consumption?
      • Disable a clock source that is not needed
      • Disable clocks to peripherals and/or CPU
      • Select a lower clock frequency
        • Clock peripherals at lower speed
        • Execute code at lower speed
      • Reduce or eliminate startup delays
      • Use low power peripherals
  • 53. Power Managed Modes
    • What are Power Managed Modes?
    • Clock Sources
    • Clock switch example
    • Clock source status Flags
    • CPU Operation (PIC18 only)
    • Entry to Power Managed Modes
    • Exit from Power Managed Modes
  • 54. Power Managed Modes: What are they?
    • Power Managed Modes allow the user to:
      • Select System clock source
      • Select System clock frequency
      • Disable clocks to the CPU (PIC18 only)
    • These options provide code with the means to control power consumption as needed
  • 55. Power Managed Modes: Clock Sources
    • Select desired clock source
      • Most Primary clock sources are fixed frequency (i.e. not controllable by code)
      • Secondary clock source (Timer1 Oscillator) is fixed frequency
        • Required for Real-Time Clock time base
      • Internal Oscillator Block allows selection of clock frequency
        • Code can select system frequency according to need
  • 56. Power Managed Modes: Clock Sources
    • Select desired clock source
      • Set the SCS<1:0> bits (OSCCON(<1:0>) for the desired clock source
        • PRI = 00 SEC = 01 INTOSC = 1X
      • PIC18 - Execute SLEEP instruction
      • PIC16 - Clock switch is immediate
        • Consider using a shadow register
  • 57. Power Managed Modes: Clock Switching Example
    • Switching from XT (old) to Timer1 (new)
      • Execution pauses at the end of Q4 clock
      • 8 cycles from the new clock are counted
      • Execution resumes clocked by the new clock
    • This example is repeated for every clock switching event
    OSC1 TMR1 SysClk Q1 Q2 Q3 Q4 Q1 Q2 Q3 1 2 7 8 // Q4 Execution Pauses for 8 of the new clocks Original clock is disabled (shut down)
  • 58. Power Managed Modes: Clock Status Flags
    • Each clock source sets a status bit to indicate when it is providing the system clock
      • Primary clock - OSTS bit (OSCCON<3>)
      • Secondary clock - T1RUN bit (T1CON<6>)
      • Internal Oscillator Block - IOFS bit (OSCCON<2>)
    • Only one clock status bit will be set at any time
  • 59. Power Managed Modes: Clock Status Flags
    • If no bits are set,
      • INTOSC is providing clocks but not yet stable
        • OR
      • INTRC is providing clocks at 31kHz
      • To determine IOB clock source, check
        • IOFS bit after suitable delay or
        • IRCF bits
  • 60. Power Managed Modes: Clock Status Flags
    • IOFS always =0 if IRCF<2:0>=000 (31kHz)
    • IOFS set after startup delay if IRCF<2:0> =000
  • 61. Power Managed Modes
  • 62. PRI_RUN Mode
    • This is the normal full power execution mode
    • Exits from all other power managed modes return to PRI_RUN mode
    • CPU and peripherals are clocked by Primary clock source
      • T1RUN, IOFS cleared OSTS set
  • 63.
    • This is the sleep mode in other Microchip controllers
    • IDLEN = 0 (PIC18 only), SCS<1:0> = 00
    • Execute SLEEP instruction
      • CPU not clocked
      • Peripherals depending on system clocks are not clocked
      • Primary oscillator is disabled
    • This is the only power managed mode where no system clock sources are running
    SLEEP Mode
  • 64.
    • This mode replaces the clock switching mechanism in other PIC18 controllers
    • Adjust peripherals for T1OSC frequency
    • IDLEN = 0 (PIC18 only) , SCS<1:0> = 01
    • Execute a SLEEP instruction (PIC18 only)
      • CPU and Peripherals clocked using T1OSC
      • Primary oscillator is disabled
      • IOFS, OSTS cleared T1RUN set
    SEC_RUN Mode
  • 65.
    • Adjust peripherals for new clock frequency
    • IRCF<2:0> selects clock speed (optional)
    • IDLEN = 0 (PIC18 only) , SCS<1:0> = 1X
    • Execute a SLEEP instruction (PIC18 only)
      • Primary oscillator is disabled
      • CPU and Peripherals clocked using IOB
      • OSTS, T1RUN cleared
      • IOFS set after 1-4 ms delay if Freq  31 kHz
        • Check datasheet for INTOSC delay
    RC_RUN Mode
  • 66. Power Managed Modes: CPU Operation (PIC18 only)
    • Code can disable clocks to the CPU
      • Stops code execution without affecting peripheral operation
      • CPU is in a sleep-like state
      • WDT, Interrupts and resets restart CPU
    • Disable CPU clocks by setting the IDLEN bit (OSCCON<7>) and executing a SLEEP instruction
  • 67. IDLE Modes (PIC18 only)
    • Configure IDLEN (OSCCON<7>)
      • Choose whether CPU is clocked or not
      • Peripherals are always clocked
      • Sleep mode is exception - No clocks operate
  • 68. PRI_IDLE Mode (PIC18 only)
    • IDLEN = 1, SCS<1:0> = 00
    • Execute a SLEEP instruction
      • CPU not clocked
      • Peripherals that need system clocks are clocked by Primary oscillator
      • Primary oscillator is continues to run
  • 69. SEC_IDLE Mode (PIC18 only)
    • Adjust peripherals for new clock frequency
    • IDLEN = 1, SCS<1:0> = 01
    • Execute a SLEEP instruction
      • CPU not clocked
      • Peripherals that need system clocks are clocked by T1OSC oscillator
      • Primary oscillator is disabled
      • OSTS, IOFS cleared T1RUN set
  • 70. RC_IDLE Mode (PIC18 only)
    • IDLEN = 1, SCS<1:0> = 1X
    • Adjust peripherals for new clock frequency
    • Execute a SLEEP instruction
      • CPU not clocked
      • Peripherals that need system clocks are clocked by Internal Oscillator Block
      • Primary oscillator is disabled
      • OSTS, T1RUN cleared IOFS may be set after delay
  • 71. (any)_RUN to (same)_IDLE (PIC18 only)
    • ; Switch from (any)_RUN to (same)_IDLE
    • ; Uses same clock source / frequency
    • bsf OSCCON,IDLEN ; select IDLE mode
    • sleep ; enters (*)_IDLE mode
    • ; Execution pauses here, waits for
    • ; wake by interrupt, reset,
    • ; or WDT timeout.
    • ; CPU not clocked, peripherals run from
    • ; same clock source (not changed).
  • 72. Exit from Power Managed Mode
    • What wakes a device from SLEEP? (Any controller, not just nanoWatt)
      • Any Interrupt
      • Any Reset
      • WDT time-out
  • 73. Exit from Power Managed Mode
    • On Exit by Interrupt
      • Program flow is controlled GIE/GIEH
        • If set, branch to ISR
        • If clear, resume at next instruction
      • Primary clock is started (if not already running)
        • Automatic clock switch occurs if / when Primary becomes ready
  • 74. Exit from Power Managed Mode
    • On Exit by Interrupt
      • CPU and peripherals are clocked using selected clock until Primary becomes ready
      • Exit from SLEEP mode:
        • No clock is selected, execution resumes when Primary becomes ready
        • Execution can begin immediately if either Two-Speed Startup or Fail-Safe Clock Monitor is enabled
  • 75. Exit from Power Managed Mode
    • On Exit by Reset
      • Primary clock is started
      • Execution pauses until Primary becomes ready
        • Execution can begin immediately if either Two-Speed Startup or Fail-Safe Clock Monitor is enabled
        • OSTS bit in OSCCON register is set when Primary is providing system clocks
  • 76. Exit from Power Managed Mode
    • On Exit by WDT Time-out
        • Reset if in any RUN mode (CPU clocked, executing code)
        • Wake if in SLEEP or any IDLE mode (CPU not clocked, not executing code)
      • TO bit is cleared PIC16 - STATUS<4> PIC18 - RCON<3>
      • Exit process depends on if CPU was executing code
  • 77. Lab Exercises
    • Please choose a device to use
    • for the labs that follow:
    • PIC16F88
    • or
    • PIC18F1320
  • 78. Lab #1 - Fail-Safe Clock Monitor
      • Configure code for 8 MHz Canned Oscillator.
      • Write code to handle Fail-Safe interrupt.
      • When the Fail-Safe interrupt occurs, the code should operate as before the Fail-Safe condition was detected.
      • Hints:
        • ____________________
        • ____________________
        • ____________________
        • ____________________
  • 79. Lab #2 - Clock Switching
      • Configure the clock system to minimize current consumption.
      • Communication to the I/O expander (and LCD) cannot be affected.
      • Measure I DD
      • Hints:
        • ____________________
        • ____________________
        • ____________________
        • ____________________
  • 80. Lab #3 - Analog I/O Pin
      • Write code in the Voltmeter block that minimizes current consumption.
      • Measure I DD
      • Hints:
        • ____________________
        • ____________________
        • ____________________
        • ____________________
  • 81. Lab #4 - Communication
      • Review the PICDEM™ 4 Schematic
      • Write code in the AUSART block that minimizes current consumption.
      • Measure I DD
      • Hints:
        • ____________________
        • ____________________
        • ____________________
        • ____________________
  • 82. Lab #5 - Real Time Clock
      • Write code within the Timer 1 block that minimizes current consumption.
      • Measure I DD
      • Hints:
        • ____________________
        • ____________________
        • ____________________
        • ____________________
  • 83. 704 NWF Low Power Features of the nanoWatt Family Devices