Microchip NANOWatt Technology

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  • Announce class Intro BD and CV
  • Microchip NANOWatt Technology

    1. 1. 704 NWF Low Power Features of the nanoWatt Family Devices
    2. 2. Introduction <ul><li>Presenters </li></ul><ul><ul><li>PIC16 nanoWatt </li></ul></ul><ul><ul><ul><li>PIC16F87/88, PIC16F818/819 </li></ul></ul></ul><ul><ul><li>PIC18 nanoWatt </li></ul></ul><ul><ul><ul><li>PIC18F1220/1320, PIC18F2220/2320/4220/4320 </li></ul></ul></ul><ul><li>Feel free to ask questions! </li></ul>
    3. 3. Agenda <ul><li>This 4 hour class will consist of </li></ul><ul><ul><li>2 Hours of lecture </li></ul></ul><ul><ul><ul><li>Ask questions at any time </li></ul></ul></ul><ul><ul><ul><li>A short break during the lecture </li></ul></ul></ul><ul><ul><li>2 Hours of lab time </li></ul></ul><ul><ul><ul><li>Take a break any time </li></ul></ul></ul><ul><ul><ul><li>Feel free to experiment </li></ul></ul></ul><ul><ul><ul><li>Use either PIC16F88 or PIC18F1320 (Students choice) </li></ul></ul></ul>
    4. 4. Topics <ul><li>What is nanoWatt Technology? </li></ul><ul><li>Clock System </li></ul><ul><li>2-Speed Start-up </li></ul><ul><li>Fail-Safe Clock Monitor (FSCM) </li></ul><ul><li>Watch Dog Timer (WDT) </li></ul><ul><li>Power Managed Modes </li></ul><ul><ul><li>Clock Sources and Clock Status Flags </li></ul></ul><ul><ul><li>Entry and Exit from Power Managed Modes </li></ul></ul><ul><ul><li>Discuss each mode </li></ul></ul>
    5. 5. What is nanoWatt Technology? <ul><li>Microchip took the existing portfolio of products and made several improvements </li></ul><ul><ul><li>Redesigned existing modules for lower current operation </li></ul></ul><ul><ul><li>Added a new Internal Oscillator and Oscillator modes </li></ul></ul><ul><ul><li>Added new Power Managed features and modes to PIC16 and PIC18 devices </li></ul></ul>
    6. 6. nanoWatt Family Devices <ul><li>PIC16 Family </li></ul><ul><ul><li>PIC16F87 / 88 </li></ul></ul><ul><ul><li>PIC16F628A </li></ul></ul><ul><ul><li>PIC16F630 </li></ul></ul><ul><ul><li>PIC16F676 </li></ul></ul><ul><ul><li>PIC16F818 </li></ul></ul><ul><li>PIC18 Family </li></ul><ul><ul><li>PIC18F1220 / 1320 </li></ul></ul><ul><ul><li>PIC18F2220 / 2320 </li></ul></ul><ul><ul><li>PIC18F4220 / 4320 </li></ul></ul><ul><li>This class focuses on PIC16F88 and PIC18F1320 devices </li></ul><ul><li>PIC12 Family </li></ul><ul><ul><li>PIC12F629 </li></ul></ul><ul><ul><li>PIC12F675 </li></ul></ul>
    7. 7. Clock System <ul><li>PIC16 and PIC18 clock systems </li></ul><ul><ul><li>Clock Sources </li></ul></ul><ul><ul><ul><li>Primary </li></ul></ul></ul><ul><ul><ul><li>Secondary </li></ul></ul></ul><ul><ul><ul><li>Internal Oscillator Block (8 MHz) </li></ul></ul></ul><ul><ul><ul><li>INTRC (31 kHz) </li></ul></ul></ul><ul><ul><li>OSCTUNE Register </li></ul></ul>
    8. 8. Clock System: PIC16 Prescaler Timer1 Oscillator Primary Oscillator (EC, RC, LP, XT, HS) Timer 1 Enable To CPU and Peripherals To Timer 1 INTRC (31kHz) Post- 1:2 scaler 1:4 1:8 1:16 1:32 1:64 INTOSC (8 MHz) OSCCON CONFIG1 & OSCCON WDTPS WDT / TMR0 Multiplexer 1ms - 2.1sec 32us FS Clock Monitor Bias Prescaler 1:32 to 1:65536
    9. 9. Clock System: PIC18 Prescaler Timer1 Oscillator Primary Oscillator (RC, EC, LP, XT, HS, HSPLL) IDLE Mode Timer 1 Enable To CPU Clock To Peripherals To Timer 1 INTRC (31kHz) Post- 1:2 scaler 1:4 1:8 1:16 1:32 1:64 INTOSC (8 MHz) CONFIG1H & OSCCON 32us 1:125 4ms WDT Time-out FS Clock Monitor WDT Postscaler 1:1 to 1:32768 Bias
    10. 10. Clock System: Primary Clocks <ul><li>Config Word defines Primary Clock Source </li></ul><ul><li>10 Modes - 4 mode bits (3 bits for PIC16) </li></ul><ul><li>FOSC3:FOSC0 (_CONFIG1H<3:0>) </li></ul><ul><ul><li>External Clock - EC, ECIO </li></ul></ul><ul><ul><li>Crystal Oscillator - LP, XT, HS, HSPLL * </li></ul></ul><ul><ul><li>External RC Oscillator - RC, RCIO </li></ul></ul><ul><ul><li>Internal Oscillator Block (IOB) - INTIO1, INTIO2 </li></ul></ul><ul><ul><li>*PIC18 family only </li></ul></ul>
    11. 11. Clock System: Primary Clocks <ul><li>When the Internal Oscillator Block is selected as primary clock source: </li></ul><ul><ul><li>OSC1 pin functions as RA7 for input and output </li></ul></ul><ul><ul><li>OSC2 pin </li></ul></ul><ul><ul><ul><li>Outputs F OSC /4 or </li></ul></ul></ul><ul><ul><ul><li>Functions as RA6 for input and output </li></ul></ul></ul>
    12. 12. Clock System: Secondary Clock <ul><li>Legacy Timer1 Oscillators </li></ul><ul><ul><li>Legacy devices do not control oscillator amplitude </li></ul></ul><ul><ul><li>Amplitude varies when V DD and Temperature change </li></ul></ul><ul><ul><li>Loading capacitors are critical </li></ul></ul><ul><ul><li>Oscillator current is 20-30 uA </li></ul></ul>
    13. 13. Clock System: Secondary Clock <ul><li>New Low Power Timer1 Oscillator </li></ul><ul><ul><li>About 3ua vs 30ua in other devices </li></ul></ul><ul><ul><li>Oscillator amplitude is regulated </li></ul></ul><ul><ul><li>Constant current across V DD and Temperature </li></ul></ul><ul><ul><li>Loading capacitors are not as critical </li></ul></ul><ul><ul><li>Robust operation </li></ul></ul>
    14. 14. Clock System: Secondary Clock <ul><li>Secondary Oscillator (Timer1 Oscillator) </li></ul><ul><ul><li>Enabled by T1OSCEN (T1CON<3>) </li></ul></ul><ul><ul><li>Commonly 32.768 kHz for a RTC time base </li></ul></ul><ul><ul><li>User code is responsible for determining when Secondary Clock is ready </li></ul></ul>
    15. 15. Clock System: Internal Oscillator Block <ul><li>Internal 8MHz Oscillator (INTOSC) </li></ul><ul><ul><li>Calibrated to 8 MHz, 1% Typ, 2% Max at 25C ‘F’ parts calibrated at 5V, ‘LF’ at 3V </li></ul></ul><ul><ul><li>Drives postscaler </li></ul></ul><ul><ul><li>Multiplexer selects 8, 4, 2, 1 MHz, 500, 250, 125 kHz, or 31 kHz clock sources </li></ul></ul>INTRC (31kHz) Post- 1:2 scaler 1:4 1:8 1:16 1:32 1:64 INTOSC (8 MHz) System Clock
    16. 16. Clock System: Internal Oscillator Block <ul><li>Internal Oscillator Block (IOB) (INTOSC 8 MHz output) </li></ul><ul><ul><li>Requires 1ms to 4ms to become stable (check datasheet) </li></ul></ul><ul><ul><li>Code execution continues while stabilizing </li></ul></ul><ul><ul><li>IOFS flag (OSCCON<2>) is set when INTOSC 8MHz output becomes stable </li></ul></ul><ul><ul><ul><li>Time critical code should wait for IOFS flag to be set </li></ul></ul></ul>
    17. 17. Clock System: INTRC <ul><li>Internal RC oscillator (INTRC) </li></ul><ul><ul><li>Nominally 31 kHz (32us) Fixed within 28 - 34 kHz range </li></ul></ul><ul><ul><ul><li>Relatively insensitive to changes in Temp or V DD compared to external RC Oscillator </li></ul></ul></ul><ul><ul><li>Instantly ready </li></ul></ul><ul><ul><li>When INTRC (31 kHz) is selected as system clock source </li></ul></ul><ul><ul><ul><li>INTOSC output is disabled - saves current </li></ul></ul></ul><ul><ul><ul><li>Postscaler is disabled - saves current </li></ul></ul></ul>
    18. 18. Clock System: INTRC <ul><li>INTRC enabled for </li></ul><ul><ul><li>Watch Dog Timer (check datasheet for periods) </li></ul></ul><ul><ul><ul><li>PIC16 - T WDT = 1ms (Nom.) </li></ul></ul></ul><ul><ul><ul><li>PIC18 - T WDT = 4ms (Nom.) </li></ul></ul></ul><ul><ul><li>Two-Speed Startup (Resets and Wake from SLEEP mode) </li></ul></ul><ul><ul><li>Fail-Safe Clock Monitor </li></ul></ul>
    19. 19. Clock System: OSCTUNE <ul><li>OSCTUNE register </li></ul><ul><ul><li>User adjustable FREQUENCY </li></ul></ul><ul><ul><ul><li>6-bits, range is up to ±12.5%, 0.4% / step </li></ul></ul></ul><ul><ul><ul><li>Affects </li></ul></ul></ul><ul><ul><ul><ul><li>8MHz INTOSC output frequency </li></ul></ul></ul></ul><ul><ul><ul><ul><li>31kHz INTRC output frequency </li></ul></ul></ul></ul><ul><ul><ul><ul><li>WDT period </li></ul></ul></ul></ul><ul><ul><ul><ul><li>Fail-Safe Clock Monitor period </li></ul></ul></ul></ul><ul><ul><ul><ul><li>2-Speed Start-up frequency </li></ul></ul></ul></ul>
    20. 20. Clock System: INTOSC Freq and Status <ul><li>When clocking from the INTOSC block, code can select a higher clock frequency when required for </li></ul><ul><ul><li>Greater workload - CPU must do more work </li></ul></ul><ul><ul><li>Peripherals need higher speed clock </li></ul></ul><ul><li>Code can select lower frequency </li></ul><ul><ul><li>Light workload </li></ul></ul><ul><ul><li>Peripherals can use lower resolution clock </li></ul></ul><ul><ul><li>Reduce current consumption </li></ul></ul>
    21. 21. Clock System: INTOSC Freq and Status <ul><li>Select desired INTOSC Frequency </li></ul><ul><ul><li>IOFS gets set when INTOSC becomes stable </li></ul></ul>
    22. 22. Clock System: OSCCON Register IDLEN Controls CPU clocking (PIC18 Only) IRCF<2:0> Selects tap from INTOSC Postscaler OSTS =1 if Primary clock is currently providing the system clock IOFS =1 if INTOSC (8 MHz) output is stable SCS<1:0> Selects the power managed mode clock source
    23. 23. Clock System: Clock Switching <ul><li>Modifying IRCF<2:0> bits immediately selects a different INTOSC postscaler tap </li></ul><ul><li>If V DD <2.9V, care must be taken to avoid selecting the 8MHz output by mistake </li></ul><ul><ul><li>CPU may not operate properly outside specified Frequency / V DD limits </li></ul></ul><ul><li>Recommended Procedure </li></ul><ul><ul><li>Read OSCCON to shadow register </li></ul></ul><ul><ul><li>Modify shadow </li></ul></ul><ul><ul><li>Write shadow back to OSCCON </li></ul></ul>
    24. 24. Clock System: INTOSC Frequency Switch <ul><li>; This code safely modifies OSCCON </li></ul><ul><li>movf OSCCON,W ; copy OSCCON to WREG </li></ul><ul><li>andlw B’10001111’ ; clear IRCF bits </li></ul><ul><li>iorlw B’01010000’ ; new IRCF bits (2MHz) </li></ul><ul><li>movwf OSCCON ; copy result to OSCCON </li></ul><ul><li>; This eliminates the possibility of selecting ; 8MHz even for one instruction cycle. </li></ul><ul><li>; Operations on OSCCON,IRCF bits have ; immediate effects! </li></ul>
    25. 25. Topics <ul><li>What is nanoWatt Technology? </li></ul><ul><li>Clock System </li></ul><ul><li>2-Speed Start-up </li></ul><ul><li>Fail-Safe Clock Monitor (FSCM) </li></ul><ul><li>Watch Dog Timer (WDT) </li></ul><ul><li>Power Managed Modes </li></ul><ul><ul><li>Clock Sources and Clock Status Flags </li></ul></ul><ul><ul><li>Entry and Exit from Power Managed Modes </li></ul></ul><ul><ul><li>Discuss each mode </li></ul></ul>
    26. 26. Two Speed Start-up: Overview <ul><li>Allows code execution to start before the Primary clock source becomes ready </li></ul><ul><li>Internal Oscillator Block (IOB) provides clocks before Primary clock source becomes ready </li></ul><ul><li>Automatically switches to Primary when it becomes ready </li></ul><ul><li>Used for </li></ul><ul><ul><li>Start from Reset </li></ul></ul><ul><ul><li>Wake from SLEEP Mode </li></ul></ul>
    27. 27. Two Speed Start-up: Operation <ul><li>Primary clocks might not be available due to startup delays </li></ul><ul><ul><li>Crystal / Resonator oscillator start time </li></ul></ul><ul><ul><li>OST delay (counts 1024 oscillator cycles) </li></ul></ul><ul><ul><li>PLL delay (additional 2ms delay for HS/PLL) </li></ul></ul><ul><li>The IOB can provide system clocks during this time </li></ul><ul><ul><li>Code can select operating frequency </li></ul></ul><ul><ul><li>Code may finish work quickly and go back to SLEEP before Primary is ready </li></ul></ul>
    28. 28. Two Speed Start-up: Operation <ul><li>When primary becomes ready </li></ul><ul><ul><li>Clock source switched to Primary clock </li></ul></ul><ul><ul><li>OSTS (OSCCON<3>) is set </li></ul></ul><ul><ul><li>IOB may shut down </li></ul></ul><ul><ul><ul><li>INTRC may be required for other features </li></ul></ul></ul><ul><ul><ul><ul><li>Watch Dog Timer (WDT) </li></ul></ul></ul></ul><ul><ul><ul><ul><li>Fail-Safe Clock Monitor (FSCM) </li></ul></ul></ul></ul>
    29. 29. Two Speed Start-up: Operation <ul><li>Enable by setting the IESO bit (_CONFIG2<1>) (PIC16) (_CONFIG1H<7>) (PIC18) (Internal External Switch Over) </li></ul><ul><li>Used with crystal based modes only </li></ul><ul><ul><li>OST delay used with crystal modes (LP, XT, HS, and HS/PLL modes) </li></ul></ul><ul><ul><li>HS/PLL (PIC18) adds 2ms </li></ul></ul><ul><ul><li>Other oscillator modes do not require 2-speed startups </li></ul></ul>
    30. 30. Two Speed Start-up: Assumptions <ul><li>Compare INTRC speed to typical crystal startup times and delays </li></ul><ul><ul><li>LP mode oscillators start in 100’s of mS </li></ul></ul><ul><ul><li>XT mode oscillators start in 1’s of mS </li></ul></ul><ul><ul><li>HS mode oscillators start in 10’s of uS </li></ul></ul><ul><ul><li>HS/PLL mode starts in 2ms (PLL start delay) </li></ul></ul><ul><li>CPU requires 5 - 10 uS following wake event to become ready to execute code </li></ul><ul><ul><li>Assume 7us </li></ul></ul>
    31. 31. Two Speed Start-up: Assumptions <ul><li>Wake from SLEEP mode </li></ul><ul><li>OSCCON register loaded before entering SLEEP mode </li></ul><ul><ul><li>31 kHz for LP mode (same as crystal) </li></ul></ul><ul><ul><li>4 MHz for XT mode (same as crystal) </li></ul></ul><ul><ul><li>8 MHz for HS and HS/PLL modes </li></ul></ul>
    32. 32. Two Speed Start-up: What to expect <ul><li>32.7 kHz LP mode (30.5us, 1T CY =122 us) </li></ul><ul><li>Without Two-Speed Start </li></ul><ul><ul><li>Crystal oscillator starts in about 750 ms </li></ul></ul><ul><ul><li>OST adds 31.3 ms (1024 * 30.5 us = 31.3 ms) </li></ul></ul><ul><ul><li>781 ms before instructions begin executing </li></ul></ul><ul><li>With Two-Speed Start (INTRC @ 31 kHz, 1 T CY = 128 us) </li></ul><ul><ul><li>CPU requires 7us to start from wake </li></ul></ul><ul><ul><li>In 774 ms, 6.0k instructions could be executed before clock switch occurs </li></ul></ul>
    33. 33. Two Speed Start-up: What to expect <ul><li>4 MHz XT mode (250ns, 1T CY =1us) </li></ul><ul><li>Without Two-Speed Start </li></ul><ul><ul><li>Crystal oscillator starts in about 1 ms </li></ul></ul><ul><ul><li>OST adds 256 us (1024 * .25 us = 256 us) </li></ul></ul><ul><ul><li>1.26 ms before instructions begin executing </li></ul></ul><ul><li>With Two-Speed Start (INTOSC @ 4MHz, T CY = 1us) </li></ul><ul><ul><li>In 1.25 ms, 1.25K instructions could be executed before clock switch occurs </li></ul></ul>
    34. 34. Two Speed Start-up: What to expect <ul><li>20MHz HS mode (T OSC =50ns, 1T CY =200ns) </li></ul><ul><li>Without Two-Speed Start </li></ul><ul><ul><li>Crystal oscillator starts in about 10 us </li></ul></ul><ul><ul><li>OST adds 51.2 us (1024 * .05 us = 51.2 us) </li></ul></ul><ul><ul><li>61.2 uS before instructions begin executing </li></ul></ul><ul><li>With Two-Speed Start (INTOSC @ 8MHz, 1 T CY = 500 ns) </li></ul><ul><ul><li>CPU requires 7us to start from wake </li></ul></ul><ul><ul><li>In 54.4 uS, 109 instructions could be executed before clock switch occurs </li></ul></ul>
    35. 35. Two Speed Start-up: What to expect <ul><li>40MHz HS/PLL mode (25ns , 1T CY =100ns) </li></ul><ul><li>Without Two-Speed Start </li></ul><ul><ul><li>Crystal oscillator (10MHz) starts in about 10 us </li></ul></ul><ul><ul><li>OST adds 102 us (1024 * 0.1 us = 102 us) </li></ul></ul><ul><ul><li>PLL adds 2ms (dominates startup delays) </li></ul></ul><ul><ul><li>2.1 ms before instructions begin executing </li></ul></ul><ul><li>With Two-Speed Start (INTOSC @ 8MHz, 1 T CY = 500 ns) </li></ul><ul><ul><li>CPU requires 7us to start from wake </li></ul></ul><ul><ul><li>In 2.1 ms, 4.2k instructions could be executed before clock switch </li></ul></ul>
    36. 36. Topics <ul><li>What is nanoWatt Technology? </li></ul><ul><li>Clock System </li></ul><ul><li>2-Speed Start-up </li></ul><ul><li>Fail-Safe Clock Monitor (FSCM) </li></ul><ul><li>Watch Dog Timer (WDT) </li></ul><ul><li>Power Managed Modes </li></ul><ul><ul><li>Clock Sources and Clock Status Flags </li></ul></ul><ul><ul><li>Entry and Exit from Power Managed Modes </li></ul></ul><ul><ul><li>Discuss each mode </li></ul></ul>
    37. 37. Fail-Safe Clock Monitor (FSCM) <ul><li>How Does It Work? </li></ul><ul><li>How To Enable It </li></ul><ul><ul><li>When is it used </li></ul></ul><ul><li>Operation During </li></ul><ul><ul><li>Clock Source Failure </li></ul></ul><ul><ul><li>System Start-Up </li></ul></ul><ul><ul><li>Wake from SLEEP mode </li></ul></ul>
    38. 38. FSCM: How Does It Work? Sample Clock (INTRC/64 - Clear) Peripheral Clock (Clock/4 - Set) CM F/F Q Output OSCFIF Oscillator Failure Failure Detected Set OSCFIF INTRC (32 us)  64 Set Q Clear !Q Peripheral clock Clock Monitor F/F ~2ms period CM F/F Tested CM F/F Tested CM F/F Tested
    39. 39. FSCM: How To Enable <ul><li>Enable by setting the FSCMEN bit (_CONFIG2<0>) (PIC16) (_CONFIG1H<6>) (PIC18) (Fail-Safe Clock Monitor ENable) </li></ul><ul><li>Used to detect a loss of externally based clocked sources </li></ul><ul><ul><li>Only IOB is fully internal </li></ul></ul>
    40. 40. FSCM: During Failure <ul><li>On Primary or Secondary clock failure </li></ul><ul><ul><li>Clears WDT (may not be enabled) </li></ul></ul><ul><ul><li>Clock source switched to IOB </li></ul></ul><ul><ul><ul><li>OSTS is cleared if Primary failed </li></ul></ul></ul><ul><ul><ul><li>T1RUN (T1CON<6>) cleared if Secondary failed </li></ul></ul></ul><ul><ul><ul><li>OSCCON is NOT updated </li></ul></ul></ul><ul><ul><li>OSCFIF (PIR2<7>) is set </li></ul></ul><ul><ul><ul><li>If interrupts enabled, causes wake without clock switch to Primary clock source </li></ul></ul></ul>
    41. 41. <ul><li>When clocked by internal RC clock source </li></ul><ul><ul><li>If IRCF bits are = 000 </li></ul></ul><ul><ul><ul><li>Clocked from INTRC at 31kHz </li></ul></ul></ul><ul><ul><li>If IRCF bits are  000 </li></ul></ul><ul><ul><ul><li>Clocked from INTOSC at higher speed </li></ul></ul></ul><ul><ul><ul><li>The IRCF bits may be set prior to the clock failure, i.e. during device startup </li></ul></ul></ul>FSCM: During Failure
    42. 42. FSCM: Normal Startup (Reset or Wake from SLEEP) <ul><li>During start-up (reset or wake from sleep) </li></ul><ul><ul><li>Internal Oscillator Block provides system clocks until Primary clock is ready (similar to 2-speed start) </li></ul></ul><ul><ul><li>When the primary is ready, an automatic clock switch selects the primary clock </li></ul></ul><ul><ul><li>FSCM then becomes active, and OSTS is set </li></ul></ul><ul><ul><li>INTOSC (8MHz) is disabled </li></ul></ul><ul><ul><ul><li>INTRC (31 kHz) runs for FSCM (and WDT) </li></ul></ul></ul><ul><ul><li>This prevents false fails at startup </li></ul></ul>
    43. 43. FSCM: Startup with Failed Primary <ul><li>During start-up (reset or wake from sleep) </li></ul><ul><ul><li>If the Primary clock never becomes ready, no clock failure will be detected </li></ul></ul><ul><ul><ul><li>Firmware will need to detect this condition </li></ul></ul></ul><ul><ul><ul><ul><li>Check OSTS flag after suitable delay </li></ul></ul></ul></ul><ul><ul><ul><li>FSCM becomes active if SEC_(mode) is selected before Primary becomes ready </li></ul></ul></ul>
    44. 44. Topics <ul><li>What is nanoWatt Technology? </li></ul><ul><li>Clock System </li></ul><ul><li>2-Speed Start-up </li></ul><ul><li>Fail-Safe Clock Monitor (FSCM) </li></ul><ul><li>Watch Dog Timer (WDT) </li></ul><ul><li>Power Managed Modes </li></ul><ul><ul><li>Clock Sources and Clock Status Flags </li></ul></ul><ul><ul><li>Entry and Exit from Power Managed Modes </li></ul></ul><ul><ul><li>Discuss each mode </li></ul></ul>
    45. 45. Watch Dog Timers <ul><li>General WDT </li></ul><ul><ul><li>PIC16 WDT </li></ul></ul><ul><ul><li>PIC18 WDT </li></ul></ul>
    46. 46. Watch Dog Timers <ul><li>Clocked by INTRC (32us period) </li></ul><ul><li>Has same characteristics as INTRC across temperature and V DD </li></ul><ul><ul><li>Greatly improved stability compared with previous WDTs </li></ul></ul><ul><li>WDT may be enabled by firmware if configured disabled by configuration word </li></ul><ul><ul><li>SWDTEN (WDTCON<0>) </li></ul></ul>
    47. 47. Watch Dog Timer: PIC16 <ul><li>PSA = 0 </li></ul><ul><ul><li>OPTION postscaler assigned to TMR0 </li></ul></ul><ul><ul><li>WDT uses only WDTCON postscaler </li></ul></ul><ul><li>PSA = 1 </li></ul><ul><ul><li>OPTION postscaler assigned to WDT </li></ul></ul><ul><ul><li>WDT uses both postscalers </li></ul></ul>1ms - 2.097s INTRC (31kHz) 16-bit Postscaler WDT Time-out TMR0 Sync TMR0 Register RA4 / T0CKI Fosc/4 TMR0IF PSA T0CS 0 1 1 1 1 8-bit Postscaler 0 0 0 OPTION PS<2:0> WDTCON WDTPS<3:0> 32us INTOSC (8MHz) PSA PSA (resets to 1:512) (16.4ms)
    48. 48. Watch Dog Timer: PIC16 <ul><li>WDTCON controls WDTCON postscaler </li></ul><ul><ul><li>Ratios 1:32 to 1:64K (1ms to 2.1s) </li></ul></ul><ul><ul><li>Resets to 1:512 (16.4ms) </li></ul></ul><ul><li>OPTION_REG controls OPTION postscaler </li></ul><ul><ul><li>Ratios 1:1 to 1:128 </li></ul></ul><ul><ul><li>Timer0 and WDT share postscaler </li></ul></ul><ul><li>Postscalers may be used in series </li></ul><ul><ul><li>Ratios 1:1 to 1:8.4M </li></ul></ul><ul><ul><li>Time-out range: 1ms to 268 sec / 4.5 min </li></ul></ul>
    49. 49. Clock System: PIC18 Prescaler Timer1 Oscillator Primary Oscillator (RC, EC, LP, XT, HS, HSPLL) IDLE Mode Timer 1 Enable To CPU Clock To Peripherals To Timer 1 INTRC (31kHz) Post- 1:2 scaler 1:4 1:8 1:16 1:32 1:64 INTOSC (8 MHz) CONFIG1H & OSCCON 32us 1:125 4ms WDT Time-out FS Clock Monitor WDT Postscaler 1:1 to 1:32768 Bias
    50. 50. Watch Dog Timer: PIC18 <ul><li>WDT postscaler offers more ratios </li></ul><ul><ul><li>WDT period is 4.0 ms (125 * 32us) </li></ul></ul><ul><ul><li>1:1 to 1:32,768 (4 ms to 131 sec / 2.2 min) </li></ul></ul><ul><ul><li>Ratio selected by CONFIG2H (fixed) </li></ul></ul>
    51. 51. Topics <ul><li>What is nanoWatt Technology? </li></ul><ul><li>Clock System </li></ul><ul><li>2-Speed Start-up </li></ul><ul><li>Fail-Safe Clock Monitor (FSCM) </li></ul><ul><li>Watch Dog Timer (WDT) </li></ul><ul><li>Power Managed Modes </li></ul><ul><ul><li>Clock Sources and Clock Status Flags </li></ul></ul><ul><ul><li>Entry and Exit from Power Managed Modes </li></ul></ul><ul><ul><li>Discuss each mode </li></ul></ul>
    52. 52. Power Managed Modes <ul><li>How to reduce current consumption? </li></ul><ul><ul><li>Disable a clock source that is not needed </li></ul></ul><ul><ul><li>Disable clocks to peripherals and/or CPU </li></ul></ul><ul><ul><li>Select a lower clock frequency </li></ul></ul><ul><ul><ul><li>Clock peripherals at lower speed </li></ul></ul></ul><ul><ul><ul><li>Execute code at lower speed </li></ul></ul></ul><ul><ul><li>Reduce or eliminate startup delays </li></ul></ul><ul><ul><li>Use low power peripherals </li></ul></ul>
    53. 53. Power Managed Modes <ul><li>What are Power Managed Modes? </li></ul><ul><li>Clock Sources </li></ul><ul><li>Clock switch example </li></ul><ul><li>Clock source status Flags </li></ul><ul><li>CPU Operation (PIC18 only) </li></ul><ul><li>Entry to Power Managed Modes </li></ul><ul><li>Exit from Power Managed Modes </li></ul>
    54. 54. Power Managed Modes: What are they? <ul><li>Power Managed Modes allow the user to: </li></ul><ul><ul><li>Select System clock source </li></ul></ul><ul><ul><li>Select System clock frequency </li></ul></ul><ul><ul><li>Disable clocks to the CPU (PIC18 only) </li></ul></ul><ul><li>These options provide code with the means to control power consumption as needed </li></ul>
    55. 55. Power Managed Modes: Clock Sources <ul><li>Select desired clock source </li></ul><ul><ul><li>Most Primary clock sources are fixed frequency (i.e. not controllable by code) </li></ul></ul><ul><ul><li>Secondary clock source (Timer1 Oscillator) is fixed frequency </li></ul></ul><ul><ul><ul><li>Required for Real-Time Clock time base </li></ul></ul></ul><ul><ul><li>Internal Oscillator Block allows selection of clock frequency </li></ul></ul><ul><ul><ul><li>Code can select system frequency according to need </li></ul></ul></ul>
    56. 56. Power Managed Modes: Clock Sources <ul><li>Select desired clock source </li></ul><ul><ul><li>Set the SCS<1:0> bits (OSCCON(<1:0>) for the desired clock source </li></ul></ul><ul><ul><ul><li>PRI = 00 SEC = 01 INTOSC = 1X </li></ul></ul></ul><ul><ul><li>PIC18 - Execute SLEEP instruction </li></ul></ul><ul><ul><li>PIC16 - Clock switch is immediate </li></ul></ul><ul><ul><ul><li>Consider using a shadow register </li></ul></ul></ul>
    57. 57. Power Managed Modes: Clock Switching Example <ul><li>Switching from XT (old) to Timer1 (new) </li></ul><ul><ul><li>Execution pauses at the end of Q4 clock </li></ul></ul><ul><ul><li>8 cycles from the new clock are counted </li></ul></ul><ul><ul><li>Execution resumes clocked by the new clock </li></ul></ul><ul><li>This example is repeated for every clock switching event </li></ul>OSC1 TMR1 SysClk Q1 Q2 Q3 Q4 Q1 Q2 Q3 1 2 7 8 // Q4 Execution Pauses for 8 of the new clocks Original clock is disabled (shut down)
    58. 58. Power Managed Modes: Clock Status Flags <ul><li>Each clock source sets a status bit to indicate when it is providing the system clock </li></ul><ul><ul><li>Primary clock - OSTS bit (OSCCON<3>) </li></ul></ul><ul><ul><li>Secondary clock - T1RUN bit (T1CON<6>) </li></ul></ul><ul><ul><li>Internal Oscillator Block - IOFS bit (OSCCON<2>) </li></ul></ul><ul><li>Only one clock status bit will be set at any time </li></ul>
    59. 59. Power Managed Modes: Clock Status Flags <ul><li>If no bits are set, </li></ul><ul><ul><li>INTOSC is providing clocks but not yet stable </li></ul></ul><ul><ul><ul><li>OR </li></ul></ul></ul><ul><ul><li>INTRC is providing clocks at 31kHz </li></ul></ul><ul><ul><li>To determine IOB clock source, check </li></ul></ul><ul><ul><ul><li>IOFS bit after suitable delay or </li></ul></ul></ul><ul><ul><ul><li>IRCF bits </li></ul></ul></ul>
    60. 60. Power Managed Modes: Clock Status Flags <ul><li>IOFS always =0 if IRCF<2:0>=000 (31kHz) </li></ul><ul><li>IOFS set after startup delay if IRCF<2:0> =000 </li></ul>
    61. 61. Power Managed Modes
    62. 62. PRI_RUN Mode <ul><li>This is the normal full power execution mode </li></ul><ul><li>Exits from all other power managed modes return to PRI_RUN mode </li></ul><ul><li>CPU and peripherals are clocked by Primary clock source </li></ul><ul><ul><li>T1RUN, IOFS cleared OSTS set </li></ul></ul>
    63. 63. <ul><li>This is the sleep mode in other Microchip controllers </li></ul><ul><li>IDLEN = 0 (PIC18 only), SCS<1:0> = 00 </li></ul><ul><li>Execute SLEEP instruction </li></ul><ul><ul><li>CPU not clocked </li></ul></ul><ul><ul><li>Peripherals depending on system clocks are not clocked </li></ul></ul><ul><ul><li>Primary oscillator is disabled </li></ul></ul><ul><li>This is the only power managed mode where no system clock sources are running </li></ul>SLEEP Mode
    64. 64. <ul><li>This mode replaces the clock switching mechanism in other PIC18 controllers </li></ul><ul><li>Adjust peripherals for T1OSC frequency </li></ul><ul><li>IDLEN = 0 (PIC18 only) , SCS<1:0> = 01 </li></ul><ul><li>Execute a SLEEP instruction (PIC18 only) </li></ul><ul><ul><li>CPU and Peripherals clocked using T1OSC </li></ul></ul><ul><ul><li>Primary oscillator is disabled </li></ul></ul><ul><ul><li>IOFS, OSTS cleared T1RUN set </li></ul></ul>SEC_RUN Mode
    65. 65. <ul><li>Adjust peripherals for new clock frequency </li></ul><ul><li>IRCF<2:0> selects clock speed (optional) </li></ul><ul><li>IDLEN = 0 (PIC18 only) , SCS<1:0> = 1X </li></ul><ul><li>Execute a SLEEP instruction (PIC18 only) </li></ul><ul><ul><li>Primary oscillator is disabled </li></ul></ul><ul><ul><li>CPU and Peripherals clocked using IOB </li></ul></ul><ul><ul><li>OSTS, T1RUN cleared </li></ul></ul><ul><ul><li>IOFS set after 1-4 ms delay if Freq  31 kHz </li></ul></ul><ul><ul><ul><li>Check datasheet for INTOSC delay </li></ul></ul></ul>RC_RUN Mode
    66. 66. Power Managed Modes: CPU Operation (PIC18 only) <ul><li>Code can disable clocks to the CPU </li></ul><ul><ul><li>Stops code execution without affecting peripheral operation </li></ul></ul><ul><ul><li>CPU is in a sleep-like state </li></ul></ul><ul><ul><li>WDT, Interrupts and resets restart CPU </li></ul></ul><ul><li>Disable CPU clocks by setting the IDLEN bit (OSCCON<7>) and executing a SLEEP instruction </li></ul>
    67. 67. IDLE Modes (PIC18 only) <ul><li>Configure IDLEN (OSCCON<7>) </li></ul><ul><ul><li>Choose whether CPU is clocked or not </li></ul></ul><ul><ul><li>Peripherals are always clocked </li></ul></ul><ul><ul><li>Sleep mode is exception - No clocks operate </li></ul></ul>
    68. 68. PRI_IDLE Mode (PIC18 only) <ul><li>IDLEN = 1, SCS<1:0> = 00 </li></ul><ul><li>Execute a SLEEP instruction </li></ul><ul><ul><li>CPU not clocked </li></ul></ul><ul><ul><li>Peripherals that need system clocks are clocked by Primary oscillator </li></ul></ul><ul><ul><li>Primary oscillator is continues to run </li></ul></ul>
    69. 69. SEC_IDLE Mode (PIC18 only) <ul><li>Adjust peripherals for new clock frequency </li></ul><ul><li>IDLEN = 1, SCS<1:0> = 01 </li></ul><ul><li>Execute a SLEEP instruction </li></ul><ul><ul><li>CPU not clocked </li></ul></ul><ul><ul><li>Peripherals that need system clocks are clocked by T1OSC oscillator </li></ul></ul><ul><ul><li>Primary oscillator is disabled </li></ul></ul><ul><ul><li>OSTS, IOFS cleared T1RUN set </li></ul></ul>
    70. 70. RC_IDLE Mode (PIC18 only) <ul><li>IDLEN = 1, SCS<1:0> = 1X </li></ul><ul><li>Adjust peripherals for new clock frequency </li></ul><ul><li>Execute a SLEEP instruction </li></ul><ul><ul><li>CPU not clocked </li></ul></ul><ul><ul><li>Peripherals that need system clocks are clocked by Internal Oscillator Block </li></ul></ul><ul><ul><li>Primary oscillator is disabled </li></ul></ul><ul><ul><li>OSTS, T1RUN cleared IOFS may be set after delay </li></ul></ul>
    71. 71. (any)_RUN to (same)_IDLE (PIC18 only) <ul><li>; Switch from (any)_RUN to (same)_IDLE </li></ul><ul><li>; Uses same clock source / frequency </li></ul><ul><li>bsf OSCCON,IDLEN ; select IDLE mode </li></ul><ul><li>sleep ; enters (*)_IDLE mode </li></ul><ul><li>; Execution pauses here, waits for </li></ul><ul><li>; wake by interrupt, reset, </li></ul><ul><li>; or WDT timeout. </li></ul><ul><li>; CPU not clocked, peripherals run from </li></ul><ul><li>; same clock source (not changed). </li></ul>
    72. 72. Exit from Power Managed Mode <ul><li>What wakes a device from SLEEP? (Any controller, not just nanoWatt) </li></ul><ul><ul><li>Any Interrupt </li></ul></ul><ul><ul><li>Any Reset </li></ul></ul><ul><ul><li>WDT time-out </li></ul></ul>
    73. 73. Exit from Power Managed Mode <ul><li>On Exit by Interrupt </li></ul><ul><ul><li>Program flow is controlled GIE/GIEH </li></ul></ul><ul><ul><ul><li>If set, branch to ISR </li></ul></ul></ul><ul><ul><ul><li>If clear, resume at next instruction </li></ul></ul></ul><ul><ul><li>Primary clock is started (if not already running) </li></ul></ul><ul><ul><ul><li>Automatic clock switch occurs if / when Primary becomes ready </li></ul></ul></ul>
    74. 74. Exit from Power Managed Mode <ul><li>On Exit by Interrupt </li></ul><ul><ul><li>CPU and peripherals are clocked using selected clock until Primary becomes ready </li></ul></ul><ul><ul><li>Exit from SLEEP mode: </li></ul></ul><ul><ul><ul><li>No clock is selected, execution resumes when Primary becomes ready </li></ul></ul></ul><ul><ul><ul><li>Execution can begin immediately if either Two-Speed Startup or Fail-Safe Clock Monitor is enabled </li></ul></ul></ul>
    75. 75. Exit from Power Managed Mode <ul><li>On Exit by Reset </li></ul><ul><ul><li>Primary clock is started </li></ul></ul><ul><ul><li>Execution pauses until Primary becomes ready </li></ul></ul><ul><ul><ul><li>Execution can begin immediately if either Two-Speed Startup or Fail-Safe Clock Monitor is enabled </li></ul></ul></ul><ul><ul><ul><li>OSTS bit in OSCCON register is set when Primary is providing system clocks </li></ul></ul></ul>
    76. 76. Exit from Power Managed Mode <ul><li>On Exit by WDT Time-out </li></ul><ul><ul><ul><li>Reset if in any RUN mode (CPU clocked, executing code) </li></ul></ul></ul><ul><ul><ul><li>Wake if in SLEEP or any IDLE mode (CPU not clocked, not executing code) </li></ul></ul></ul><ul><ul><li>TO bit is cleared PIC16 - STATUS<4> PIC18 - RCON<3> </li></ul></ul><ul><ul><li>Exit process depends on if CPU was executing code </li></ul></ul>
    77. 77. Lab Exercises <ul><li>Please choose a device to use </li></ul><ul><li>for the labs that follow: </li></ul><ul><li>PIC16F88 </li></ul><ul><li>or </li></ul><ul><li>PIC18F1320 </li></ul>
    78. 78. Lab #1 - Fail-Safe Clock Monitor <ul><ul><li>Configure code for 8 MHz Canned Oscillator. </li></ul></ul><ul><ul><li>Write code to handle Fail-Safe interrupt. </li></ul></ul><ul><ul><li>When the Fail-Safe interrupt occurs, the code should operate as before the Fail-Safe condition was detected. </li></ul></ul><ul><ul><li>Hints: </li></ul></ul><ul><ul><ul><li>____________________ </li></ul></ul></ul><ul><ul><ul><li>____________________ </li></ul></ul></ul><ul><ul><ul><li>____________________ </li></ul></ul></ul><ul><ul><ul><li>____________________ </li></ul></ul></ul>
    79. 79. Lab #2 - Clock Switching <ul><ul><li>Configure the clock system to minimize current consumption. </li></ul></ul><ul><ul><li>Communication to the I/O expander (and LCD) cannot be affected. </li></ul></ul><ul><ul><li>Measure I DD </li></ul></ul><ul><ul><li>Hints: </li></ul></ul><ul><ul><ul><li>____________________ </li></ul></ul></ul><ul><ul><ul><li>____________________ </li></ul></ul></ul><ul><ul><ul><li>____________________ </li></ul></ul></ul><ul><ul><ul><li>____________________ </li></ul></ul></ul>
    80. 80. Lab #3 - Analog I/O Pin <ul><ul><li>Write code in the Voltmeter block that minimizes current consumption. </li></ul></ul><ul><ul><li>Measure I DD </li></ul></ul><ul><ul><li>Hints: </li></ul></ul><ul><ul><ul><li>____________________ </li></ul></ul></ul><ul><ul><ul><li>____________________ </li></ul></ul></ul><ul><ul><ul><li>____________________ </li></ul></ul></ul><ul><ul><ul><li>____________________ </li></ul></ul></ul>
    81. 81. Lab #4 - Communication <ul><ul><li>Review the PICDEM™ 4 Schematic </li></ul></ul><ul><ul><li>Write code in the AUSART block that minimizes current consumption. </li></ul></ul><ul><ul><li>Measure I DD </li></ul></ul><ul><ul><li>Hints: </li></ul></ul><ul><ul><ul><li>____________________ </li></ul></ul></ul><ul><ul><ul><li>____________________ </li></ul></ul></ul><ul><ul><ul><li>____________________ </li></ul></ul></ul><ul><ul><ul><li>____________________ </li></ul></ul></ul>
    82. 82. Lab #5 - Real Time Clock <ul><ul><li>Write code within the Timer 1 block that minimizes current consumption. </li></ul></ul><ul><ul><li>Measure I DD </li></ul></ul><ul><ul><li>Hints: </li></ul></ul><ul><ul><ul><li>____________________ </li></ul></ul></ul><ul><ul><ul><li>____________________ </li></ul></ul></ul><ul><ul><ul><li>____________________ </li></ul></ul></ul><ul><ul><ul><li>____________________ </li></ul></ul></ul>
    83. 83. 704 NWF Low Power Features of the nanoWatt Family Devices

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