Your SlideShare is downloading. ×
Reporte vhdl9
Upcoming SlideShare
Loading in...5
×

Thanks for flagging this SlideShare!

Oops! An error has occurred.

×
Saving this for later? Get the SlideShare app to save on your phone or tablet. Read anywhere, anytime – even offline.
Text the download link to your phone
Standard text messaging rates apply

Reporte vhdl9

133
views

Published on

practicas realizadas en la clase de vhdl (programacion ) unidad 2 . REALIZADO CON EN Kit basys2

practicas realizadas en la clase de vhdl (programacion ) unidad 2 . REALIZADO CON EN Kit basys2

Published in: Education, Technology, Design

0 Comments
0 Likes
Statistics
Notes
  • Be the first to comment

  • Be the first to like this

No Downloads
Views
Total Views
133
On Slideshare
0
From Embeds
0
Number of Embeds
0
Actions
Shares
0
Downloads
2
Comments
0
Likes
0
Embeds 0
No embeds

Report content
Flagged as inappropriate Flag as inappropriate
Flag as inappropriate

Select your reason for flagging this presentation as inappropriate.

Cancel
No notes for slide

Transcript

  • 1. SEP DGEST INSTITUTO TECNOLÓGICO SNEST DE MATAMOROS DEPARTAMENTO DE INGENIERÍA ELÉCTRICA Y ELECTRÓNICA Diseño Digital con VHDL Equipo: Alumno(s): Núm. de control: Mario Arturo Cruz Colunga 11260077 Miguel Angel Fierros Peña 11260081 Hermenegildo Martínez de la Cruz 11260095 Jorge Alejandro Reyes Torres 11260108 H. MATAMOROS, TAM. 1 de Noviembre del 2013
  • 2. Practica 9 Objetivo: Realizar la implementación de un cronometro de 2 dígitos mediante aldechdl y basys2. Material: Laptop Kit spartan3e Software aldec HDL, xilinx ISE, adept. Procedimiento: Se crea nuevo proyecto en aldec HDL Se crea un diagrama de estados Clocksecond. library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entityclockSecondis port ( rst : in std_logic; clk : in std_logic; clkOut : outstd_logic ); endclockSecond; architecturebehavioral of clockSecondis -- signalassignments signalcounter : std_logic_Vector (27 downto 0); signalclkOutSignal : std_logic; begin process (clk, rst) begin if (rst = '1') then clkOutSignal<= '0'; counter<= (others => '0'); elsif (clk'event and clk = '1') then if (counter = "1011111010111100001000000")then counter<= (others => '0'); clkOutSignal<= notclkOutSignal; else counter<= counter + 1; endif; endif; endprocess; -- output assignments clkOut<= clkOutSignal; endbehavioral;
  • 3. Counter7seg library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity binary7decoder is port ( binaryIn : in std_logic_vector (3 downto 0); sevenSegment : outstd_logic_vector (7 downto 0)); end binary7decoder; architecturebehavioral of binary7decoder is -- signaldeclerations signalsevenSegmentSignal : std_logic_vector (7 downto 0); begin process (binaryIn) begin casebinaryInis when "0000" => sevenSegmentSignal (6 downto 0) <= "1000000"; when "0001" => sevenSegmentSignal (6 downto 0) <= "1111001"; when "0010" => sevenSegmentSignal (6 downto 0) <= "0100100"; when "0011" => sevenSegmentSignal (6 downto 0) <= "0110000"; when "0100" => sevenSegmentSignal (6 downto 0) <= "0011001"; when "0101" => sevenSegmentSignal (6 downto 0) <= "0010010"; when "0110" => sevenSegmentSignal (6 downto 0) <= "0000010"; when "0111" => sevenSegmentSignal (6 downto 0) <= "1111000"; when "1000" => sevenSegmentSignal (6 downto 0) <= "0000000"; whenothers => sevenSegmentSignal (6 downto 0) <= "0010000"; end case; endprocess; -- dpisalwayszero sevenSegmentSignal(7) <= '1'; -- output assignments sevenSegment<= sevenSegmentSignal; endbehavioral;
  • 4. binary7decoder library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity counter7seg is port ( clk : in std_logic; rst : in std_logic; start : in std_logic; pause : in std_logic; continue : in std_logic; digitOne : outstd_logic_vector (3 downto 0); digitTen : outstd_logic_vector (3 downto 0) ); end counter7seg; architecturebehavioral of counter7seg is -- signalassignments signaldigitOneSignal : std_logic_vector (3 downto 0); signaldigitTenSignal : std_logic_vector (3 downto 0); typestatesis (resetState, countState, pauseState); signalstate : states; begin process (clk, rst) begin if (rst = '1') then state<= resetState; elsif (clk'event and clk = '1') then casestateis whenresetState => digitOneSignal<= (others => '0'); digitTenSignal<= (others => '0'); if (start = '1') then state<= countState; endif; whencountState => if (pause = '1') then state<= pauseState; endif; if (digitOneSignal = "1001") then digitOneSignal<= (others => '0'); digitTenSignal<= digitTenSignal + '1';
  • 5. if (digitTenSignal = "1001") then digitTenSignal<= (others => '0'); endif; else digitOneSignal<= digitOneSignal + '1'; endif; whenpauseState => if (continue = '1') then state<= countState; endif; end case; endif; endprocess; -- output signalassignments digitOne<= digitOneSignal; digitTen<= digitTenSignal; endbehavioral; anodecontroller library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entityanodeControlleris port ( clk : in std_logic; an0 :outstd_logic; an1 :outstd_logic; an2 :outstd_logic; an3 :outstd_logic ); endanodeController; architecturebehavioral of anodeControlleris -- signaldeclerations signal an0Signal : std_logic; signal an1Signal : std_logic; signal an2Signal : std_logic; signal an3Signal : std_logic; begin process (clk) begin if (clk = '0') then an2Signal <= '1';
  • 6. an3Signal <= '0'; else an2Signal <= '0'; an3Signal <= '1'; endif; endprocess; -- an0 & an1 are always '1' an0Signal <= '1'; an1Signal <= '1'; -- output assignments an0 <= an0Signal; an1 <= an1Signal; an2 <= an2Signal; an3 <= an3Signal; endbehavioral; anodeclock library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entityanodeClockis port ( rst : in std_logic; clk : in std_logic; clkOut : outstd_logic ); endanodeClock; architecturebehavioral of anodeClockis -- signalassignments signalcounter : std_logic_Vector (19 downto 0); signalclkOutSignal : std_logic; begin process (clk, rst) begin if (rst = '1') then clkOutSignal<= '0'; counter<= (others => '0'); elsif (clk'event and clk = '1') then if (counter = x"186a0")then counter<= (others => '0'); clkOutSignal<= notclkOutSignal; else counter<= counter + 1;
  • 7. endif; endif; endprocess; clkOut<= clkOutSignal; endbehavioral; sevenselect library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entitysevenSelectis port ( an2 : in std_logic; an3 : in std_logic; sevenOne : in std_logic_vector (7 downto 0); sevenTen : in std_logic_vector (7 downto 0); sevenOut : outstd_logic_vector (7 downto 0) ); endsevenSelect; architecturebehavioral of sevenSelectis -- signaldeclerations signalsevenOutSignal : std_logic_vector (7 downto 0); begin process (an2, an3, sevenOne, sevenTen) begin if (an2 = '1' and an3 = '0') then sevenOutSignal<= sevenTen; else sevenOutSignal<= sevenOne; endif; endprocess; -- output assignments sevenOut<= sevenOutSignal; endbehavioral;
  • 8. Diagrama bde top U1 rst rs t U2 c lk O ut c lk c lk clk an0 an1 an2 an3 an0 an1 an2 anodeClock U3 an3 anodeController rs t c lk O ut sevenOut(7:0) U5 c lk an2 clockSecond U4 U8 c lk start pause continue d ig itO ne (3:0 ) rs t d ig itT e n(3 :0 ) s tart b inary In(3 :0 ) s e v enO ut(7:0 ) an3 s e v enS eg m e nt(7:0 ) binary7decoder U6 s e v enO ne (7:0 ) s e v e nT e n(7 :0 ) sevenSelect p aus e b inary In(3 :0 ) s e v enS eg m e nt(7:0 ) c o ntinue counter7seg binary7decoder Observaciones y conclusiones: El programa realiza el conteo mediante 2 dígitos como lo hace un cronometro. Siendo la velocidad de conteo clocksecond, el conteo realizado por counter7seg, binary7decoder el decodificador a 7 segmentos y por digito y sevenselect el encargado de seleccionar cada uno de los digitos a mostrar a la velocidad de anodeclock.

×