XIO2200A PCI Express to 1394a Chip <ul><li>Source: T EXAS  I NSTRUMENTS </li></ul>
Introduction <ul><li>Purpose </li></ul><ul><ul><li>This training module will go over the basics of PCI Express, and introd...
What is PCI Express? <ul><li>PCI Express is a high speed, low voltage, differential serial communication interconnect betw...
Differences between PCI and PCI Express PCI Express PCI <ul><li>High-speed serial bus </li></ul><ul><li>Dual uni-direction...
PCI Express Terminology PCI Express Device A PCI Express Device B Link Lane Signal Wire
PCI Express Features <ul><li>Point-to-point connection </li></ul><ul><li>Serial bus requires fewer pins than parallel bus ...
PCI Express Topology * Borrowed from literature at PCI-SIG Developer’s Conference
Types of PCI Express Devices <ul><li>Physical Layer (PHY) Devices </li></ul><ul><ul><li>Used to interface the PCI Express ...
XIO2200A PCIe Endpoints <ul><li>Full x1 PCI Express throughput </li></ul><ul><li>Fully compliant with  </li></ul><ul><ul><...
Key Benefits <ul><li>Proven compatibility and interoperability with leading PCIe chipsets and 1394a devices </li></ul><ul>...
Block Diagram
XIO2200A Typical System Implementation
PCI Express Interface <ul><li>2.5 Gbps Transmit and Receive Link </li></ul><ul><ul><li>High-speed differential transmit an...
1394a Port Interface <ul><li>The cable not active (CNA) terminal (U09) is an output that reflects the state of the incomin...
GPIO Terminals <ul><li>GPIO0, GPIO1, GPIO3, GPIO6, and GPIO7: These terminals always operate as GPIO bits. </li></ul><ul><...
Summary <ul><li>PCI Express allows for: </li></ul><ul><ul><li>Higher, scalable bandwidth over PCI using less pins </li></u...
Additional Resource <ul><li>For ordering the XIO2200A, please click the part list or </li></ul><ul><li>Call our sales hotl...
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XIO2200A PCI Express to 1394a Chip

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This training module will go over the basics of PCI Express, and introduce XIO2200A 1394-based endpoint device

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  • Welcome to the training module on Texas Instruments XIO2200A PCI Express to 1394a Chip. This training module will go over the basics of PCI Express, including an overview of PCI Express, differences between PCI and PCI Express, and types of PCI Express devices. It will also introduce XIO2200A 1394-based endpoint device.
  • Over the past few years, the industry has started the migration from PCI to PCI Express. However, many designers and engineers still ask ‘What exactly is PCI Express’? As a starting point, PCI Express is a high speed, low voltage, differential serial communication interconnect between two devices. This point-to-point communication mechanism was defined by an industry consortium known as the Peripheral Component Interconnect Special Interest Group, or PCI-SIG. The first revision of the PCI Express Base Specification was in 2002, and multiple revisions have been made since then to make improvements. PCI Express can be broken down to two speed grades specified by PCI Express Base Specification: Gen1 at 2.5Gbps and Gen2 at 5.0Gbps. This training module will focus on Gen1 speeds of 2.5Gbps. PCI Express operates at a high-speed serial rate of 2.5Gbps and utilizes low-voltage differential signaling to achieve this. Coming from PCI, this technology doubles the existing theoretical bandwidth of PCI while also utilizing a much lower pin count.
  • This table illustrates some basic differences between PCI Express and traditional PCI. PCI Express utilizes a high-speed serial bus which uses low-voltage differential signaling to transmit data across the bus. This is a drastic change from the parallel bus PCI employed. PCI Express is also a point-to-point architecture, while PCI was a shared-bus architecture. With the high-bandwidth capability of PCI Express, isochronous data transfer is support and QoS is much improved over what PCI offered.
  • A physical connection between two PCI Express devices is broken down into sub-parts, as can be seen on the figure. A lane consists of signal pairs in each direction (dual simplex transmission), with each signal of the pair made up of two wires. These two wires are used to transmit the differential signals across the lane. The peak-to-peak signaling voltage at the transmitter ranges from 800mV to 1200mV, while the differential peak voltage is half of these values. Common mode voltage can be anywhere between 0 and 3.6V, making the transmission of data fairly low power. A full PCI Express link is a collection of one or more symmetric lanes in each direction, and combinations are specified by PCI-SIG in the base specification. A x1 Link consists of 1 Lane or 1 differential signal pair in each direction for a total of 4 signals. A x32 Link consists of 32 Lanes or 32 signal pairs in each direction for a total of 128 signals. Links can defined as x1, x2, x4, x8, x12, x16 or x32.
  • There are many attractive features that come built into the PCI Express specification. Besides have a point-to-point connection between two devices, utilizing a serial bus requires fewer pins in design versus that of PCI. With lane aggregation, PCI Express is very scalable to bandwidth-intensive applications. Since PCI Express evolved from PCI and PCI-X, migration is much easier. The same memory, I/O and configuration address space is used in PCI Express as was used in PCI. In addition, PCI Express has a higher QoS (quality of service) with improved data integrity and error handling. PCI Express is RAS-capable, and data integrity is available at both the link level and at the transmitter/receiver.
  • The basic PCI Express Topology includes 4 major components including the root complex, bridges, switches and endpoints. The root complex is the device that connects the CPU and memory subsystem to the total PCI Express fabric, and can support one or more PCI Express ports. The example in the page has 3 ports. A bridge device creates a bridge between PCI Express and another standard, typically a PCI or PCI-X hierarchy. A switch is used to expand the PCI Express fabric, utilizing virtual PCI to PCI bridges as seen in the figure. Endpoint devices are simply peripheral devices that are either requesters or completers of PCI Express transactions.
  • TI offers 4 different types of PCI Express device families, including physical layer, or PHY, devices, bridges, switches and endpoints. PCI Express PHY devices are necessary when FPGAs in a system design do not have this functionality integrated. Connecting a PHY device to a FPGA allows the FPGA to then be part of the PCI Express fabric, and in turn, can take advantage of the higher speed and bandwidth capability of the architecture. PCI Express switch devices are used to extend the PCI Express fabric allowing for more devices, or endpoints, to be connected. PCI Express switch devices are used to extend the PCI Express fabric allowing for more devices, or endpoints, to be connected. Endpoints are necessary to add peripheral capabilities to a PCI Express fabric. There are many examples of peripherals including 1394 controllers, Ethernet, USB and graphics devices that can take advantage of the high bandwidth capabilities of PCI Express.
  • The Texas Instruments XIO2200A is a single-function PCI Express to PCI local bus translation bridge where the PCI bus interface is internally connected to a 1394a-2000 open host controller link-layer controller with a two-port 1394a PHY. The device is capable of transferring data between the PCI Express bus and the 1394 bus at 100, 200 and 400 Mbps. The XIO2200A provides two 1394 ports that have separate cable bias (TPBIAS). The device also supports IEEE standards such as 1394a-2000 power-down features for battery-operated applications and arbitration enhancements.
  • The PCI-Express to PCI translation bridge is proven compatibility and interoperability with leading PCIe chipsets and 1394a devices. The Software-programmable and hardware-autonomous power-management features for low-power applications such as ExpressCard. An external 2-wire serial EEPROM interface is provided to load the global unique ID for the 1394 fabric. The XIO2200A is available in either a 176-ball GGW/ZGW MicroStar TM BGA or a 175−ball ZHH MicroStar TM BGA package.
  • The figure shows a simplified block diagram of the basic architecture of the PCI-Express to PCI Bridge with 1394a OHCI and two-port PHY. The top of the diagram is the PCI Express interface and the 1394a OHCI with two-port PHY is located at the bottom of the diagram.
  • The figure represents a typical implementation of the XIO2200A PCI Express to PCI Translation Bridge with 1394a OHCI and two-port PHY. This solution provides robust PCI Express link to 1394a cable port protocol conversion in a single semiconductor package. The XIO2200A operates only with the PCI Express link as the primary interface and the 1394a cable ports as the secondary interface. The XIO2200A requires either a differential, 100-MHz common clock reference or a single-ended, 125-MHz clock reference. The EEPROM can be used to set various configuration registers, but is not necessary if those registers are settable via system software/BIOS. Up to eight general-purpose inputs and outputs (GPIO) exist for further system customization. The 1394a core requires the standard 24.576-MHz crystal oscillator as described in the 1394a specification.
  • The XIO2200A has an x1 PCI Express interface that is fully compliant to the PCI Express Base Specification , Revision 1.0a.The XIO2200A TX and RX terminals attach to the upstream PCI Express device over a 2.5Gbps high-speed differential transmit and receive PCI Express x1 Link. The XIO2200A requires an external reference clock for the PCI-Express interface. The XIO2200A is designed to meet all stated specifications when the reference clock input is within all PCI Express operating parameters. This includes both standard clock oscillator sources or spread spectrum clock oscillator sources. The XIO2200A PCI Express Reset terminal (J17) connects to the upstream PCI Express device’s PERST output. The bridge also supports the PCI Express sideband WAKE feature.
  • The XIO2200A has two 1394a cable ports that can operate at 100, 200, or 400 Mbps. These ports are compliant with the IEEE Std 1394a−2000 , Amendment 1. Here describes implementation considerations for the XIO2200A’s secondary 1394a cable ports. The figure illustrates the connection of the XIO2200A to a 1394a cable connector. For any unused 1394 port, the TPB+ and TPB− terminals can be tied together and then pulled to ground through a 1KΩ resistor; the TPA+ and TPA− terminals of an unused port can be left unconnected.
  • There are eight general-purpose input/output (GPIO) terminals in the XIO2200A. All eight GPIO terminals are 3.3-V tolerant. Three of the GPIO terminals are shared with other miscellaneous functions. The remaining five terminals are always general-purpose inputs or outputs. All eight GPIO terminals are individually configurable as either inputs or outputs by writing the corresponding bit in the GPIO control register at offset B4h. A GPIO data register at offset B6h exists to either read the logic state of each GPIO input or to set the logic state of each GPIO output. The power-up default state for the GPIO control register is input mode.
  • In summary, PCI Express is the latest in high-speed, serial technology allowing for flexible connection options while utilizing less pins than traditional PCI. With improvements in RAS and QoS, PCI Express will be used for years to come. PCI Express Endpoint devices are necessary to add peripheral capabilities to a PCI Express fabric. There are many examples of peripherals including 1394 controllers, Ethernet, USB and graphics devices that can take advantage of the high bandwidth capabilities of PCI Express. The XIO2200A is 1394-based endpoint devices as a PCI Express to PCI local bus translation bridge to provide full PCI Express and 1394a functionality and performance.
  • Thank you for taking the time to view this presentation on “ XIO2200A PCI Express to 1394a Chip” . If you would like to learn more or go on to purchase some of these devices, you may either click on the part list link, or simply call our sales hotline. For more technical information you may either visit the Texas Instruments site, or if you would prefer to speak to someone live, please call our hotline number, or even use our ‘live chat’ online facility.
  • XIO2200A PCI Express to 1394a Chip

    1. 1. XIO2200A PCI Express to 1394a Chip <ul><li>Source: T EXAS I NSTRUMENTS </li></ul>
    2. 2. Introduction <ul><li>Purpose </li></ul><ul><ul><li>This training module will go over the basics of PCI Express, and introduce XIO2200A 1394-based endpoint device. </li></ul></ul><ul><li>Outline </li></ul><ul><ul><li>PCI Express Overview </li></ul></ul><ul><ul><li>Types of PCI Express devices </li></ul></ul><ul><ul><li>XIO2200A device introduction </li></ul></ul><ul><ul><li>Summary </li></ul></ul><ul><li>Content </li></ul><ul><ul><li>17 pages </li></ul></ul>
    3. 3. What is PCI Express? <ul><li>PCI Express is a high speed, low voltage, differential serial communication interconnect between 2 devices </li></ul><ul><ul><li>High speed  2.5Gbps in each direction </li></ul></ul><ul><ul><li>Low voltage  differential signaling environment between 0.8 and 1.2 volts </li></ul></ul><ul><li>PCI Express nearly doubles the theoretical bandwidth of PCI by using approximately 1/10 th the number of pins </li></ul>
    4. 4. Differences between PCI and PCI Express PCI Express PCI <ul><li>High-speed serial bus </li></ul><ul><li>Dual uni-directional data transmission </li></ul><ul><li>Point-to-point architecture </li></ul><ul><li>Supports isochronous data transfers </li></ul><ul><li>Designed for scalability </li></ul><ul><li>Parallel bus </li></ul><ul><li>Shared bi-directional data transmission </li></ul><ul><li>Shared-bus architecture </li></ul><ul><li>No isochronous support </li></ul>
    5. 5. PCI Express Terminology PCI Express Device A PCI Express Device B Link Lane Signal Wire
    6. 6. PCI Express Features <ul><li>Point-to-point connection </li></ul><ul><li>Serial bus requires fewer pins than parallel bus </li></ul><ul><li>Scaleable (lane aggregation) </li></ul><ul><li>Packet based transaction protocol </li></ul><ul><li>Same memory, IO and configuration address space as PCI </li></ul><ul><ul><li>Similar transaction types as PCI with additional features </li></ul></ul><ul><li>Improved data integrity and error handling </li></ul><ul><ul><li>RAS capable (Reliable, Available, Serviceable) </li></ul></ul><ul><ul><li>Data integrity available at link level and end-to-end </li></ul></ul>
    7. 7. PCI Express Topology * Borrowed from literature at PCI-SIG Developer’s Conference
    8. 8. Types of PCI Express Devices <ul><li>Physical Layer (PHY) Devices </li></ul><ul><ul><li>Used to interface the PCI Express Media Access Layer (MAC) to a x1 PCI Express serial link </li></ul></ul><ul><li>Bridges </li></ul><ul><ul><li>Used to bridge between PCI Express and a PCI bus </li></ul></ul><ul><ul><ul><li>Allows for older generation PCI devices to still be used in conjunction with PCI Express fabric </li></ul></ul></ul><ul><li>Switches </li></ul><ul><ul><li>Used to extend the PCI Express fabric allowing more devices to be connected </li></ul></ul><ul><ul><ul><li>Can be thought of as consisting of two or more logical PCI-to-PCI bridges, each bridge associated with a switch port </li></ul></ul></ul><ul><li>Endpoints </li></ul><ul><ul><li>Used to add peripheral capabilities to a PCI Express fabric </li></ul></ul><ul><ul><ul><li>Examples include 1394 controllers, Ethernet, USB or graphics devices </li></ul></ul></ul><ul><ul><ul><li>PCI Express endpoint devices can support up to 8 functions per endpoint, allowing for multi-function solutions </li></ul></ul></ul>
    9. 9. XIO2200A PCIe Endpoints <ul><li>Full x1 PCI Express throughput </li></ul><ul><li>Fully compliant with </li></ul><ul><ul><li>PCI Express to PCI/PCI-X Bridge Specification, Revision 1.0 </li></ul></ul><ul><ul><li>PCI Express Base Specification, Revision 1.0a </li></ul></ul><ul><ul><li>IEEE standard 1394-1995 for a high-performance serial bus and IEEE standard 1394a-2000 </li></ul></ul><ul><ul><li>1394 Open Host Controller Interface Specification 1.1 </li></ul></ul><ul><li>Full IEEE standard 1394a-2000 support includes: connection debounce, arbitrated short reset and multi-speed </li></ul><ul><li>Concatenation, arbitration acceleration, fly-by concatenation and port disable/suspend/resume </li></ul><ul><li>Two IEEE standard 1394a-2000 fully compliant cable ports at 100, 200 and 400 Mbps </li></ul><ul><li>Cable ports monitor line conditions for active connection to remote nodes </li></ul><ul><li>Cable power presence monitoring </li></ul><ul><li>EEPROM configuration support to load the global unique ID for the 1394 fabric </li></ul>
    10. 10. Key Benefits <ul><li>Proven compatibility and interoperability with leading PCIe chipsets and 1394a devices </li></ul><ul><li>One-chip solution for 1394a ExpressCards </li></ul><ul><li>Software-programmable and hardware-autonomous power-management features for low-power applications such as ExpressCard </li></ul><ul><li>Compact footprint, 12 mm x 12 mm 175-ball MicroStar BGA™ </li></ul><ul><li>EEPROM configuration support to load the global unique ID for the 1394 fabric </li></ul>
    11. 11. Block Diagram
    12. 12. XIO2200A Typical System Implementation
    13. 13. PCI Express Interface <ul><li>2.5 Gbps Transmit and Receive Link </li></ul><ul><ul><li>High-speed differential transmit and receive PCI Express x1 Link </li></ul></ul><ul><li>PCI-Express Reference Clock Inputs </li></ul><ul><ul><li>Either a differential, 100-MHz common clock reference or a single-ended, 125-MHz clock reference </li></ul></ul><ul><ul><li>Meet all PCI Express Specification requirements for frequency tolerance, spread spectrum clocking, and signal electrical characteristics. </li></ul></ul><ul><li>PCI Express Reset </li></ul><ul><ul><li>The XIO2200A PCI Express Reset (PERST) terminal (J17) connects to the upstream PCI Express device’s PERST output. </li></ul></ul><ul><li>PCI Express Wake </li></ul><ul><ul><li>WAKE is an open-drain output from the XIO2200A </li></ul></ul><ul><ul><li>WAKE is driven low to re-activate the PCI Express link hierarchy’s main power rails and reference clocks. </li></ul></ul>
    14. 14. 1394a Port Interface <ul><li>The cable not active (CNA) terminal (U09) is an output that reflects the state of the incoming 1394a cable port bias voltage. </li></ul><ul><li>The cable power status (CPS) terminal (T10) is an input that drives an internal comparator for the purpose of detecting the presence of 1394a cable power. </li></ul><ul><li>PC2 (R09), PC1 (T09), and PC0 (U10) are the power class programming inputs. </li></ul>
    15. 15. GPIO Terminals <ul><li>GPIO0, GPIO1, GPIO3, GPIO6, and GPIO7: These terminals always operate as GPIO bits. </li></ul><ul><li>GPIO4//SCL and GPIO5//SDA share the SCL and SDA signals for the external EEPROM. </li></ul><ul><li>GPIO2 must be a logic one at the de-assertion of PERST to enable PCI Express 1.0a compatibility mode. </li></ul>
    16. 16. Summary <ul><li>PCI Express allows for: </li></ul><ul><ul><li>Higher, scalable bandwidth over PCI using less pins </li></ul></ul><ul><ul><li>Point-to-point connection of devices, systems, etc. </li></ul></ul><ul><ul><li>Stability, scalability and extensibility </li></ul></ul><ul><li>PCI Express Endpoint devices used to add peripheral capabilities to a PCI Express fabric. </li></ul><ul><li>XIO2200A is 1394-based endpoint device. </li></ul><ul><ul><li>PCI Express to PCI local bus translation bridge </li></ul></ul><ul><ul><li>provides full PCI Express and 1394a functionality and performance. </li></ul></ul>
    17. 17. Additional Resource <ul><li>For ordering the XIO2200A, please click the part list or </li></ul><ul><li>Call our sales hotline </li></ul><ul><li>For additional inquires contact our technical service hotline </li></ul><ul><li>For more product information go to </li></ul><ul><ul><li>http://focus.ti.com/docs/prod/folders/print/xio2200a.html </li></ul></ul>

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