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- 1. Very Low-Jitter Encoded Clocking for High Speed ADCs Using the ADF4002 PLL <ul><li>Source: ANALOG DEVICES </li></ul>
- 2. Introduction <ul><li>Purpose </li></ul><ul><ul><li>This training module discusses the design example - using the ADF4002 frequency synthesizer to generate a very low-jitter clock to control sampling on the AD9215 ADC. </li></ul></ul><ul><li>Outline </li></ul><ul><ul><li>PLL basics </li></ul></ul><ul><ul><li>Phase noise in PLL </li></ul></ul><ul><ul><li>Overview of the ADF4002 Frequency Synthesizer </li></ul></ul><ul><ul><li>Using the ADF4002 as a sampling clock for high speed ADC </li></ul></ul><ul><li>Content </li></ul><ul><ul><li>14 pages </li></ul></ul>
- 3. Phase Locked Loop (PLL) Basics <ul><li>In a PLL, the error signal from the phase comparator is the difference between the input frequency or phase and that of the signal feed back. </li></ul><ul><li>The system will force the frequency or phase error signal to zero in the steady state. </li></ul><ul><ul><li>The phase detector and charge pump together form the error detector block . </li></ul></ul>F O = N x F REF
- 4. Phase Noise in PLL <ul><li>S REF is the noise of the reference input to the phase detector. </li></ul><ul><li>S N is the noise due to the feedback divider appearing at the frequency input to the phase detector. </li></ul><ul><li>S CP is the noise due to the phase detector. </li></ul><ul><li>S VCO is the phase noise of the VCO. </li></ul>
- 5. Optimizing PLL Design for Phase Noise <ul><li>Use low N-value </li></ul><ul><ul><li>Since phase noise is multiplied up from the PFD at a rate of 20 log N , reducing N by a factor of 2 will improve system phase noise by 3 dB. </li></ul></ul><ul><li>Choose a higher frequency synthesizer is required </li></ul><ul><li>Use the lowest Rset resistor specified for operation </li></ul><ul><ul><li>Reducing the Rset increases the charge-pump current, which reduces phase noise. </li></ul></ul>
- 6. Why Low-jitter Clocks for High Speed ADC? <ul><li>Aperture jitter is a key ADC concern when performing IF sampling. </li></ul><ul><ul><li>It can increase system noise. </li></ul></ul><ul><ul><li>It can contribute to the uncertainty in the actual phase of the sampled signal itself giving rise to increases in error vector magnitude. </li></ul></ul><ul><ul><li>It can heighten intersymbol interference (ISI). </li></ul></ul><ul><li>ADC sampling process is a multiplication of the sampling clock and the analog input signal. </li></ul><ul><ul><li>This is multiplication in the time domain, which is equivalent to convolution in the frequency domain. </li></ul></ul>
- 7. The ADF4002 Frequency Synthesizer <ul><li>400 MHz bandwidth </li></ul><ul><li>Programmable charge pump currents </li></ul><ul><li>3-wire serial interface </li></ul><ul><li>Analog and digital lock detect </li></ul><ul><li>104 MHz phase detector </li></ul><ul><li>Hardware and software power-down mode </li></ul><ul><li>Applications </li></ul><ul><ul><li>Clock conditioning </li></ul></ul><ul><ul><li>Clock generation </li></ul></ul><ul><ul><li>IF LO generation </li></ul></ul>
- 8. Phase Frequency Detector (PFD) of the ADF4002 <ul><li>The PFD takes inputs from the R counter and N counter and produces an output proportional to the phase and frequency difference between them. </li></ul>
- 9. PLL Counters <ul><li>N Counter </li></ul><ul><ul><li>The N counter allows a wide ranging division ratio in the PLL feedback counter. </li></ul></ul><ul><ul><li>N Counter is 13-bit. </li></ul></ul><ul><ul><li>Division ratios from 1 to 8191 are allowed. </li></ul></ul><ul><li>R Counter </li></ul><ul><ul><li>The 14-bit R counter allows the input reference frequency to be divided down to produce the reference clock to the phase frequency detector (PFD). </li></ul></ul><ul><ul><li>Division ratios from 1 to 16,383 are allowed. </li></ul></ul>The output frequency of external voltage controlled oscillator (VCO)
- 10. Digital Lock Detect <ul><li>Digital lock detect outputs either a CMOS logic high, indicating a locked PLL state, or a logic low, indicating an unlocked state. </li></ul><ul><li>It works by measuring the phase error at the PFD inputs and using a window of 15 ns phase error to decide the lock status of the PLL. </li></ul>
- 11. The ADF4002 PLL Configuration
- 12. The ADF4002 as High Speed ADC Clock Pin 2 Loop Filter Verified Circuits are designed for ease of use and proven to work by ADI.
- 13. SPI Interface <ul><li>The ADF4002 has a simple SPI-compatible serial interface for writing to the device. </li></ul><ul><li>The maximum allowable serial clock rate is 20 MHz. </li></ul>Control the data transfer
- 14. Additional Resource <ul><li>For ordering the ADF4002 and selected parts, please click the part list or </li></ul><ul><li>Call our sales hotline </li></ul><ul><li>For additional inquires contact our technical service hotline </li></ul><ul><li>For more product information go to </li></ul><ul><ul><li>http://www.analog.com/en/content/CU_verified_circuits_CN0003/fca.html </li></ul></ul>

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