Two-Phase Interleaved CCM PFC Controller

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To introduce the UCC28070 two-phase interleaved CCM PFC Controller and its basic operation

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  • Welcome to the training module on Texas Instrument’s Two-Phase Interleaved CCM PFC Controller. This training module introduces the UCC28070 two-phase interleaved CCM PFC Controller and its basic operations.
  • Power factor correction, shapes the input current of off-line power supplies to maximize the real power available from the mains. Simply put, it is the ratio of real power to apparent power. In the past, passive PFC solutions were used in high power applications to fully utilize the line power. These solutions required bulky 60Hz Iron core inductors. Nowadays, an active PFC is used in place of the passive PFC solutions. This topology uses boost regulators and average current-mode control techniques for current-shaping. In high power applications the input filter and PFC boost regulators are much smaller than the older passive solutions.
  • In PFC pre-regulators, the most popular topology used is a boost converter. This is because boost converters can have continuous input-current that can be manipulated with average current-mode control techniques to force the input-current to track changes in line voltage. This figure shows the functional diagram of a two phase interleaved boost converter. The interleaved boost converter is simply two boost converters in parallel, operating at 180° out of phase. The input-current is the sum of the two inductor currents IL1 and IL2. Because the inductor’s ripple currents are out of phase, they tend to cancel each other and reduce the input ripple current caused by the boost inductors. Interleaving presents the power supply designer with some design options. Input and Output ripple current-cancellation can reduce the output capacitor RMS current, reduce the EMI filter size and also boost inductor size depending on the design requirements.
  • The UCC28070 is a single-chip interleaved power factor correction control circuit. This IC simplifies power design, increases system reliability, achieves greater power factor and high efficiency ratings in applications ranging from multi-kilowatt communication, server & industrial systems, to digital TVs & PCs. The UCC28070 integrates two pulse-width modulators operating at 180 º out of phase. An improved multiplier design, provides a shared current reference to two independent current amplifiers to ensure matched average current-mode control in both PWM outputs while maintaining a stable, low-distortion sinusoidal input-line current. The UCC28070 also contains a current synthesizer and quantized voltage feed-forward to promote performance enhancements in power factor, efficiency and transient response.
  • Ripple current reduction due to interleaving is often referred to as “ripple cancellation”, but strictly speaking, the peak-to-peak ripple is completely cancelled only at 50% duty-cycle in a 2-phase system. At duty-cycles other than 50%, ripple reduction occurs in the form of partial cancellation due to the super-position of the individual phase currents. Nevertheless, compared to the ripple currents of an equivalent single-phase PFC pre-regulator, those of a 2-phase interleaved design are extra-ordinarily smaller.
  • Frequency dithering refers to modulating the switching frequency to achieve a reduction in conducted-EMI noise beyond the capability of the line filter alone. The UCC28070 implements a triangular modulation method which results in equal time spent at every point along the switching frequency range. This total range from minimum to maximum frequency is defined as the dither magnitude, and is centered around the nominal switching frequency f PWM set with R RT . The rate at which f PWM traverses from one extreme to the other and back again is defined as the dither rate.
  • One of the most prominent features in the UCC28070 design, is the current synthesizer circuitry that synchronously monitors the instantaneous inductor current through a combination of on-time sampling and off-time down-slope emulation. During the on-time of the GDA and GDB outputs, the inductor current is recorded at the CSA and CSB pins respectively via the current transformer network in each output phase. Meanwhile, the continuous monitoring of the input and output voltage via the VINAC and VSENSE pins permits the UCC28070 to internally recreate the inductor current’s down-slope during each output’s respective off-time.
  • The UCC28070 has been designed with a programmable cycle-by-cycle peak current-limit dedicated to disabling either GDA or GDB output whenever the corresponding current-sense input (i.e. CSA or CSB) rises above the voltage, established on the PKLMT pin. Once an output has been disabled via the detection of peak current- limit, the output remains disabled until the next clock cycle initiates a new PWM period. A resistor-divider network from VREF to GND can easily program the peak current-limit voltage on PKLMT, provided the total current out of VREF is less than 2 mA to avoid drooping of the 6-V VREF voltage.
  • The multiplier of the UCC28070 generates a reference current which represents the desired wave shape and proportional amplitude of the AC input current. This current is converted to a reference voltage signal by the R IMO resistor, which is scaled in value to match the voltage of the current-sense signals. The instantaneous multiplier current is dependent upon the rectified, scaled input voltage V VINAC and the voltage-error amplifier output V VAO . A major innovation in the UCC28070 multiplier architecture, is the internal quantized VRMS feed-forward (Q VFF ) circuitry, which eliminates the requirement for external filtering of the VINAC signal and the subsequent slow response to transient line variations. The performance of the multiplier has high linearity and accuracy over most of the input ranges.
  • External clock synchronization is able to facilitate using more than 2 phases for interleaving. Multiple UCC28070s can easily be paralleled to add an even number of additional phases for higher-power applications. With appropriate phase-shifting of the synchronization signals, even more input and output ripple current cancellation can be obtained. For 4-, 6-, or any 2 x n-phases (where n = the number of UCC28070 controllers), each controller should receive a SYNC signal which is 360/n degrees out of phase with each other. For a 4-phase application interleaving with two controllers, SYNC1 should be 180° out of phase with SYNC2 for optimal ripple cancellation. The figure shows the paralleling of two controllers for a 4-phase 90°-interleaved PFC system.
  • The UCC28070 incorporates two identical and independent trans-conductance-type current-error amplifiers (i.e. one for each phase) with which to control the shaping of the PFC input current waveform. The current-error amplifier (CA) forms the heart of the embedded current control loop of the boost PFC pre-regulator, and is compensated for loop stability. The output of the current-error-amplifier for phase-A is CAOA, and that for phase-B is CAOB. Since the design considerations are the same for both, they are collectively referred to as CAOx, where the "x" may be "A" or "B“, shown in the figure.
  • The outer voltage control loop of the dual-phase PFC controller functions the same way as with a single-phase controller. The bandwidth of the voltage-loop must be considerably lower than twice-the line ripple frequency (f 2LF ) on the output capacitor, to avoid distortion-causing correction to the output voltage. The output of the voltage-error amplifier (VA) is an input to the multiplier, to adjust the input current amplitude relative to the required output power. Variations on VAO within the bandwidth of the current loops will influence the wave-shape of the input current. Any response of the voltage-loop to this ripple will have a greater distorting effect on high-line current than on low-line current. Therefore, the allowable percentage of 3rd-harmonic distortion on the input current contributed by VAO should be determined using high-line conditions.
  • The UCC28070 contains a variety of protection features including output over-voltage detection, zero-power detection and thermal shutdown. It implements over-voltage-protection through the continuous monitoring of the VSENSE voltage. When V VSENSE rises above 106 percent (%) of regulation or 3.18 V, the GDx outputs are immediately disabled to prevent the output voltage from reaching excessive levels. Meanwhile the CAOx outputs are pulled low in order to ensure a controlled recovery starting from 0 percent duty-cycle after an over-voltage-protection fault is released. In order to prevent undesired performance under no-load and near-no-load conditions, the UCC28070 zero-power detection comparator is designed to disable both GDA and GDB output in the event the VAO voltage falls below 0.75 V. The UCC28070 has an internal temperature-sensing comparator that shuts down nearly all of the internal circuitry, and disables the GDA and GDB outputs, if the die temperature rises above 160°C.
  • The UCC28070 Interleaving PFC pre-regulator has many benefits. It can reduce EMI and boost inductor magnetic volume. The amount of reduction varies and depends on the design requirements and design tradeoffs. The designer may choose to reduce either the boost inductor magnetic volume or cut back the switching frequency to reduce the size of the EMI filter. In some cases, just adding an additional phase will reduce the size of the EMI filter. Interleaving also reduces the RMS current in the boost capacitor thus greatly reducing electrical over-stress on the capacitor. However, the complexity and cost of the design will increase with each additional phase.
  • Thank you for taking the time to view this presentation on “ Two-Phase Interleaved CCM PFC Controller” . If you would like to learn more or go on to purchase some of these devices, you may either click on the part list link, or simply call our sales hotline. For more technical information you may either visit the Texas Instruments site, or if you would prefer to speak to someone live, please call our hotline number, or even use our ‘live chat’ online facility.
  • Two-Phase Interleaved CCM PFC Controller

    1. 1. Two-Phase Interleaved CCM PFC Controller <ul><li>Source: T EXAS I NSTURMENTS </li></ul>
    2. 2. Introduction <ul><li>Purpose </li></ul><ul><ul><li>To introduce the UCC28070 two-phase interleaved CCM PFC Controller and its basic operation. </li></ul></ul><ul><li>Outline </li></ul><ul><ul><li>PFC basics </li></ul></ul><ul><ul><li>Overview of the UCC28070 </li></ul></ul><ul><ul><li>Basic operations of the UCC28070 </li></ul></ul><ul><ul><li>Summary </li></ul></ul><ul><li>Content </li></ul><ul><ul><li>16 pages </li></ul></ul>
    3. 3. Power Factor Correction (PFC) Basics <ul><li>PFC is simply defied as the ratio of real power to apparent power </li></ul><ul><li>Passive PFC – requires bulky 60-Hz iron core inductors </li></ul><ul><li>Active PFC – smaller than passive PFC </li></ul>
    4. 4. Why Interleave PFC? <ul><li>Input and output ripple current cancellation </li></ul><ul><ul><li>Reduces boost inductor volume </li></ul></ul><ul><ul><li>Reduces output capacitor RMS current </li></ul></ul><ul><ul><li>Reduces the EMI filter size </li></ul></ul>
    5. 5. UCC28070 Two-Phase Interleave PFC <ul><li>Key Features </li></ul><ul><ul><li>Interleaved average current mode PWM control </li></ul></ul><ul><ul><li>Advanced current synthesizer for superior efficiency, accurate current sensing and high power factor </li></ul></ul><ul><ul><li>Highly linear multiplier output with internal voltage feed-forward correction for near unity power factor </li></ul></ul><ul><ul><li>Programmable switching frequency (30 kHz to 300 kHz) </li></ul></ul><ul><ul><li>Selectable frequency dithering for reduced EMI </li></ul></ul><ul><ul><li>Phase management for high-efficiency light-load operation </li></ul></ul><ul><li>Key Applications </li></ul><ul><ul><li>High end servers </li></ul></ul><ul><ul><li>Base stations </li></ul></ul><ul><ul><li>Data centers </li></ul></ul><ul><ul><li>HVAC </li></ul></ul><ul><ul><li>White goods </li></ul></ul><ul><ul><li>Motor control </li></ul></ul>
    6. 6. Ripple Current Reduction <ul><li>Delivers output and input ripple cancellation </li></ul><ul><ul><li>Reduce design size and cost </li></ul></ul><ul><ul><li>Increase power capability of already established design size </li></ul></ul>
    7. 7. Frequency Dithering <ul><li>The desired dither magnitude is set by a resistor from the RDM pin to GND. </li></ul><ul><li>Once the value of RRDM is determined, the desired dither rate may be set by a capacitor from the CDR pin to GND. </li></ul><ul><li>Frequency dithering may be fully disabled by forcing the CDR pin > 5 V or by connecting it to VREF (6 V) and connecting the RDM pin directly to GND. </li></ul>
    8. 8. Current Synthesizer <ul><li>The current synthesizer circuitry synchronously monitors the instantaneous inductor current. </li></ul><ul><li>Setting up the current synthesizer is accomplished by correctly selecting R SYN . </li></ul>
    9. 9. Peak Current Limit <ul><li>A programmable cycle-by-cycle peak current limit dedicated to disabling either GDA or GDB output whenever the corresponding current-sense input rises above the voltage established on the PKLMT pin. </li></ul><ul><li>A resistor-divider network from VREF to GND can program the peak current limit voltage on PKLMT. </li></ul>
    10. 10. Linear Multiplier Linear Multiplier Architecture
    11. 11. Multi-phase Operation Synchronized clock
    12. 12. Current Loop Compensation <ul><li>The current control loop comprises </li></ul><ul><ul><li>Boost power plant stage </li></ul></ul><ul><ul><li>Current sensing circuitry </li></ul></ul><ul><ul><li>Wave-shape reference </li></ul></ul><ul><ul><li>Current-error amplifier with compensation components </li></ul></ul>
    13. 13. Voltage Loop Compensation <ul><li>The bandwidth of the voltage-loop must be considerably lower than the twice-line ripple frequency (f 2LF ) on the output capacitor, to avoid distortion-causing correction to the output voltage. </li></ul><ul><li>The output of the voltage-error amplifier adjusts the input current amplitude relative to the required output power. </li></ul>
    14. 14. Other Protection Features <ul><li>Over-Voltage Protection (OVP) </li></ul><ul><ul><li>When V VSENSE rises above 106% of regulation (3.18 V) </li></ul></ul><ul><ul><ul><li>the GDx outputs are immediately disabled </li></ul></ul></ul><ul><ul><ul><li>the CAOx outputs are pulled low </li></ul></ul></ul><ul><li>Zero-Power Detection </li></ul><ul><ul><li>To prevent undesired performance under no-load and near no-load conditions </li></ul></ul><ul><li>Thermal Shutdown </li></ul><ul><ul><li>When the die temperature rises above 160°C </li></ul></ul><ul><ul><ul><li>Internal temperature-sensing comparator shuts down nearly all of the internal circuitry </li></ul></ul></ul><ul><ul><ul><li>The GDA and GDB outputs are disabled </li></ul></ul></ul>
    15. 15. Summary <ul><li>Input and output ripple current cancellation </li></ul><ul><ul><li>Reduce boost capacitor RMS current </li></ul></ul><ul><ul><li>Attenuates inductor ripple current at the converter’s input </li></ul></ul><ul><li>Can increase power density </li></ul><ul><ul><li>Reduce inductor volume </li></ul></ul><ul><ul><li>Reduce the size of the EMI filter </li></ul></ul><ul><li>Interleaving can improve efficiency and/or allow the designer to use lower power/cheaper components in their designs </li></ul>
    16. 16. Additional Resource <ul><li>For ordering the UCC28070, please click the part list or </li></ul><ul><li>Call our sales hotline </li></ul><ul><li>For additional inquires contact our technical service hotline </li></ul><ul><li>For more product information go to </li></ul><ul><ul><li>http://focus.ti.com/docs/prod/folders/print/ucc28070.html </li></ul></ul>Newark Farnell

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