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TPS720xx: LDO Linear Regulators
TPS720xx: LDO Linear Regulators
TPS720xx: LDO Linear Regulators
TPS720xx: LDO Linear Regulators
TPS720xx: LDO Linear Regulators
TPS720xx: LDO Linear Regulators
TPS720xx: LDO Linear Regulators
TPS720xx: LDO Linear Regulators
TPS720xx: LDO Linear Regulators
TPS720xx: LDO Linear Regulators
TPS720xx: LDO Linear Regulators
TPS720xx: LDO Linear Regulators
TPS720xx: LDO Linear Regulators
TPS720xx: LDO Linear Regulators
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TPS720xx: LDO Linear Regulators

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Technical review of TPS20xx low dropout voltage regulators and detailed discussions of internal operation

Technical review of TPS20xx low dropout voltage regulators and detailed discussions of internal operation

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  • Welcome to the training module on TI LDO Voltage Regulators. This training module provides a technical review of TPS720xx low dropout voltage regulators, and detailed discussions of internal operation.
  • Dropout voltage is the input-to-output differential voltage at which the circuit ceases to regulate against further reductions in input voltage; this point occurs when the input voltage approaches the output voltage. In the linear region, the series pass element acts like a series resistor. LDO operation can be explained using the NMOS series pass element I-V Characteristics. It shows two regions of operation—linear and saturation. In the saturation region, the device becomes a voltage-controlled current source. Voltage regulators usually operate in the saturation region. Figure 2 shows the dropout region in relation to the off and regulation regions. Below V(dropout), the output voltage drops with decreasing input voltage.
  • The regulator circuit can be partitioned into four functional blocks: the reference, the pass element, the sampling resistor, and the error amplifier. Traditionally, the PNP bipolar transistor has been applied to low dropout applications, primarily because it easily enables a low drop out voltage. However, it has a high quiescent current and low efficiency, which are not ideal in applications where maximizing efficiency is a priority. To have a high efficiency LDO regulator, drop out voltage and quiescent current must be minimized. In addition, the voltage difference between input and output must be minimized since the power dissipation of LDO regulators accounts for the efficiency.
  • The TPS720xx family of dual rail, low-dropout linear regulators (LDOs) offers outstanding ac performance (PSRR, load and line transient response), while consuming a very low quiescent current of 38µA. The TPS720xx supports a novel feature in which the output of the LDO regulates under light loads when the IN pin is left floating. The TPS720xx is stable with ceramic capacitors and uses an advanced BICMOS fabrication process that yields a dropout of 110mV at a 350mA output load. The TPS720xx uses a precision voltage reference and feedback loop to achieve overall accuracy of 2% over load, line, process, and temperature extremes.
  • At startup, the error amplifier senses that the output voltage is low and drives the pass element as hard as possible. The TPS720xx employs the NMOS device as the pass element. The NMOS can have a low dropout voltage with a charge pump. The dropout voltage is determined by saturation voltage across the pass element, and the dropout voltage is proportional to the current flowing through the pass element. At light load, the dropout voltage is only a few millivolts. At full load, the typical dropout voltage is 350 mV. The TPS720xx internal current limits help protect the regulator during fault conditions. The undervoltage lock-out circuit on the BIAS pin is to keep the output shut off until the internal circuitry is operation properly. The TPS720xx uses innovative circuitry to achieve ultra-wide bandwidth and high loop gain resulting in extremely high PSRR.
  • Although an input capacitor is not required for stability on the IN pin, it is good analog design practice to connect a 0.1 µ F to 1.0 µ F low equivalent series resistance (ESR) capacitor across the IN pin input supply near the regulator. This capacitor counteracts reactive input sources and improves transient response, noise rejection, and ripple rejection. The BIAS pin does not require an input capacitor because it does not source high currents. However, if source impedance is not sufficiently low, a small 0.1mF bypass capacitor is recommended. To decrease the voltage variation resulting from the load transient, a big value of output capacitor and the low ESR of the capacitor are recommended. The TPS720xx is designed to be stable with standard ceramic capacitors with values of 2.2mF or larger at the output.
  • Power supply rejection ratio (PSRR) is a measure of how well a circuit rejects ripple coming from the input power supply at various frequencies and is very critical in many RF and wireless applications. In an LDO, it is a measure of the output ripple compared to the input ripple over a wide frequency range (10 Hz to 10 MHz is common) and is expressed in decibels (dB). To improve ac performance such as PSRR, output noise, and transient response, it is recommended that the board be designed with separate ground planes for V IN and V OUT , with the ground plane connected only at the GND pin of the device.
  • The TPS720xx family of LDO regulators implement a novel inrush current-limit circuit architecture: the current drawn through the IN pin is limited to a finite value. This I INRUSHLIMIT charges the output to its final voltage. All the current drawn through V IN goes to charge the output capacitance when the load is disconnected. Another consideration is when a load is connected to the output of an LDO. The connected load tries to steer a portion of the current away from V OUT . The TPS720xx inrush current-limit circuit employs a new technique that supplies not only the I INRUSHLIMIT , but also the additional current needed by the load.
  • As with any regulator, increasing the size of the output capacitor reduces over/undershoot magnitude but increases duration of the transient response. The transient response is a function of the output capacitor value (Co), the equivalent series resistance (ESR) of the output capacitor, the buypass capacitor (Cb), and the maximum load-current (Io,max). The application determines how low this value should be. To decrease the voltage variation resulting from the load transient, a big value of output capacitor and the low ESR of the capacitor are recommended.
  • The TPS720xx supports a novel feature in which the output of the LDO regulates under light loads when the IN pin is left floating. Under normal conditions, when the IN pin is connected to a power source, the BIAS pin draws only tens of milliamperes. However, when the IN pin is floating, an innovative circuit is used that allows a mximum current of 500 µ A to be drawn by the load through the BIAS pin, while maintaining the output in regulation. This feature is particularly useful in power-saving applications where a dc/dc converter connected to the IN pin is disabled, but the LDO is required to regulate the output voltage to a light load. The figure shows an application example where a microcontroller is not turned off (to maintain the state of the internal memory), but where the regulated supply (shown as the TPS62xxx) is turned off to reduce power. In this case, the TPS720xx BIAS pin provides sufficient load current to maintain a regulated voltage to the microcontroller.
  • The internal protection circuitry of the TPS720xx has been designed to protect against overload conditions. It was not intended to replace proper heatsinking. Thermal protection disables the output when the junction temperature rises to approximately +160°C, allowing the device to cool. When the junction temperature cools to approximately +140°C, the output circuitry is again enabled. Depending on power dissipation, thermal resistance, and ambient temperature, the thermal protection circuit may cycle on and off This cycling limits the dissipation of the regulator, protecting it from damage as a result of overheating. For reliable operation, junction temperature should be limited to +125°C maximum.
  • Most LDO regulators specify a junction temperature to assure their operations; the maximum junction temperature allowable without damaging the device is also specified. This restriction limits the power dissipation that the regulator can handle in any given application. To ensure that the junction temperature is within acceptable limits, calculate the maximum allowable dissipation, P D(max) , and the actual dissipation, P D , which must be less than or equal to P D(max) .
  • Thank you for taking the time to view this presentation on LDO Voltage Regulators. If you would like to learn more or go on to purchase some of these devices, you may either click on the part list link, or simply call our sales hotline. For more technical information you may either visit the TI site – link shown – or if you would prefer to speak to someone live, please call our hotline number, or even use our ‘live chat’ online facility.
  • Transcript

    • 1. TPS720xx: LDO Linear Regulators
      • Source: T EXAS I NSTRUMENTS
    • 2. Introduction
      • Purpose
        • This training module provides a technical review of TPS20xx low dropout voltage regulators, and detailed discussions of internal operation.
      • Outline
        • Basic low dropout (LDO) regulator technology
        • Overview of TPS20xx LDO regulators
        • Discussion of internal operation
      • Content
        • 14 pages
      • Duration
        • 10 Minutes
    • 3. Dropout Voltage
      • Dropout voltage is the input-to-output differential voltage at which the circuit ceases to regulate against further reductions in input voltage
      Figure 1 Figure 2
    • 4. Linear Regulator
      • Linear Regulator consists of four functional blocks: the reference, the pass element, the sampling resistor, and the error amplifier
      Efficiency of a LDO regulator:
    • 5. TPS720xx Features
      • 350mA High-Performance LDO
      • Low Quiescent Current: 38µA
      • Excellent Load Transient Response: ±15mV for I LOAD = 0mA to 350mA in 1µs
      • Excellent Line Transient Response
      • Low Noise: 48µV RMS (10Hz to 100kHz)
      • 80dB V IN PSRR (10Hz to 10kHz)
      • 70dB V BIAS PSRR (10Hz to 10kHz)
      • Fast Start-Up Time: 140µs
      • Built-In Soft-Start with Monotonic V OUT Rise and Startup Current Limited
      • Over-Current and Thermal Protection
      • Low Dropout: 110mV at I LOAD = 350mA
      • Stable with 2.2µF Output Capacitor
    • 6. Functional Block Diagram
    • 7. Input & Output Capacitor Requirements
      • The Input Capacitor on the IN pin counteracts reactive input sources and improves transient response, noise rejection, and ripple rejection.
      • The Output Capacitor decreases the voltage variation resulting from the load transient.
      Input Capacitor Output Capacitor
    • 8. Power Supply Ripple Rejection Ratio (PSRR)
      • Power supply rejection ratio measures the LDO regulator’s ability to prevent the regulated output voltage fluctuating caused by input voltage variations.
    • 9. Inrush Current Limit
      • Inrush current is a measure of the transient current taken from the supply pin during the initial startup sequence.
      • When not properly limited, the inrush current in LDOs can cause system level failures.
      I INRUSHLIMIT (A) = C OUT ( µ F) (V/ µ s) x 0.0454545 (V/ µ s) + I LOAD (A)
    • 10. Transient Response
      • The transient response is the maximum allowable output voltage variation for a load current step change.
    • 11. Regulation with IN Pin Floating
      • when the IN pin is floating, an innovative circuit is used that allows a mximum current of 500 µ A to be drawn by the load through the BIAS pin, while maintaining the output in regulation.
    • 12. Thermal Protection
      • Any tendency to activate the thermal protection circuit indicates excessive power dissipation or an inadequate heatsink.
      • The thermal protection shuts the regulator off if the junction temperature rises above 160°C.
      • Recovery is automatic when the junction temperature drops approximately to 140°C, where regulator operation resumes.
      • The thermal protection circuit may cycle on and off depending on different conditions.
      • For reliable operation, junction temperature should be limited to +125°C maximum.
      • For good reliability, thermal protection should trigger at least +35°C above the maximum expected ambient condition of the particular application.
    • 13. Power Dissipation
      • Power dissipation depends on input voltage and load conditions.
      • P D = (V IN – V OUT ) × I OUT
      • The maximum power dissipation limit is determined using the following equation
      T Jmax : the maximum allowable junction temperature R θ JA : the thermal resistance junction-to-ambient for the package T A : the ambient temperature
    • 14. Additional Resource
      • For ordering the current shunt monitors, please click the part list or
      • Call our sales hotline
      • For additional inquires contact our technical service hotline
      • For more product information go to
        • http://focus.ti.com/paramsearch/docs/parametricsearch.tsp?family=analog&familyId=400&uiTemplateId=NODE_STRY_PGE_T
      Newark Farnell

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