Timing Generators and ClockCleaner Solutions <ul><li>Source: GENNUM </li></ul>
Introduction <ul><li>Purpose </li></ul><ul><ul><li>To introduce Gennum’s timing generator and clock cleaner technology and...
Why Synchronize? <ul><li>Any video receiver must synchronize its circuitry to the timing information embedded in the input...
Genlock Studio Example House Reference VTR 1 Movie Commercial 1 Commercial 2 TV VTR 2 VTR 3 switch Genlock Circuitry
What is Genlock? <ul><li>Genlock is short for ‘Generator Lock’. </li></ul><ul><li>It refers to the process of synchronizin...
Genlock – Traditional Methods <ul><li>Traditional Genlock circuitry  requires  multiple discrete components  on a board , ...
Analog Video Timing and Studio Sync <ul><li>Usually an analog video signal containing all the standard sync and colour bur...
Synchronous Switching In a perfect world…
Synchronous Switching Skew between two channels
What are GEN Clocks?   <ul><li>The  GEN Clocks TM  family are a group of products that generate the clock and timing signa...
Gennum GEN Clock   Family  <ul><li>Clock Cleaner  –  GS4915 </li></ul><ul><ul><li>27MHz, 74.25MHz,74.175MHz, 148.5Mhz, 148...
GS4911B Key Features  <ul><li>Clock Synthesis </li></ul><ul><ul><li>Pre-programmed to generate 8 video, 13 graphic, and 7 ...
GS4911B Key Features  cont’d   <ul><li>Genlock Capability </li></ul><ul><ul><li>Automatic input format detection for 5 1  ...
GS4911B Output Clock & Timing <ul><li>GS49 11B  delivers 3 types of outputs: </li></ul><ul><ul><li>Video Clock (PCLK) </li...
GS4915 Clock Cleaner <ul><li>Reduces jitter on I/P video clocks, namely; </li></ul><ul><ul><li>HD data rates (148.5MHz, 14...
GS4911B & GS4915 Critical Parameters <ul><li>Ideal complement for GS4911B in any SDI application clean high frequency jitt...
Additional Resource <ul><li>For ordering GEN Clock, please click the part list or </li></ul><ul><li>Call our sales hotline...
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Timing Generators and ClockCleaner Solutions

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To introduce Gennum’s timing generator and clock cleaner technology and its product offerings

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  • This is an introduction to Gennum Timing Generators and Clock Cleaner Solutions
  • Welcome to the training module on Timing Generators and ClockCleaner Solutions. This training module introduces Gennum’s timing generators and clock cleaner technology and its product offerings
  • Video timing is one of those things that most people never notice — until it goes wrong. Timing is most important in a broadcast studio, where synchronization is critical to the capture, processing, and distribution of video signals. Since any video receiver must synchronize its circuitry to the timing reference signals embedded in the input video signal to properly display — or even just manipulate — the image it carries, trouble can arise when the input to the receiver is suddenly changed. If the timing reference for the new signal is different than that of the old, the receiver circuitry must re-synchronize. This transition time can take up to several milliseconds, enough time to cause the image to visibly tear, skip, jump, or otherwise be disrupted. The most common example of this is the temporary breakup of the image on your TV when changing channels.
  • The process of combining video signals originating from different local sources requires perfect synchronism and relative timing of all the signals present at the input of a production switcher. External, incoming video feeds are non-synchronous. They can be recorded without difficulty as the VTR locks onto the incoming video signal. Mixing the incoming feeds with the locally generated signals requires that the external and internal video signal sources be synchronous and meet the timing requirements. All local signals must be locked to the incoming external feed. To achieve this the master sync generator is locked to the external feed. Alternately, various operational configurations, consisting of a studio, several cameras, VTRs and production switchers, are genlocked to specific external sources.
  • In order to ensure that there are no mid-program disruptions, television studios make sure that all of their video signals are exactly in sync with one another. This synchronization is referred to as &apos;generator lock&apos;, or &apos;GENLOCK&apos;, since it requires locking the circuitry of a given piece of equipment to the timing reference signal produced by a sync pulse generator (SPG), the box that is used to create the studio sync. Genlock is the process of synchronizing multiple pieces of video equipment so when multiple pieces of equipment in a system are synchronized they are said to be genlocked. Genlocking is a critical function of any broadcast video system.
  • Traditional genlock circuits will generate a pixel clock, a horizontal sync pulse, a vertical sync pulse, a frame/field reference pulse, and in analog systems, a colour burst frequency, and will lock them to the corresponding signals extracted from the reference signal by a sync separator. These circuits require multiple discrete components on a board. To design traditional genlock circuitry, the user needs to determine the timing relationship between the reference and the desired output format, and use the appropriate VCXO(s), flip-flops, filter, and FPGA to create the clock and timing signals. The traditional methods require unique circuitry for each video frequency. Depending on video standards, this circuitry may be hard to design. In addition, this solution may take up a lot of board space.
  • In the case of a standard analog television signal, the composite signal contains regularly spaced horizontal sync pulses to indicate the beginning of each line, a series of vertical sync pulses to indicate the end of an image (frame) and the beginning of the next, and a colour sub-carrier used to encode colour information for the image. The analog receiver will extract these timing signals and synchronize its internal circuitry to them so that the received image can be properly displayed. The studio sync is produced by a sync pulse generator (SPG) and distributed to all the video equipment in the studio.
  • For digital video signals, such as the Serial Digital Interface (SDI) signals commonly used to transport video within a broadcast studio, the timing information is encoded as a uniquely identifiable digital word and transmitted at regular intervals in the bit stream. In the SDI interface, this word is called the TRS (timing reference signal). There are two kinds of TRS words, the EAV (end of active video) and SAV (start of active video), which, by both their location in the bit stream and their actual value, relate the same kind of horizontal and vertical timing information needed to distinguish one line from another, and one frame from the next. This figure shows the A and B channel are synchronized to each other, the switch won’t cause a disruption in the timing.
  • Here is another example for two unsynchronized channels. For example, during broadcast switch is made from one camera to another during a newscast. These two cameras are not synchronized to each other. It results a disruption in the timing, and therefore, a disruption of the image broadcast to you.
  • The GEN Clock family are a group of products that generate the clock and timing signals required for most video and graphics systems. This family can generate multiple clocks, including 3 video clocks (2 single ended and one differential), 3 audio clocks, and 8 configurable timing signal clocks. By supplying the clock generator with HSync, VSync and Fsync, the chips will determine if it meets one of 36 video or 16 graphics standards and will report which standard. Members of the GS49xx family are GS4900B, GS4901B, GS4910B and GS4911B. The GS4911B is an SD/HD/Graphics Video and Audio Timing Generator with Genlock incorporating all the features of the other devices.
  • This table shows the different clock signals generated by different members. The generator is referenced to an internal crystal oscillator and is responsible for generating the PCLK output signals. The maximum PCLK value is listed in the table. The GS4915 provides a low jitter clock output when fed with an HD or SD video clock input. Other input clock frequencies between 12MHz and 165MHz can be automatically passed through to the GS4915 outputs. An internal 2:1 mux allows the user to select between a differential or single-ended (LVCMOS) input clock. If the input clock frequency is 74.25 or 74.25/1.001MHz, the GS4915 can double the output, providing a low jitter 148.5 or 148.5/1.001MHz output clock which can be used for HD-SDI and 3Gb/s-SDI applications.
  • The GS4911B is a highly flexible, digitally controlled clock synthesis circuit and timing generator with genlock capability. The user may select to output one of 8 different video sample clock rates or 13 different graphic display clock rates. In addition, the GS4911B provides three audio sample clock outputs. The chosen clock frequency may be further internally divided, and is available on two video clock outputs and one LVDS video clock output pair. The video clocks may also be individually phase delayed with respect to the timing outputs for clock skew control. The user may also program any clock frequency between 13.5MHz and 165MHz. The GS4911B can generate up to 8 different timing signals at a time.
  • When the device is in Genlock mode and the input reference is removed, the GS4911B will enter Freeze mode. In this mode, the output clock and timing signals will maintain their previously genlocked phase and frequency to within +/- 2ppm. The device will first attempt to automatically genlock the output to the input reference. If the output format selected is such that it is not commonly genlocked to the input reference, the GS4911B will not automatically lock. In this case, the user may program designated registers to manually allow locking to occur. The GS4911B supports cross-locking, allowing the outputs to be genlocked to an incoming reference that is different from the output video standard selecte The GS4911B is Pb-free, and the encapsulation compound does not contain halogenated flame retardant (RoHS Compliant).
  • The internal PCLK signal generated by the clock synthesis circuit is used to produce horizontal, vertical, and frame based timing output signals. In addition to the device’s pre-programmed clock frequencies, the user may generate a custom audio or video clock by programming designated registers in the host interface. In addition to the devices’s pre-programmed output timing signals, the user may also build their own custom timing signals. The GS4911B also provides audio sample clock outputs that can produce audio clocks up to 512fs with fs ranging from 9.7kHz to 96kHz. Clock &amp; timing generation requires only one 27MHz external crystal reference.
  • The GS4915 provides a low jitter clock output when fed with an HD or SD video clock input. The typical output jitter is as low as 20ps. Other input clock frequencies between 12MHz and 165MHz can be automatically passed through to the GS4915 outputs. In bypass mode, the GS4915 will automatically or manually bypass its cleaning stage and pass the input clock signal directly to the output whenever the device is unlocked. Clock input may be either LVDS or CMOS levels and fed by the GS4911B clock generator. The GS4915 contains two separate input buffers to accept either a differential or single-ended input clock. The GS4915 is designed to operate with the GO1555 VCO as part of its phase-locked loop.
  • The GS4915 Clock Cleaner complements Gennum&apos;s GS4911B Clock and Timing Generator for implementing a video genlock solution. Whereas the GS4911B itself cleans low-frequency jitter, the GS4915 is designed to clean primarily the higher frequency jitter of clocks generated by the GS4911B. Here we list the critical parameters for GS4911B and GS4915.
  • Thank you for taking the time to view this presentation on “ Timing Generators and ClockCleaner Solutions ” . If you would like to learn more or go on to purchase some of these devices, you may either click on the part list link, or simply call our sales hotline. For more technical information you may either visit the GENNUM site, or if you would prefer to speak to someone live, please call our hotline number, or even use our ‘live chat’ online facility.
  • Timing Generators and ClockCleaner Solutions

    1. 1. Timing Generators and ClockCleaner Solutions <ul><li>Source: GENNUM </li></ul>
    2. 2. Introduction <ul><li>Purpose </li></ul><ul><ul><li>To introduce Gennum’s timing generator and clock cleaner technology and its product offerings </li></ul></ul><ul><li>Outline </li></ul><ul><ul><li>Genlock technology </li></ul></ul><ul><ul><li>Analog & Digital Video Timing and Studio Sync </li></ul></ul><ul><ul><li>GEN Clock ™ product family and their key features </li></ul></ul><ul><li>Content </li></ul><ul><ul><li>17 pages </li></ul></ul>
    3. 3. Why Synchronize? <ul><li>Any video receiver must synchronize its circuitry to the timing information embedded in the input video to that circuit. </li></ul><ul><li>If the input timing changes abruptly then the receiver must re-sync to the new input timing. This can take several milliseconds and may result in visible disruptions in the video stream. </li></ul><ul><li>A common example of when timing might abruptly change is when switching cameras during a studio news broadcast. </li></ul><ul><li>If the cameras are not properly synchronized you will see tears, skips, jumps, etc. on your television at home. </li></ul>
    4. 4. Genlock Studio Example House Reference VTR 1 Movie Commercial 1 Commercial 2 TV VTR 2 VTR 3 switch Genlock Circuitry
    5. 5. What is Genlock? <ul><li>Genlock is short for ‘Generator Lock’. </li></ul><ul><li>It refers to the process of synchronizing multiple pieces of video equipment so when multiple pieces of equipment in a system are synchronized they are said to be genlocked. </li></ul><ul><ul><li>Genlock is accomplished by locking everything to a studio reference (e.g. a master sync pulse generator). </li></ul></ul><ul><li>Synchronizing all pieces of equipment in a studio is fundamental. i.,e if equipment is not genlocked then : </li></ul><ul><ul><li>When mixing, editing, or switching between two sources the image stability will not be maintained. </li></ul></ul><ul><ul><li>Audio sync problems may occur when switching between video sources with embedded audio. </li></ul></ul><ul><ul><li>The video in each piece of equipment may start to drift over time. </li></ul></ul>
    6. 6. Genlock – Traditional Methods <ul><li>Traditional Genlock circuitry requires multiple discrete components on a board , and is usually a ‘homegrown’ solution involving ; </li></ul><ul><ul><li>Sync separator, PLL, VCXOs for different standards, timing logic. </li></ul></ul><ul><li>To design traditional genlock circuitry: </li></ul><ul><ul><li>The user needs to determine the timing relationship between the reference and the desired output format. </li></ul></ul><ul><ul><li>Use the appropriate VCXO(s), flip-flops, filter, and FPGA to create the clock and timing signals. </li></ul></ul><ul><li>Disadvantages of the traditional methods include: </li></ul><ul><ul><li>Requires unique circuitry for each video frequency (multiple circuitry and VCXOs required for multi-format equipment). </li></ul></ul><ul><ul><li>Depending on video standards, circuitry may be hard to design (e.g. locking HD to SD may require intermediate locking stages). </li></ul></ul><ul><ul><li>Solution may take up a lot of board space (especially in multi-format equipment). </li></ul></ul>
    7. 7. Analog Video Timing and Studio Sync <ul><li>Usually an analog video signal containing all the standard sync and colour burst information as other analog video but with the image data set to black level – referred to as “Black and Burst”. </li></ul><ul><li>The studio sync is produced by a sync pulse generator (SPG) and distributed to all the video equipment in the studio. </li></ul>
    8. 8. Synchronous Switching In a perfect world…
    9. 9. Synchronous Switching Skew between two channels
    10. 10. What are GEN Clocks? <ul><li>The GEN Clocks TM family are a group of products that generate the clock and timing signals required for most video and graphics systems. </li></ul><ul><li>Generates multiple clocks </li></ul><ul><ul><li>3 video clocks </li></ul></ul><ul><ul><li>3 audio clocks </li></ul></ul><ul><ul><li>8 configurable timing signal clocks </li></ul></ul><ul><li>Members of the GS49xx family are GS4900B, GS4901B, GS4910B and GS4911B. </li></ul><ul><li>The GS4911B is an SD/HD/Graphics Video and Audio Timing Generator with Genlock incorporating all the features of the other devices. </li></ul>
    11. 11. Gennum GEN Clock Family <ul><li>Clock Cleaner – GS4915 </li></ul><ul><ul><li>27MHz, 74.25MHz,74.175MHz, 148.5Mhz, 148.35MHz </li></ul></ul><ul><ul><li>DOUBLE clock mode available when 74.25MHz and 74.175MHz is input. </li></ul></ul><ul><ul><li>Single Ended and Differential I/O. </li></ul></ul>Part Video Clocks Graphics Clocks Audio Clocks Custom Clocks MAX PCLK GS4900B √ 54MHz GS4901B √ √ 54MHz GS4910B √ √ √ 165MHz GS4911B √ √ √ √ 165MHz
    12. 12. GS4911B Key Features <ul><li>Clock Synthesis </li></ul><ul><ul><li>Pre-programmed to generate 8 video, 13 graphic, and 7 audio clock periods. </li></ul></ul><ul><ul><li>One differential and 2 single-ended video/graphics clocks with skew control. </li></ul></ul><ul><ul><li>3 audio clock outputs. </li></ul></ul><ul><ul><li>Custom video and audio clock frequencies may be programmed. </li></ul></ul><ul><li>Timing Generation </li></ul><ul><ul><li>Generate up to 8 different timing signals at a time. </li></ul></ul><ul><ul><li>Choose from 10 different pre-programmed timing signals (H and V Sync and Blanking, F Sync, F Digital, 10FID, AFS, DE) and 4 user-programmable timing signals. </li></ul></ul><ul><ul><li>Pre-programmed to generate 35 different video formats and 13 different graphics formats OR user may program their own custom video formats. </li></ul></ul>
    13. 13. GS4911B Key Features cont’d <ul><li>Genlock Capability </li></ul><ul><ul><li>Automatic input format detection for 5 1 different reference timing formats. </li></ul></ul><ul><ul><li>Output may be cross-locked to a different input reference (automatic for many standards, otherwise the user may manually program the internal PLL). </li></ul></ul><ul><ul><li>Clock and timing outputs may be offset relative to the reference. </li></ul></ul><ul><ul><li>‘ Freeze’ (flywheel) operation on loss of reference. </li></ul></ul><ul><li>Other features/specifications </li></ul><ul><ul><li>64-pin QFN package (9x9mm). </li></ul></ul><ul><ul><li>Small package size replaces multiple VCXOs, PLLs and timing generators. </li></ul></ul><ul><ul><li>Typical power consumption of 300mW. </li></ul></ul>
    14. 14. GS4911B Output Clock & Timing <ul><li>GS49 11B delivers 3 types of outputs: </li></ul><ul><ul><li>Video Clock (PCLK) </li></ul></ul><ul><ul><li>Timing Signals (TIMING1~8) </li></ul></ul><ul><ul><li>Audio Clock (ACLK) </li></ul></ul><ul><li>Video clocks and timing signals correspond to a particular video standard . </li></ul><ul><li>Audio clocks correspond to common audio sampling rates . </li></ul><ul><li>Clock & timing generation requires only one 27MHz external crystal . </li></ul>
    15. 15. GS4915 Clock Cleaner <ul><li>Reduces jitter on I/P video clocks, namely; </li></ul><ul><ul><li>HD data rates (148.5MHz, 148.5/1.001MHz, 74.25MHz, 74.25/1.001MHz) </li></ul></ul><ul><ul><li>SD data rates (27MHz) </li></ul></ul><ul><li>Typical O/P jitter of 20ps guarantees 3G-SDI compliance when used with any serializers. </li></ul><ul><li>Automatic bypass for all other frequencies. </li></ul><ul><li>Skew control pin allows the users to adjust the relative timing of the regenerated output clock relative to the input clock. </li></ul><ul><li>Loop bandwidth adjustable as low as 10kHz. </li></ul><ul><li>Selectable I/Os either differential or single-ended. </li></ul><ul><li>Requires external VCO using Gennum's GO1555. </li></ul><ul><li>Clock input may be either LVDS or CMOS levels and fed by the GS4911B clock generator. </li></ul>
    16. 16. GS4911B & GS4915 Critical Parameters <ul><li>Ideal complement for GS4911B in any SDI application clean high frequency jitter. </li></ul><ul><li>Best solution on the market acting as a “jitter reducer” for differential clocks that will be used by FPGAs with jitter sensitive SDI serializers. </li></ul><ul><li>Auto mode checks the incoming input clock to see if its frequency matches the SD/HD clock rates. If it’s a match then it replaces the I/P with a phase locked, cleaned up clock. If no match then it bypasses the I/P directly to the O/P. </li></ul><ul><li>Helps FPGAs achieve adequate jitter performance and meet SMPTE compliance for the parallel data at 74.25 MHz to be accompanied by a double rate clock at 148.5 MHz. </li></ul><ul><li>Can generate a 148.5 MHz clean output clock locked to a 74.25 MHz input clock, and a 148.35 MHz clean output clock locked to a 74.175 MHz input clock which are used by HD and 3G-SDI applications. </li></ul><ul><li>Skew control can advance the O/P clocks by 1/4 of the O/P PCLK period to accommodate downstream setup and hold requirements. </li></ul>
    17. 17. Additional Resource <ul><li>For ordering GEN Clock, please click the part list or </li></ul><ul><li>Call our sales hotline </li></ul><ul><li>For more product information go to </li></ul><ul><ul><li>http://www.gennum.com/video/functions/timing.php </li></ul></ul><ul><li>For additional inquires contact our technical service hotline or even use our “Live Technical Chat” online facility </li></ul>

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