Stratix FPGA Overview

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Overview of the Major Features and Design Capabilities of the Stratix Family FPGAs

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  • Welcome to this module on the Stratix family FPGA from Altera. The module overviews the major features of the Stratix family FPGA and Design Capabilities of the Stratix Family FPGAs.
  • Altera understands programmable devices are part of a bigger picture, and that true design success requires an array of other tools. To that end, Altera complements its complex programmable logic devices (CPLDs) and field programmable gate arrays (FPGAs) with sophisticated software tools, pre-verified and configurable intellectual property (IP) cores, a soft-core processor – Nios II, development kits, and reference designs. Altera’s comprehensive solution portfolios result in a faster, simplified design process and, in turn, faster time to market and lower development costs. With Altera® solutions, you can undertake your design, confident that you’ll be able to meet your unique application design goals.
  • Altera’s Stratix® FPGAs were designed to address your design and business challenges, anticipate the unforeseen, and help you win in your market. The family supports your applications’ increased levels of integration and complexity with higher densities and performance, while decreasing power consumption. With its flexible and efficient logic architecture, enhanced memory blocks, and high-capacity digital signal processing (DSP) blocks, Stratix FPGAs meet your system’s most demanding requirements.
  • The Stratix® series of FPGA families enables you to deliver high-performance, state-of-the-art products to market faster with lower risk and higher productivity. By combining high density, high performance, and a rich feature set, FPGAs in the Stratix series allow you to integrate more functions and maximize system bandwidth. Stratix and the Stratix GX variants are the original members of the Stratix FPGA series. This high-performance FPGA family introduced DSP hard IP blocks along with Altera's ubiquitous TriMatrix on-chip memory and flexible I/O structures. Stratix II  and  Stratix II GX  variant FPGAs introduced the adaptive logic module (ALM) architecture, which uses a high-performance, 8-input fracturable look-up table (LUT) in place of a 4 input LUT, and which is found in Altera's newest high-end FPGAs today. This second-generation high-performance FPGA family includes best-in-class 6.375-Gbps transceiver-based variant devices. These Stratix II GX FPGAs are available in volume and are still highly recommended for new designs. Stratix III FPGAs are the industry’s lowest power high-performance 65-nm FPGAs. Logic rich (L) and enhanced for memory (E) and digital signal processing (DSP) variants allow you to balance your resource requirements to your design without having to design in a device any bigger than is absolutely necessary—saving board real estate, compilation time, and money. Stratix III FPGAs target high-end core system processing designs in many applications. Stratix IV  FPGAs are the fourth-generation Stratix FPGA family and provide the highest density, highest performance and lowest power of any 40-nm FPGA. With enhanced (E) and enhanced with transceivers (GX) variants, Stratix IV FPGAs address many markets and applications, such as wireless and wireline communications, military, and broadcast.
  • Stratix™ devices feature the TriMatrix™ memory structure, composed of three sizes of embedded RAM blocks. The TriMatrix memory offers different memory structures that can implement a wide variety of memory functions found in complex designs. Designers can use the smaller M512 RAM blocks for first-in first-out (FIFO) functions and clock domain buffering where memory bandwidth is critical. The revolutionary M-RAM block addresses the FPGA requirement for large buffering applications such as intellectual property (IP) packet buffering and system cache. The M4K blocks are ideal for medium-sized memory applications such as asynchronous transfer mode (ATM) cell processing.
  • The high-performance Stratix™ device architecture consists of vertically arranged logic elements (LEs), TriMatrix ™ memory blocks , digital signal processing (DSP) blocks, and phase-locked loops (PLLs) that are surrounded by I/O elements (IOEs) as depicted in Figure . A speed-optimized interconnect and low-skew clock network provide connectivity between each of these structures for clock and data signals.
  • Stratix devices are based on the MultiTrack™ interconnect with DirectDrive™ technology. The MultiTrack interconnect consists of continuous, performance-optimized routing lines of different lengths used for communication within and between distinct design blocks. The MultiTrack interconnect structure is complemented by an advanced, low-skew clock network for clock distribution within the device, providing access to up to 22 clock domains per region. Each Stratix device features up to 16 global clock networks that span the entire device, feeding all architectural structures. Global clocks can be driven by internal logic, phase-locked loop (PLL) outputs, or device input pins, and can be used for other device-wide signals with large fan-outs such as asynchronous clears and clock enables, as shown in Figure.
  • Each DSP block is optimized for maximum performance of up to 333 million samples per second (MSPS) per block allowing for efficient implementation of high-precision DSP functions. For example, a 180-tap, 5 MSPS finite impulse response (FIR) filter can be implemented within a single DSP block using external add-accumulate circuitry. Further, these DSP blocks have been optimized to interface with the specialized memory structures in Stratix devices for memory-intensive DSP applications.
  • The DSP blocks in Stratix™ devices are high-performance embedded DSP units optimized for applications such as: Rake receivers Voice over Internet protocol (VoIP) gateways Orthogonal frequency division multiplexing (OFDM) transceivers Image processing applications Multimedia entertainment systems
  • Stratix devices are designed to reliably transfer data to and from external memory devices. Stratix devices include dedicated I/O features that ensure that all timing requirements are met and that performance is maximized.
  • Here is the example that LG uses Stratix in their HDTV products.
  • Here is another example that Doremi has relied exclusively on Altera® FPGAs to implement their high bandwidth video products.
  • Altera’s Quartus II design software is #1 in performance and productivity for CPLD, FPGA, and structured ASIC designs. Used in combination with a broad portfolio of design-ready intellectual property (IP) cores, you get unmatched levels of performance and productivity in your designs. Quartus II software is easy to use and enables you to get products to market faster. Dramatically improve your productivity compared to traditional FPGA design flows.
  • Altera offers a broad portfolio of easy-to-use intellectual property (IP) cores, also known as megafunctions. These IP cores are high-quality “building blocks” that you can drop into your system designs, increasing productivity by avoiding the time-consuming task of creating complete designs from scratch. Easy-to-use, pre-verified, and configurable, Altera® IP cores are optimized for the latest Altera devices and are fully supported in Quartus® II design software. Some of the IP cores are from leading third-party IP vendors who have developed, optimized, and qualified their IP products for Altera devices, licensing them directly to our customers. Discover how quickly you can use these cores to accelerate your system design, lower development costs, speed your time to market, and give your systems a competitive edge.
  • With Altera’s versatile, 32-bit Nios® II embedded processors, you can drag and drop the precise mix of processors and peripherals to build an exact-fit embedded system in just minutes, adapt rapidly to changes in the market, and get a jump on your competition. These processors are backed by a full range of embedded software tools and operating system support from Altera and industry-leading embedded partners. With Nios II processors, you can upgrade system performance at any stage of the product life cycle without having to redesign the board or develop hand-optimized software. The Nios II C-to-Hardware Acceleration (C2H) Compiler boosts performance of time-critical C subroutines, converting them to powerful hardware accelerators with a simple “right-click to accelerate” interface. As a soft-core processor, our Nios II offering can be implemented in any of Altera’s FPGA or structured ASIC device families, insulating your embedded software investment from processor obsolescence. Used by each of the world’s top 20 OEMs and with more than 20,000 development kits sold worldwide, the proven Nios II processor is the most popular configurable soft processor in the industry.
  • Thank you for taking the time to view this presentation on Altera Stratix FPGAs. If you would like to learn more or go on to purchase some of these devices, you may either click on the part list link, or simply call our sales hotline. For more technical information you may either visit the Altera site – link shown – or if you would prefer to speak to someone live, please call our hotline number, or even use our ‘live chat’ online facility.
  • Stratix FPGA Overview

    1. 1. Stratix FPGA Overview <ul><li>Source: Altera Corporation </li></ul>
    2. 2. Introduction <ul><li>Purpose </li></ul><ul><ul><li>This module will overview the Major Features and Design Capabilities of the Stratix Family FPGAs. </li></ul></ul><ul><li>Outline </li></ul><ul><ul><li>Provide an overview of the Stratix Architecture, Clock Management, Memory Blocks ,DSP Blocks and I/O features. </li></ul></ul><ul><li>Contents </li></ul><ul><ul><li>18 pages </li></ul></ul><ul><li>Duration </li></ul><ul><ul><li>15 Minutes </li></ul></ul>
    3. 3. Altera product lineup High-end FPGAs with transceiver options CPLDs ASICs Low-cost FPGAs Design software Intellectual property (IP) Development kits Programmable logic solutions for all your needs Low-cost protocol-optimized FPGAs Embedded soft-core processors
    4. 4. High Performance FPGAs <ul><li>Highest-density and fastest-performance FPGAs </li></ul><ul><li>Programmable Power Technology and selectable core voltage provide lowest-power solution </li></ul><ul><li>Seamless migration to HardCopy® structured ASICs </li></ul><ul><li>Excellent signal integrity </li></ul>www.altera.com/Stratix
    5. 5. Stratix for High-Performance Applications 2002 2004 2006 <ul><li>10K – 79K logic elements (LEs) </li></ul><ul><li>Up to 7 Mbits RAM available </li></ul><ul><li>DDR support </li></ul><ul><li>Multipliers(18x18) – 24 to 88 </li></ul><ul><li>15K – 179K LEs </li></ul><ul><li>Up to 9 Mbits RAM </li></ul><ul><li>Multiplier(18 x 18) – 48 to 384 </li></ul><ul><li>DDR2 support </li></ul><ul><li>Nios II embedded processor </li></ul><ul><li>72K – 681K LEs </li></ul><ul><li>31 Mbits RAM </li></ul><ul><li>Multiplier(18 x 18) – 512 to 1360 </li></ul><ul><li>Higher performance DDR3 support </li></ul><ul><li>Nios II embedded processor </li></ul>2008 <ul><li>48K – 338K LEs </li></ul><ul><li>Up to 20 Mbits RAM </li></ul><ul><li>Multiplier(18 x 18) – 216 to 896 </li></ul><ul><li>DDR3 support </li></ul><ul><li>Nios II embedded processor </li></ul>130nm 90nm 65nm 40nm III
    6. 6. Embedded Memory in Stratix
    7. 7. Stratix Architecture
    8. 8. Clock Distribution in Stratix <ul><li>Highly versatile PLLs </li></ul><ul><li>Four enhanced PLLs </li></ul><ul><li>Eight fast PLLs </li></ul><ul><li>Stratix PLL features </li></ul><ul><ul><li>Clock multiplication and division </li></ul></ul><ul><ul><li>Phase shift </li></ul></ul><ul><ul><li>Clock switchover </li></ul></ul><ul><ul><li>Programmable duty cycle </li></ul></ul><ul><ul><li>PLL reconfiguration </li></ul></ul>
    9. 9. DSP Block in Stratix <ul><li>A Multiplier block </li></ul><ul><li>Adder/Subtractor/Multiplier </li></ul><ul><li>Block </li></ul><ul><li>Summation Block </li></ul><ul><li>Output Interface </li></ul><ul><li>Output Registers </li></ul><ul><li>Routing and Control signals </li></ul>
    10. 10. Stratix DSP Blocks for Multiple Applications
    11. 11. Stratix Device I/O Interface Features - <ul><li>Multi-Register I/O Elements (IOEs) </li></ul><ul><li>Programmable Input Delays </li></ul><ul><li>Programmable ZBT Delay </li></ul><ul><li>Dedicated Data Strobe (DQS) Circuitry </li></ul><ul><li>Positive Edge Alignment Circuitry </li></ul>
    12. 12. LG Electronics Luxury Gold 71” PDP Television Altera Products Chosen: Altera Value Proposition: <ul><li>Short Time-to-Market with Differentiating Features </li></ul><ul><li>Path to Low-Cost HardCopy Structured ASICs </li></ul>Industry: Consumer HDTV Application: © 2007 Altera Corporation— Public Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation
    13. 13. Doremi Labs V1-HD Compressed HDTV Recorder Altera Products Chosen: Industry: Broadcast HD Video Disk Recorder Application: “ Doremi has relied exclusively on Altera® FPGAs to implement our high bandwidth video products. Although we have been using a third-party synthesis tool, since Quartus II v2.0, we have had great success using the built-in Quartus synthesizer. We have also used the LogicLock™ feature in every design that exceeds 100K gates. LogicLock has enabled us to design, debug, meet timing, and lock down every major block of the design, and subsequently reduce compile time and interference across design blocks.” – Camille Rizko, Technical Director Altera Value Proposition: <ul><li>Tools Ease of Use </li></ul><ul><li>Product Line Breadth </li></ul>© 2007 Altera Corporation— Public Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation
    14. 14. Design Software <ul><li>Number one design software for performance and productivity </li></ul><ul><li>Industry’s only complete design solution for CPLDs, FPGAs, and structured ASICs </li></ul><ul><li>Integrated development environment to accelerate system-level design </li></ul><ul><li>Seamless integration with leading third-party software tools and flows </li></ul>www.altera.com/software Design Idea
    15. 15. Intellectual Property <ul><li>Optimized to increase performance and lower cost in high-speed I/O interconnect, digital signal processing (DSP), and embedded applications </li></ul><ul><li>Easy-to-use, pre-verified, and configurable to reduce time to market </li></ul><ul><li>Part of Altera’s complete, productivity-enhancing solution portfolio. </li></ul>www.altera.com/IPmegastore
    16. 16. Embedded Soft-Core Processor <ul><li>Configure an exact-fit embedded system in minutes </li></ul><ul><li>Supported by an array of software tools from Altera and leading embedded partners </li></ul><ul><li>Used by more designers than any other configurable processor </li></ul><ul><li>World’s most versatile embedded processor </li></ul>www.altera.com/NiosII Features Performance Cost Life Cycle
    17. 17. Summary of Benefits <ul><li>First time users experience the Altera design flow for minimal cost </li></ul><ul><li>Design examples aid design implementation and serve as starting points for customer designs </li></ul><ul><li>FPGA design and Software development can begin early in the design process </li></ul><ul><li>Device features can be evaluated </li></ul>
    18. 18. Additional Resource <ul><li>For ordering the Stratix FPGAs, please click the part list or </li></ul><ul><li>Call our sales hotline </li></ul><ul><li>For additional inquires contact our technical service hotline </li></ul><ul><li>For more product information go to </li></ul><ul><ul><li>http://www.altera.com/products/devices/stratix-fpgas/about/stx-about.html </li></ul></ul>

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