Your SlideShare is downloading. ×

STM32 MCU Family

1,598

Published on

An overview of STM32 MCU family and its key features

An overview of STM32 MCU family and its key features

Published in: Technology, Business
1 Comment
2 Likes
Statistics
Notes
  • very helpful ....thank you very much
       Reply 
    Are you sure you want to  Yes  No
    Your message goes here
No Downloads
Views
Total Views
1,598
On Slideshare
0
From Embeds
0
Number of Embeds
1
Actions
Shares
0
Downloads
1
Comments
1
Likes
2
Embeds 0
No embeds

Report content
Flagged as inappropriate Flag as inappropriate
Flag as inappropriate

Select your reason for flagging this presentation as inappropriate.

Cancel
No notes for slide
  • Welcome to this module on STM32 MCU family from ST. This module will overview the STM32 MCU family and discuss the key features and applications of STM32 products.
  • The ARM Cortex™-M3 processor is the generation of ARM processors for embedded systems. The advanced architectural features of the Cortex-M3 processor reduce memory size while delivering industry-leading performance in a small, power-efficient RISC core. It thus provides an ideal platform for the migration of many different applications around the world from legacy devices to the 32-bit microcontroller world.
  • The STM32 family incorporates the high-performance ARM Cortex™-M3 32-bit RISC core operating at up to 72 MHz frequency, high-speed embedded Flash memories and SRAM, and an extensive range of enhanced peripherals and I/Os connected to two APB buses. All devices offer standard communication interfaces, such as I2Cs, SPIs, and USARTs, one 12-bit ADC and the general-purpose timers. STM32 has two complete lines, Performance line and Access line. Both lines are pin-to pin and software-compatible.
  • These features make the STM32 microcontroller family suitable for a wide rage of applications.
  • STM32 has two complete lines, Performance line and Access line. Both lines are pin-to pin and software-compatible and offer excellent connectivity and control. The Performance line, STM32F103, operates at 72 MHz, with more on-chip RAM and peripherals. The Access line, STM32F101, operates at 36 MHz. With its Cortex-M3 core at 72 MHz, it is able to perform high-end computation. The Access line is the entry point of the STM32 family. It has the power of the 32-bit MCU but at a 16-bit MCU cost.
  • The main system consists of five masters and three slaves. The five masters include Cortex-M3 core ICode bus, DCode bus, System bus and two general-pupose DMA. The three slaves include internal SRAM, internal Flash memory and AHB to APB bridges which connect all the APB peripherals.
  • The device requires a 2.0-to-3.6 V operating voltage supply (VDD). An embedded regulator is used to supply the internal 1.8 V digital power. The voltage regulator is always enabled after Reset. To improve conversion accuracy, the ADC has an independent power supply which can be separately filtered and shielded from noise on the PCB. The device has an integrated power-on reset (POR)/power-down reset (PDR) circuitry. It is always active, and ensures proper operation starting from/down to 2 V. The device remains in reset mode when VDD is below a specified threshold, VPOR/PDR, without the need for an external reset circuit. The device features an embedded programmable voltage detector (PVD) that monitors the VDD/VDDA power supply and compares it to the VPVD threshold. An interrupt can be generated when VDD/VDDA drops below the VPVD threshold and/or when VDD/VDDA is higher than the VPVD threshold. The interrupt service routine can then generate a warning message and/or put the MCU into a safe state. The PVD is enabled by software.
  • The backup registers are implemented in the backup domain that remains powered on by VBAT when the VDD power is switched off. They are not reset when the device wakes up from Standby mode or by a system reset or power reset. In addition, the BKP control registers are used to manage the Tamper detection feature and RTC calibration.
  • There are three types of reset, defined as system Reset, power Reset and backup domain Reset. A system reset sets all registers to their reset values except the reset flags in the clock controller CSR register and the registers in the Backup domain. A power reset is generated when PRO/PDR reset or existing standby mode occurs. Backup domain reset is generated when software is reset or V DD or V BAT power on, if both supplies have previously been powered off. Three different clock sources can be used to drive the system clock, HIS clock, HSE clock, and PLL clock. Each clock source can be switched on or off independently when it is not used, to optimize power consumption. After a system reset, the HSI oscillator is selected as system clock. When a clock source is used directly or through the PLL as system clock, it is not possible to stop it.
  • The RTC consists of two main units. The first one (APB1 Interface) is used to interface with the APB1 bus. This unit also contains a set of 16-bit registers accessible from the APB1 bus in read or write mode. The APB1 interface is clocked by the APB1 bus clock in order to interface with the APB1 bus. The RTC provides a set of continuously running counters which can be used with suitable software to provide a clock calendar function, and provides an alarm interrupt and a periodic interrupt.
  • The STM32 has two embedded watchdog peripherals which offer a combination of high safety level, timing accuracy and flexibility of use. Both Watchdog peripherals (Independent and Window) serve to detect and resolve malfunctions due to software failure, and to trigger system reset or an interrupt (window watchdog only) when the counter reaches a given timeout value. The independent watchdog (IWDG) is clocked by its own dedicated low-speed clock (40 kHz) and thus stays active even if the main clock fails. The window watchdog (WWDG) clock is prescaled from the APB1 clock and has a configurable time-window that can be programmed to detect abnormally late or early application behavior.
  • Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog alternate functions. All GPIOs are high-current capable except for analog inputs. The I/Os alternate function configuration can be locked if needed following a specific sequence in order to avoid spurious writing to the I/Os registers.
  • Direct memory access (DMA) is used in order to provide high-speed data transfer between peripherals and memory as well as memory to memory. Data can be quickly moved by DMA without any CPU actions. This keeps CPU resources free for other operations. The two DMA controllers have 12 channels in total (7 for DMA1 and 5 for DMA2), each dedicated to managing memory access requests from one or more peripherals. It has an arbiter for handling the priority between DMA requests.
  • The 12-bit ADC is a successive approximation analog-to-digital converter. It has up to 18 multiplexed channels allowing it measure signals from 16 external and two internal sources. A/D conversion of the various channels can be performed in single, continuous, scan or discontinuous mode. The result of the ADC is stored in a left-aligned or right-aligned 16-bit data register.
  • The DAC module is a 12-bit, voltage output digital-to-analog converter. The DAC can be configured in 8- or 12-bit mode and may be used in conjunction with the DMA controller. In 12-bit mode, the data could be left- or right-aligned. The DAC has two output channels, each with its own converter. In dual DAC channel mode, conversions could be done independently or simultaneously when both channels are grouped together for synchronous update operation.
  • The SPI allows half/ full-duplex, synchronous, serial communication with external devices. The interface can be configured as the master and in this case it provides the communication clock (SCK) to the external slave device. The interface is also capable of operating in multimaster configuration. I 2 C bus Interface serves as an interface between the microcontroller and the serial I 2 C bus. It provides multimaster capability, and controls all I 2 C bus-specific sequencing, protocol, arbitration and timing. It supports standard and fast speed modes. It is also SMBus 2.0 compatible. The USART offers a flexible means of full-duplex data exchange with external equipment requiring an industry standard NRZ asynchronous serial data format. The USART offers a very wide range of baud rates using a fractional baud rate generator.
  • Thank you for taking the time to view this presentation on STM32 MCU family . If you would like to learn more or go on to purchase some of these devices, you can either click on the link embedded in this presentation, or simple call our sales hotline. For more technical information you can either visit the ST site – link shown – or if you would prefer to speak to someone live, please call our hotline number, or even use our ‘live chat’ online facility.
  • Transcript

    • 1. STM32 MCU Family
      • Source: STMicroelectronics
    • 2. Introduction
      • Purpose
        • This module provides information about the STM32 MCU family.
      • Outline
        • Provide an overview of STM32 MCU family.
        • Discuss the key features and applications of STM32 MCU.
      • Contents
        • 17 pages
      • Duration
        • 10 Minutes
    • 3. The World of STM32
    • 4. Key Features
      • ARM 32-bit Cortex™-M3 core with embedded Flash and SRAM
        • Up to 512KB Flash memory
        • Up to 64KB SRAM
      • Clock, reset and supply management
      • Multiple communication peripherals
        • I 2 C, USART, SPI
      • Sleep, Stop and Standby low power mode
      • Multiple 16-bit timer
      • Real-time clock
      • DMA controller
      • 12-bit DAC
      • Easy development, fast time to market
    • 5. Applications
      • Industrial:
      • PLC
      • Inverters
      • Printers, scanners
      • Industrial networking
      • Building and security:
      • Alarm systems
      • Video intercom
      • HVAC
      • Low power:
      • Glucose meters
      • Power meters
      • Battery operated application
      • Appliances:
      • Motor drive
      • Application control
      • Consumer:
      • PC peripherals, gaming
      • Digital camera, GPS platforms
    • 6. STM32 Product Lines
    • 7. System Architecture
    • 8. Power Control
      • Power supplies
        • 2.0 to 3.6V operating voltage supply (V DD )
        • The ADC has an independent power supply.
        • Battery backup domain
        • The voltage regulator is always enable after reset.
      • Power supply supervisor
        • Power on reset (POR)/Power down reset (PDR)
        • Programmable voltage detector (PVD)
        • Sleep/Stop/Standby low-power mode
        • Slowing down system clocks
        • Peripheral clock gating
    • 9. Backup Register (BKP)
      • 20-byte data registers (in access line) or 84-byte data registers (in performance line)
      • Status/control register for managing tamper detection with interrupt capability
      • Calibration register for storing the RTC calibration value
      • Possibility to output the RTC Calibration Clock, RTC Alarm pulse or Second pulse on TAMPER pin PC13 (when this pin is not used for tamper detection)
    • 10. Reset and Clock Control (RCC)
      • Reset
        • System reset
        • Power reset
        • Low-power management reset
      • Clock
        • High speed internal (HIS) oscillator clock
        • High speed external (HSE) oscillator clock
        • PLL clock
    • 11. Real Timer Clock (RTC)
      • Programmable prescaler: division factor up to 220
      • 32-bit programmable counter for long-term measurement
      • Two separate clocks: PCLK1 for the APB1 interface and RTC clock
      • The RTC clock source could be any of the following three
        • HSE clock divided by 128
        • LSE oscillator clock
        • LSI oscillator clock
      • Two separate reset types
        • The APB1 interface is reset by system reset
        • The RTC Core
      • Three dedicated maskable interrupt lines
        • Alarm interrupt, for generating a software programmable alarm interrupt.
        • Seconds interrupt, for generating a periodic interrupt signal with a programmable period length (up to 1 second).
        • Overflow interrupt, to detect when the internal programmable counter rolls over to zero.
    • 12. Watchdog (WDG)
      • Independent watchdog (IWDG)
        • Free-running downcounter
        • Clocked from an independent RC oscillator (can operate in Standby and Stop modes)
        • Reset (if watchdog activated) when the downcounter value of 0x000 is reached
      • Window watchdog (WWDG)
        • Programmable free-running downcounter
        • Conditional reset
          • – Reset (if watchdog activated) when the downcounter value becomes less than 40h
          • – Reset (if watchdog activated) if the downcounter is reloaded outside the window
    • 13. General Purpose I/Os (GPIOs)
      • Two 32-bit configuration registers
      • Each I/O port bit is freely programmed in several mode
        • Input floating
        • Input pull-up
        • Input-pull-down
        • Analog Input
        • Output open-drain
        • Output push-pull
        • Alternate function push-pull
        • Alternate function open-drain
    • 14. DMA Controller
      • 12 independently configurable channels (requests): 7 for DMA1 and 5 for DMA2
      • Each of the 12 channels is connected to dedicated hardware DMA requests, software
      • trigger is also supported on each channel.
      • Priorities between requests from channels of one DMA are software programmable
      • Independent source and destination transfer size, emulating packing and unpacking
      • Support for circular buffer management
      • Memory-to-memory transfer
      • Peripheral-to-memory and memory-to-peripheral, and peripheral-to-peripheral transfers
      • Access to Flash, SRAM, peripheral SRAM, APB1, APB2 and AHB peripherals as source and destination
    • 15. ADC
      • 12-bit resolution
      • Interrupt generation at End of Conversion, End of Injected conversion and Analog Watchdog event
      • Single and continuous conversion modes
      • Scan mode for automatic conversion of channel 0 to channel ‘n’
      • Self-calibration
      • Data alignment with in-built data coherency
      • Channel by channel programmable sampling time
      • External trigger option for both regular and injected conversion
      • ADC conversion time:
        • Performance line devices: 1 μs at 56 MHz (1.17 μs at 72 MHz)
        • Access line devices: 1 μs at 28 MHz (1.55 μs at 36 MHz)
      • DMA request generation during regular channel conversion
    • 16. DAC
      • Two DAC converters: one output channel each
      • 8-bit or 12-bit monotonic output
      • Left or right data alignment in 12-bit mode
      • Synchronized update capability
      • Noise-wave generation
      • Triangular-wave generation
      • Dual DAC channel independent or simultaneous conversions
      • DMA capability for each channel
      • External triggers for conversion
    • 17. Communication Peripherals
      • Serial peripheral interface (SPI)
        • 8- or 16-bit transfer frame format selection
        • Master or slave operation
        • Multimaster mode capability
      • Inter-integrated circuit interface (I 2 C)
        • Parallel-bus/I 2 C protocol converter
        • Multimaster capability: the same interface can act as Master or Slave
        • Universal synchronous asynchronous receiver
        • Supports different communication speeds
      • Transmitter (USART)
        • Full duplex, asynchronous communications
        • NRZ standard format (Mark/Space)
        • Programmable data word length
    • 18. Additional Resource
      • For ordering the STM32 products, please click the part list or
      • call our sales hotline
      • For additional inquires contact our technical service hotline
      • For more product information go to
      • www.st.com/stm32
      Newark Farnell

    ×