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SC28C94: Quad Universal Asynchronous Receiver/Transmitter (QUART)
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SC28C94: Quad Universal Asynchronous Receiver/Transmitter (QUART)

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This training module introduces 28C94 quad universal asynchronous receiver/transmitter, its internal operation, and applications.

This training module introduces 28C94 quad universal asynchronous receiver/transmitter, its internal operation, and applications.

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SC28C94: Quad Universal Asynchronous Receiver/Transmitter (QUART) SC28C94: Quad Universal Asynchronous Receiver/Transmitter (QUART) Presentation Transcript

  • SC28C94: Quad Universal Asynchronous Receiver/Transmitter (QUART)
    • Source: NXP
  • Introduction
    • Purpose
      • This training module introduces 28C94 quad universal asynchronous receiver/transmitter, its internal operation, and applications.
    • Outline
      • UART overview
      • SC28C94 overview
      • Block diagram
      • Internal operations
      • Applications
    • Content
      • 14 pages
  • UART Overview
    • A Universal Asynchronous Receiver and Transmitter (UART) is used for serial communications – usually via a cable.
    • UARTs provide parallel-to-serial and serial-to-parallel data conversion for both the transmitter and receiver sections.
    CPU / MPU / MCU UART IC Receiver RxD Transmitter TxD RxD TxD Data bus (8 bit) Address bus CTRL bus
  • SC28C94 Quad UART (QUART)
    • Four Philips Semiconductors industry-standard UARTs
    • Eight byte receive FIFO and eight byte transmit FIFO for each UART
    • Parity, framing, and overrun error detection
    • False start bit detection
    • Low overhead interrupt control
    • Programmable interrupt priorities
    • Selectable baud rate for the receiver and transmitter
    • Single +5V power supply with low power mode
    • 1MHz 16x mode operation
    • Two multifunction programmable 16-bit counter/timers
  • Block Diagram Bus Buffer Timing Channel C Channel D I/O port Control Counter /Timer X2 X1/CLK D0-D7 Internal Bus DUART CD TxDC RxDC TxDD RxDD I/O[3:0]C I/O[3:0]D Interrupt Arbitration IACKN IRQN Operation Control RDN WRN CEN A0-A5 DACKN Channel A Channel B I/O port Control Counter /Timer TxDA RxDA TxDB RxDB I/O[3:0]A I/O[3:0]B DUART AB
  • Operation Control Block
    • The operation control logic receives operation commands from the CPU and generates appropriate signals to internal sections to control device operation.
    • It contains
      • address decoding
      • read and write circuits to permit communications with the microprocessor
    Operation Control RDN WRN CEN A0-A5 DACKN Address Decode R/W Control Internal Bus Mode Register d (MR0d, MR1d, MR2d) Mode Register d (MR0d, MR1d, MR2d) 011000 Mode Register c (MR0c, MR1c, MR2c) Mode Register c (MR0c, MR1c, MR2c) 010000 Mode Register b (MR0b, MR1b, MR2b) Mode Register b (MR0b, MR1b, MR2b) 001000 Mode Register a (MR0a, MR1a, MR2a) Mode Register a (MR0a, MR1a, MR2a) 00000 Wrtie (WRN=Low) Read (RDN=Low) A5:0
  • Timing Block
    • The timing block consists of
      • a crystal oscillator
        • operates directly from a 3.6864MHz crystal connected across the X1/CLK and X2 inputs
      • a baud rate generator
        • operates from the oscillator or external clock input
        • capable of generating 18 commonly used data communications baud rates ranging from 50 to 38.4K baud.
      • power up/down logic
    Timing X2 X1/CLK Crystal Oscillator Power Up/down Baud rate Generator Internal Bus
  • Interrupt Arbitration
    • The QUART contains eighteen sources which may cause an interrupt:
      • Four receiver data FIFO filled functions.
      • Four receiver BREAK detect functions.
      • Four transmitter FIFO space available functions.
      • Four “Change of State” detectors.
      • Two counter/timers.
    Interrupt Arbitration IACKN IRQN Logic Global Registers Interrupt Control Internal Bus
  • Channel Blocks
    • Transmitter
      • It accepts parallel data from the CPU and converts it to a serial bit stream on the TxD output pin.
    • Transmit FIFO (8 bytes)
      • Data is loaded from the transmit shift register.
    • Receiver
      • It accepts serial data on the RxD pin, converts the serial input to parallel format.
    • Receive FIFO (8 bytes)
      • Data is loaded from the receive shift register.
    • Input/Output control
      • There are 16 multi-use pins; four for each UART.
    • Counter/Timer
      • Counter: time delay
      • Timer: square wave
      • Time out: monitors the time between received data.
  • Wake-Up Mode
    • The QUART incorporates a special mode which provides automatic “wake up” of a receiver through address frame recognition for multi-processor or multi-station communications.
      • A ‘master’ station transmits an address character to the several ‘slave’ stations.
      • The receiver loads that character to the RxFIFO and set the RxRDY bit in the status register.
      • The local processor at the slave station will read the ‘address’ character just received.
      • If the address is matched the local processor will enable the local receiver and receive the following data characters.
  • Interface to Its Controlling Processor
    • The Asynchronous Interface
      • In this mode all of the interface pins are usually used.
      • During a read of the QUART DACKN signals that valid data is on the data bus.
      • During a write to the QUART DACKN signals that data placed on the bus by the control processor has been written to the addressed register.
    • The Synchronous Interface
      • The synchronous mode usually will not use the IACKN and DACKN.
    Processor SC28C94 CEN RDN WRN IACKN IRQN DACKN A0~A5 D0~D7
  • UART in GPS Navigation System
  • UART to Bluetooth Interfacing
  • Additional Resource
    • For ordering SC28C94 QUART, please click the part list or
    • Call our sales hotline
    • For additional inquires contact our technical service hotline
    • For more product information go to
      • http://www.nxp.com/#/pip/pip=[pip=SC28C94_3]|pp=[t=pip,i=SC28C94_3]|