PIC32MX5XX/6XX/7XX USB, CAN and Ethernet 32-Bit Flash Microcontrollers <ul><li>Source: M ICROCHIP </li></ul>
Introduction <ul><li>Purpose </li></ul><ul><ul><li>An overview study on High-Performance, USB, CAN and Ethernet 32-Bit Fla...
MCU Core Features <ul><li>80MHz, 1.56 DMIPS/MHz, 32-bit MIPS M4K® Core  </li></ul><ul><li>USB 2.0 On-The-Go Peripheral wit...
Other Features <ul><li>System   Features   </li></ul><ul><ul><li>512K   Flash   (plus   12K   boot   Flash)   </li></ul></...
Block Diagram
Memory Organization <ul><li>32-bit native data width </li></ul><ul><li>Separate User (KUSEG) and Kernel (KSEG0/KSEG1) mode...
Interrupt Controller <ul><li>Up to 96 Interrupt Sources </li></ul><ul><li>Up to 64 Interrupt Vectors </li></ul><ul><li>Sin...
Prefetch Cache Prefetch Module Block Diagram <ul><li>16 Fully Associative Lockable Cache Lines </li></ul><ul><li>16-Byte C...
Direct Memory Access (DMA) Controller <ul><li>Four Identical Channels, each Featuring Auto-Increment Source and Destinatio...
USB On-The-Go (OTG) USB Block Diagram
Comparator Voltage Reference (CVREF) •  High and low range selection •  Sixteen output levels available for each range •  ...
Ethernet Controller Ethernet Controller Block Diagram
Controller Area Network (CAN) PIC32MX CAN Module Block Diagram
10-BIT ANALOG-TO-DIGITAL CONVERTER (ADC) <ul><li>Successive Approximation Register (SAR) Conversion </li></ul><ul><li>Up t...
Parallel Master Port (PMP) <ul><li>8-Bit, 16-Bit Interface and Up to 16 Programmable Address Lines and Two Chip Select Lin...
Universal Asynchronous Receiver Transmitter <ul><li>Full-Duplex, 8-Bit or 9-Bit Data Transmission </li></ul><ul><li>Even, ...
Input Capture Input Capture Block Diagram <ul><li>Capture timer value on every falling edge of input at ICx pin and every ...
Additional Resource <ul><li>For ordering  PIC32MX5xx/6xx/7xx , please click the part list or </li></ul><ul><li>Call our sa...
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PIC32MX5XX/6XX/7XX USB, CAN and Ethernet 32-Bit Flash Microcontrollers

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An overview study on High-Performance, USB, CAN and Ethernet 32-Bit Flash Microcontrollers

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PIC32MX5XX/6XX/7XX USB, CAN and Ethernet 32-Bit Flash Microcontrollers

  1. 1. PIC32MX5XX/6XX/7XX USB, CAN and Ethernet 32-Bit Flash Microcontrollers <ul><li>Source: M ICROCHIP </li></ul>
  2. 2. Introduction <ul><li>Purpose </li></ul><ul><ul><li>An overview study on High-Performance, USB, CAN and Ethernet 32-Bit Flash Microcontrollers. </li></ul></ul><ul><li>Outline </li></ul><ul><ul><li>MCU and other Features </li></ul></ul><ul><ul><li>Block Diagram and Memory Organisation </li></ul></ul><ul><ul><li>Interrupt Controller, Pre-fetch Cache, DMA Controller </li></ul></ul><ul><ul><li>USB, Ethernet Controller, Comparator ref voltage </li></ul></ul><ul><ul><li>ADC, UART, CAN Features. </li></ul></ul><ul><li>Content </li></ul><ul><ul><li>18 pages </li></ul></ul>
  3. 3. MCU Core Features <ul><li>80MHz, 1.56 DMIPS/MHz, 32-bit MIPS M4K® Core </li></ul><ul><li>USB 2.0 On-The-Go Peripheral with integrated PHY </li></ul><ul><li>10/100 Ethernet MAC with MII/RMII Interfaces </li></ul><ul><li>4 Dedicated DMA Channels for USB OTG & Ethernet </li></ul><ul><li>5 Stage pipeline, Harvard architecture </li></ul><ul><li>MIPS16e mode for up to 40% smaller code size </li></ul><ul><li>Single cycle multiply and hardware divide unit </li></ul><ul><li>32 x 32-bit Core Registers </li></ul><ul><li>32 x 32-bit Shadow Registers </li></ul><ul><li>Fast context switch and interrupt response </li></ul>
  4. 4. Other Features <ul><li>System Features </li></ul><ul><ul><li>512K Flash (plus 12K boot Flash) </li></ul></ul><ul><ul><li>64K RAM (can execute from RAM) </li></ul></ul><ul><ul><li>8 Channel General Hardware DMA Controller </li></ul></ul><ul><ul><li>Flash pre-Fetch module with 256 Byte cache </li></ul></ul><ul><ul><li>Lock instructions or data in cache for fast access </li></ul></ul><ul><ul><li>Programmable vector interrupt controller </li></ul></ul><ul><li>Analog Features </li></ul><ul><ul><li>Fast and Accurate 16 channel 10-bit ADC, </li></ul></ul><ul><ul><li>Max 1 Mega sample per second at +/- 1LSB, conversion available during SLEEP & IDLE </li></ul></ul>
  5. 5. Block Diagram
  6. 6. Memory Organization <ul><li>32-bit native data width </li></ul><ul><li>Separate User (KUSEG) and Kernel (KSEG0/KSEG1) mode address space </li></ul><ul><li>Flexible program Flash memory partitioning </li></ul><ul><li>Flexible data RAM partitioning for data and program space </li></ul><ul><li>Separate boot Flash memory for protected code </li></ul><ul><li>Robust bus exception handling to intercept runaway code </li></ul><ul><li>Simple memory mapping with Fixed Mapping Translation (FMT) unit </li></ul><ul><li>Cacheable (KSEG0) and non-cacheable (KSEG1) address regions </li></ul>
  7. 7. Interrupt Controller <ul><li>Up to 96 Interrupt Sources </li></ul><ul><li>Up to 64 Interrupt Vectors </li></ul><ul><li>Single and Multi-Vector mode Operations </li></ul><ul><li>Five External Interrupts with Edge </li></ul><ul><li>Polarity Control </li></ul><ul><li>Interrupt Proximity Timer </li></ul><ul><li>Module Freeze in Debug mode </li></ul><ul><li>Seven User-Selectable Priority </li></ul><ul><li>Levels for each Vector </li></ul><ul><li>Four User-Selectable Sub-priority Levels within each Priority </li></ul><ul><li>Dedicated Shadow Set for User-Selectable Priority Level </li></ul><ul><li>Software can Generate any Interrupt </li></ul><ul><li>User-Configurable Interrupt Vector Table Location </li></ul><ul><li>User-Configurable Interrupt Vector Spacing </li></ul>
  8. 8. Prefetch Cache Prefetch Module Block Diagram <ul><li>16 Fully Associative Lockable Cache Lines </li></ul><ul><li>16-Byte Cache Lines </li></ul><ul><li>Up to Four Cache Lines Allocated to Data </li></ul><ul><li>Two Cache Lines with Address Mask to Hold </li></ul><ul><li>Repeated Instructions </li></ul><ul><li>Pseudo LRU Replacement Policy </li></ul><ul><li>All Cache Lines are Software Writable </li></ul><ul><li>16-Byte Parallel Memory Fetch </li></ul><ul><li>Predictive Instruction Prefetch </li></ul>
  9. 9. Direct Memory Access (DMA) Controller <ul><li>Four Identical Channels, each Featuring Auto-Increment Source and Destination Address registers, Source and Destination Pointers, Memory to memory and memory to peripheral transfers. </li></ul><ul><li>Automatic Word-Size Detection, Fixed Priority Channel Arbitration, Flexible DMA Requests </li></ul><ul><li>Multiple DMA Channel Status Interrupts and CRC Generation Module. </li></ul>
  10. 10. USB On-The-Go (OTG) USB Block Diagram
  11. 11. Comparator Voltage Reference (CVREF) • High and low range selection • Sixteen output levels available for each range • Internally connected to comparators to conserve device pins • Output can be connected to a pin
  12. 12. Ethernet Controller Ethernet Controller Block Diagram
  13. 13. Controller Area Network (CAN) PIC32MX CAN Module Block Diagram
  14. 14. 10-BIT ANALOG-TO-DIGITAL CONVERTER (ADC) <ul><li>Successive Approximation Register (SAR) Conversion </li></ul><ul><li>Up to 1 Msps Conversion Speed and Up to 16 Analog Input Pins </li></ul><ul><li>External Voltage Reference Input Pins </li></ul><ul><li>Automatic Channel Scan mode </li></ul><ul><li>16-word Conversion Result Buffer </li></ul>
  15. 15. Parallel Master Port (PMP) <ul><li>8-Bit, 16-Bit Interface and Up to 16 Programmable Address Lines and Two Chip Select Lines </li></ul><ul><li>Programmable Strobe Options like Individual read and write strobes, or read/write strobe with enable strobe </li></ul><ul><li>Address Auto-Increment/Auto-Decrement, Programmable Address/Data Multiplexing and Programmable Polarity on Control Signals </li></ul>PMP Module Pinout And Connections To External Devices
  16. 16. Universal Asynchronous Receiver Transmitter <ul><li>Full-Duplex, 8-Bit or 9-Bit Data Transmission </li></ul><ul><li>Even, Odd or No Parity Options (for 8-bit data) </li></ul><ul><li>One or Two Stop Bits, Parity, Framing and Buffer Overrun Error Detection </li></ul><ul><li>Hardware Auto-Baud Feature </li></ul><ul><li>Hardware Flow Control Option </li></ul><ul><li>Fully Integrated Baud Rate Generator (BRG) with 16-Bit Prescaler </li></ul><ul><li>Baud Rates Ranging from 76 bps to 20 Mbps at 80 MHz </li></ul><ul><li>8-Level Deep First-In-First-Out (FIFO) Transmit Data Buffer </li></ul>UART Simplified Block Diagram
  17. 17. Input Capture Input Capture Block Diagram <ul><li>Capture timer value on every falling edge of input at ICx pin and every rising edge of input at ICx pin </li></ul><ul><li>Device Wake-up from Capture Pin during CPU Sleep and Idle modes </li></ul><ul><li>Interrupt on Input Capture Event </li></ul><ul><li>4-Word FIFO Buffer for Capture Values. Interrupt Optionally Generated after 1, 2, 3 or 4 and Buffer Locations are Filled </li></ul><ul><li>Input Capture can also be used to Provide and Additional Sources of External Interrupts </li></ul>
  18. 18. Additional Resource <ul><li>For ordering PIC32MX5xx/6xx/7xx , please click the part list or </li></ul><ul><li>Call our sales hotline </li></ul><ul><li>For more product information go to </li></ul><ul><ul><li>http:// www.microchip.com/wwwproducts/Devices.aspx?dDocName =en547140#1 </li></ul></ul><ul><li>Visit Element 14 to post your question </li></ul><ul><ul><li> www.element-14.com </li></ul></ul><ul><li>For additional inquires contact our technical service hotline or even use our “Live Technical Chat” online facility </li></ul>

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