Your SlideShare is downloading. ×
PCM3168A/PCM3168A-Q1 Audio Codec
Upcoming SlideShare
Loading in...5
×

Thanks for flagging this SlideShare!

Oops! An error has occurred.

×
Saving this for later? Get the SlideShare app to save on your phone or tablet. Read anywhere, anytime – even offline.
Text the download link to your phone
Standard text messaging rates apply

PCM3168A/PCM3168A-Q1 Audio Codec

600
views

Published on

To introduce PCM3168A/PCM3168A-Q1 audio codec and their internal operations

To introduce PCM3168A/PCM3168A-Q1 audio codec and their internal operations

Published in: Technology, Business

1 Comment
0 Likes
Statistics
Notes
  • hai
    am venkat , we are planning to work with pcm3168a audio codec,
    i have doubt regarding the set up of pcm3168a .
    1) if i set pcm3168 as master ,how it will generate the 'BCK'
    2)how to set the sampling frequency to '96 khz'
    3) if i give external 'SCK' , then bck will generate automatically r we need to set any register
    4)whether we can use pcm3168a audio codec with blackfin BF548
    5)is there any evaluation kit available?

    specifications:

    24 bit,
    sampling rate - 96KHZ
    Bck - 128*fs
    128 *96
    12.288 MHz

    please replay back as soon as possible.'sachin@eilabs.co.in'
    Thanks and Regards
    venkatesh
       Reply 
    Are you sure you want to  Yes  No
    Your message goes here
  • Be the first to like this

No Downloads
Views
Total Views
600
On Slideshare
0
From Embeds
0
Number of Embeds
1
Actions
Shares
0
Downloads
0
Comments
1
Likes
0
Embeds 0
No embeds

Report content
Flagged as inappropriate Flag as inappropriate
Flag as inappropriate

Select your reason for flagging this presentation as inappropriate.

Cancel
No notes for slide
  • Welcome to the training module on Texas Instrument PCM3168A/PCM3168A-Q1 Audio Codec. This training module introduces PCM3168A/PCM3168A-Q1 audio codec and their internal operations.
  • The PCM3168A and PCM3168A-Q1 are high-performance, 24-bit delta-sigma audio coders/decoders (codecs). The devices employ six-channel, analog-to-digital converters (ADC) and eight-channel digital-to-analog converter (DAC). Each audio interface supports I 2 S, left-justified, right-justified, and DSP formats with 16-bit/24-bit word width. The codecs also support the time-division-multiplexed (TDM) format. These audio codecs can be controlled through a four-wire, SPI-compatible interface, or two-wire, I 2 C-compatible serial interface in software, which provides access to all functions including digital attenuation, soft mute, de-emphasis etc. The hardware control mode provides a subset of user-programmable functions through four control pins. These devices are targeted for automotive audio applications such as external amplifiers, as well as home multi-channel audio applications (for example, home theaters and A/V receivers).
  • As shown in the functional block diagram, the PCM3168A and PCM3168A-Q1 consist of six-channel analog-to-digital converters (ADCs) and eight-channel digital-to-analog converters (DACs). The ADC input is selectable between single-ended and differential inputs. They also include two internal references for the six-channel ADCs. The DAC output type is fixed with a differential configuration. The audio serial port consists of 11 signals including data, clock and control. The PCM3168A and PCM3168A-Q1 has a high-pass filter for all ADC channels in order to remove the DC component of the digitized input signal. The codecs also have many user-programmable functions that are accessed via control registers, and are programmed through the SPI or I 2 C serial control port.
  • The PCM3168A and PCM3168A-Q1 include six ADCs, each with individual pairs of differential voltage input pins. Additionally, both devices have the capability of single-ended inputs. In single-ended mode, VINx+ pins are used and VINx– pins must be terminated with AGNDAD1/2 via a capacitor or terminated with VCOMAD. The full-scale input voltage is (0.2 × VCCAD1) VRMS at the single-ended input mode and (0.4 × VCCAD1) VRMS at the differential input mode. As soon as any of the six-channel ADC digital outputs exceed the full-scale range, an overflow flag is forced high on the OVF pin. Here also list other performance of the ADCs, including total harmonic distortion plus noise (THD+N), dynamic range, sampling rate, etc.
  • The PCM3168A and PCM3168A-Q1 include eight D/A Converters, each with individual pairs of differential voltage input pins. The full-scale output voltage is (1.6 × VCCDA1) VPP in differential mode. DC-coupled loads are allowed in addition to ac-coupled loads if the load resistance conforms to the specification. Here also list other performance of the DACs, including total harmonic distortion plus noise (THD+N), SNR, dynamic range, sampling rate, etc.
  • We will now discuss the sampling modes offered on the codec. The ADC operation supports two sampling modes (single rate and dual rate), and the DAC supports three sampling modes (single rate, dual rate, and quad rate). In single rate mode, the A/D and D/A operate at an oversampling frequency of x128 (except when SCKI = 128 fS and 192 fS). This mode is supported for sampling frequencies less than 50 kHz. In dual rate mode, the ADC and DAC operate at an oversampling frequency of x64; this mode is supported for sampling frequencies less than 100 kHz. In quad rate mode, the DAC operates at an oversampling frequency of x32. The sampling mode is automatically selected according to the ratio of system clock frequency and sampling frequency by default, but manual selection is also possible for specified combinations through the serial mode control resistor.
  • The PCM3168A and PCM3168A-Q1 have both an internal power-on reset circuit and an external reset circuit. In internal power-on reset, the initialization is triggered automatically at the point where VDD exceeds 2.2 V typical, and the internal reset is released after 3846 SCKI clock cycles from power-on if RST is kept high and SCKI is provided. For the external reset, RST accepts an external forced reset to low, and provides a device reset and power-down state that makes the lowest power dissipation state available in the PCM3168A and PCM3168A-Q1.
  • The PCM3168A and PCM3168A-Q1 support eight audio data interface formats for the ADC and DAC separately in both master and slave modes: 24-bit I 2 S, 24-bit left-justified, 24-bit right-justified, 16-bit right-justified, 24-bit left-justified mode DSP, 24-bit I2S mode DSP, 24-bit left-justified mode TDM, and 24-bit I 2 S mode TDM format. They also support two audio data interface formats for the DAC and slave mode: 24-bit left-justified mode high-speed TDM and 24-bit I 2 S mode high-speed TDM format.
  • The PCM3168A and PCM3168A-Q1 include four-way mode control selectable by MODE pin. This allows to select the hardware control / serial control modes with the analog input configuration. The pull-up and pull-down resistors on these pins must be 220 kΩ ±5%. This mode control selection is sampled only when the internal reset is released by a power-on reset or by a low-to-high transition of the external reset (RST pin); a system clock is also required.
  • The PCM3168A and PCM3168A-Q1 include an SPI-compatible serial port that operates asynchronously with the audio serial interface. The control interface consists of MDI/SDA/DEMP, MDO/ADR1/MD1, MC/SCL/FMT, and MS/ADR0/MD0. MDI is the serial data input to program the mode control registers. MDO is the serial data output to read back register settings and some flags. MDO is inactive (Hi-Z, high impedance) during MS = high. MC is the serial bit clock that shifts the data into the control port. MS is the select input to enable the mode control port.
  • The audio codecs support an I 2 C-compatible serial bus and data transmission protocol for fast mode configured as a slave device. A master device must control the packet protocol, which consists of the start condition, slave address with the read/write bit, data - if a write operation is required, acknowledgement - if a read operation is required, and stop condition. The PCM3168A and PCM3168A-Q1 support both slave receiver and transmitter functions. In receiver function, a master device can write to any of the chips registers using single or multiple accesses. The master sends a slave address with a write bit, a register address, and the data. As a transmitter, a master device can read the registers from &h40 to &h5E of the devices.
  • Before concluding the presentation, we would like to highlight key design considerations to ensure better performance.
  • Thank you for taking the time to view this presentation on “ PCM3168A/PCM3168A-Q1 Audio Codec” . If you would like to learn more or go on to purchase some of these devices, you may either click on the part list link, or simply call our sales hotline. For more technical information you may either visit the TI site – link shown – or if you would prefer to speak to someone, please call our hotline number, or even use our online ‘live chat’ facility.
  • Transcript

    • 1. PCM3168A/PCM3168A-Q1 Audio Codec
      • Source: T EXAS I NSTRUMENTS
    • 2. Introduction
      • Purpose
        • This training module introduces PCM3168A/PCM3168A-Q1 audio codec and their internal operations.
      • Outline
        • Overview the devices
        • Functional block diagram
        • Internal operations
        • Design considerations
      • Content
        • 14 pages
    • 3. Overview of PCM3168A
      • 24-bit delta-sigma ( ΔΣ ) ADC and DAC
      • 6-channel high performance ADC
      • 8-channel high performance DAC
      • Four-Wire SPI, Two-Wire I 2 C Compatible Serial Control Interface or Hardware Control
      • External reset pin
      • ADC/DAC independent master/slave
      • Audio data format: ADC/DAC Independent I 2 S, Left-Justified, Right-Justified, DSP, TDM
      • Applications:
        • Car audio external amplifiers
        • Car audio AVN applications
        • Home theaters
        • AV receivers
    • 4. Functional Block Diagram Audio Serial Interface & Clock control Mode Control Port (SPI/I 2 C) Common & Reference Digital Filter & Volume Digital Filter & Volume
    • 5. Six ADCs
      • High Performance: Differential and Single-Ended, f S = 48 kHz
      • THD+N: -93 dB (Differential), -93 dB (Single-Ended)
      • SNR: 107 dB (Differential), 104 dB (Single-Ended)
      • Dynamic Range: 107 dB (Differential), 104 dB (Single-Ended)
      • Sampling Rate: 8 kHz to 96 kHz
      • System Clock: 256 f S , 384 f S , 512 f S , 768 f S
      • Differential Voltage Input: 2 V RMS
      • Single-Ended Voltage Input: 1 V RMS
      • Decimation Filter:
        • Passband Ripple: ±0.035 dB
        • Stop Band Attenuation: -75 dB
      • On-Chip, High-Pass Filter: 0.96 Hz at fS = 48 kHz
      • Overflow Flag
      Typical interface circuits for analog input VIN6+ VIN6+, VIN6– 6 (ADC6) VIN5+ VIN5+, VIN5– 5 (ADC5) VIN4+ VIN4+, VIN4– 4 (ADC4) VIN3+ VIN3+, VIN3– 3 (ADC3) VIN2+ VIN2+, VIN2– 2 (ADC2) VIN1+ VIN1+, VIN1– 1 (ADC1) SINGLE-ENDED INPUT MODE DIFFERENTIAL INPUT MODE CHANNEL
    • 6. Eight DACs
      • High Performance: Differential, f S = 48 kHz
      • THD+N: -94 dB
      • SNR: 112 dB
      • Dynamic Range: 112 dB
      • Sampling Rate: 8 kHz to 192 kHz
      • System Clock: 128 f S , 192 f S , 256 f S , 384 f S , 512 f S , 768 f S
      • Differential Voltage Output: 8 VPP
      • Analog Low-Pass Filter Included
      • 4x/8x Oversampling Digital Filter
        • Passband Ripple: ±0.0018 dB
        • Stop Band Attenuation: -75 dB
      • Zero Flag
      Differential to Single-Ended Buffer for DAC Output (AC-Coupled) Differential to Single-Ended Buffer for DAC Output (DC-Coupled)
    • 7. Sampling Mode
      • Single rate mode
        • The ADC and DAC operate at an oversampling frequency of x128;
        • It is supported for sampling frequencies less than 50 kHz.
      • Dual rate mode
        • The ADC and DAC operate at an oversampling frequency of x64;
        • It is supported for sampling frequencies less than 100 kHz.
      • Quad rate mode
        • The DAC operates at an oversampling frequency of x32.
    • 8. Reset Operation Internal Power-On-Reset External Reset
    • 9. Audio Interface Formats
    • 10. Mode Control
      • MODE pin tied to DGND
        • Two-wire (I2C) serial control, selectable analog input configuration
      • MODE pin tied to DGND via pull-down resistor
        • Hardware control, differential analog input
      • MODE pin tied to VDD via pull-up resistor
        • Hardware control, single-ended analog input
      • MODE pin tied to VDD
        • Four-wire (SPI) serial control, selectable analog input configuration
    • 11. SPI Serial Control
      • All single write/read operations via SPI serial control port use 16-bit data words.
      • MDI is the serial data input to program the mode control registers
      • MDO is the serial data output to read back register settings and some flags
      • MDO is inactive during MS = high
      • MC is the serial bit clock that shifts the data into the control port
    • 12. I 2 C Serial Control
      • The PCM3168A and PCM3168A-Q1 support an I 2 C-compatible serial bus and data transmission protocol for fast mode configured as a slave device.
      • They have a 7-bit slave address.
      • They support both slave receiver and transmitter functions.
        • As a receiver, a master device can write to any PCM3168A and PCM3168A-Q1 register using single or multiple accesses.
        • As a transmitter, a master device can read the registers from &h40 to &h5E of the devices.
    • 13. Design Considerations
      • The digital and analog power-supply pins should be bypassed to the corresponding ground pins with 1-mF ceramic capacitors placed as close to the pins as possible.
      • To maximize the dynamic performance, the analog and digital grounds are not connected internally.
      • 10- µ F electrolytic capacitors are recommended between VCOMAD and AGNDAD to ensure a low source impedance of ADC and DAC common voltages
      • 10- µ F electrolytic capacitors are recommended between VREFAD1/2 and AGNDAD to ensure low source impedances of ADC references
    • 14. Additional Resource
      • For ordering PCM3168A/PCM3168A-Q1, please click the part list or
      • Call our sales hotline
      • For additional inquires contact our technical service hotline
      • For more product information go to
        • http://focus.ti.com/docs/prod/folders/print/pcm3168a.html