Welcome to the training module on MPC 854X device. This training module introduces the features of e500 Core and supporting devices, its peripheral functions incorporated in this device.
Key features include256KB L2 cache, integrated security, 64-bit DDR1/2 scaling up to 400 MHz data rate, 32-bit PCI, 4-bit Serial RapidIO or 4-bit PCI Express, and two Gigabit Ethernet interfaces. With clock frequencies scaling from 800 MHz to 1 GHz, this cost-effective device is ideally suited for a wide range of general-purpose embedded control applications, such as robotics, discrete manufacturing and process manufacturing control.
The processors are designed to offer clock speeds scaling up to 1.333 GHz with headroom for 1.5 GHz. They combine the powerful processor core, enhanced peripherals and high-speed interconnect technology to balance processor performance with I/O system throughput. processors offer a wide range of high-speed connectivity options, including Gigabit Ethernet, Serial RapidIO® technology and PCI Express. Support for these high-speed interfaces enables scalable connectivity to network processors and/or ASICs in the data plane while the PowerQUICC III handles complex, computationally demanding control plane processing tasks. These processors also feature next-generation double data rate (DDRII) memory controller, enhanced, Gigabit Ethernet support, double precision floating point and integrated security engines that support the Kasumi algorithm needed 3G wireless security.
Here is a block diagram of the processor core complex that shows how the functional units operate independently and in parallel. The e500 processor core is a low-power implementation of the family of reduced instruction set computing (RISC) embedded processors that implement the Book E definition of the PowerPC architecture. The e500 is a 32-bit implementation of the Book E architecture using the lower words in the 64-bit general-purpose registers (GPRs).
The MPC8548E contains an internal 512-Kbyte memory array that can be configured as memory-mapped SRAM or as a look-aside L2 cache. The array can also be divided into two arrays, one of which may be used as cache and the other as SRAM. The memory controller for this array connects to the core complex bus (CCB) and communicates via 128-bit read and write buses to the e500 core and the MPC8548E system logic.
Memory controller signals are grouped as Memory interface signals, Clock signals, Debug signals. Signals is organized into the following sections: • Overview of signals and cross-references for signals that serve multiple functions, including two lists: one by functional block and one alphabetical • List of reset configuration signals • List of output signal states at reset
The MPC8548E takes a single input clock, SYSCLK, as its primary clock source for the e500 core and all of the devices and interfaces that operate synchronously with the core. The SYSCLK input (frequency) is multiplied up using a phase lock loop (PLL) to create the core complex bus (CCB) clock (also called the platform clock). The CCB clock is used by virtually all of the synchronous system logic, including the L2 cache, and other internal blocks such as the DMA and interrupt controller. The CCB clock also feeds the PLL in the e500 core and the PLL that create clocks for the local bus memory controller
The e500 core complex supports demand-paged virtual memory as well other memory management schemes that depend on precise control of effective-to-physical address translation and flexible memory protection as defined by the architecture. The mapping mechanism consists of software-managed TLBs that support variable-sized pages with per-page properties and permissions.
The integrated 512-Kbyte L2 cache is organized as 2048 eight-way sets of 32-byte cache lines based on 36-bit physical addresses The SRAM can be configured with memory-mapped registers as externally accessible memory-mapped SRAM in addition to or instead of cache.
The fully programmable DDR SDRAM controller supports most JEDEC standard x8, x16, or x32 DDR and DDR2 memories available. In addition, unbuffered and registered DIMMs are supported. mixing different memory types or unbuffered and registered DIMMs in the same system is not supported. Built-in error checking and correction (ECC) ensures very low bit-error rates for reliable high-frequency operation. Dynamic power management and auto-precharge modes simplify memory system design. A large set of special features, including ECC error injection, support rapid system debug.
The PIC prioritizes and manages interrupts directed to the int signal. It also manages the interrupts generated by the PIC itself and by off-chip interrupt sources. The PIC is compliant with the OpenPIC architecture. The interrupt controller provides interrupt management, and is responsible for receiving hardware-generated interrupts from different sources, prioritizing them, and delivering them to the CPU for servicing. The PIC receives interrupt signals from three sources: external to the integrated device, internal to the integrated device, and intrinsic to the PIC itself.
The two-wire I2C bus minimizes interconnections between devices. The synchronous, multiple-master I2C bus allows the connection of additional devices to the bus for expansion and system development. The bus includes collision detection and arbitration that prevent data corruption if two or more masters attempt to control the bus simultaneously.
The DUART consists of two universal asynchronous receiver/transmitters (UARTs). The UARTs act independently; all references to UART refer to one of these receiver/transmitters. Each UART is clocked by the core complex bus (CCB) clock. The DUART programming model is compatible with the PC16552D. The UART interface is point to point, meaning that only two UART devices are attached to the connecting signals.
The PCI Express controller provides the mechanism to communicate with PCI Express devices. The PCI Express controller connects the internal platform to a 2.5-GHz serial interface. MPC8548E offers up to a x8 interface link. As both an initiator and a target device, the PCI Express interface is capable of high-bandwidth data transfer and is designed to support next generation I/O devices. Upon coming out of reset, the PCI Express interface performs link width negotiation and exchanges flow control credits with its link partner. Once link auto negotiation is successful, the controller is in operation.
A block diagram of the integrated security engine’s internal architecture is shown here. The SEC is a modular and scalable security core optimized to process all the algorithms associated with IPSec, IKE, WTLS/WAP, SSL/TLS, and 3GPP. it is not a protocol processor, the SEC is designed to perform multi-algorithmic operations in a single pass of the data, The bus interface module is designed to transfer 64-bit words between the internal bus and any register inside the SEC.
The MPC8548E serial RapidIO controller consists of a RapidIO endpoint and the RapidIO messaging unit (RMU). The serial RapidIO interface provides a RapidIO port and message unit to communicate with other RapidIO devices. RapidIO endpoint supports Nine outbound ATMU windows with each window having up to 32 sub windows except the default Window, Five inbound ATMU windows, Logical outbound packet time-to-live counter to prevent local processor from hanging when the RIO interface fails.
The PCI/X controller acts as a bridge between the PCI/X interface and the OCeaN switch fabric. The PCI/X controller connects the OCeaN to the PCI bus, to which I/O components are connected. The PCI bus uses a 32- or 64-bit multiplexed address/data bus, plus various control and error signals. The PCI/X interface supports address and data parity with error checking and reporting. The integrated processor’s PCI/X interface functions both as a master (initiator) and a target device.
The DMA controller has four high-speed DMA channels. Both the e500 core and external devices can initiate DMA transfers. All channels are capable of complex data movement and advanced transaction chaining. Operations such as descriptor fetches and block transfers are initiated by each channel. A channel is selected by the arbitration logic and information is passed to the source and destination control blocks for processing. The source and destination blocks generate read and write requests to the address tenure engine, which manages the DMA master port address interface.
The enhanced three-speed Ethernet controllers (eTSECs) of the device interface to 10 Mbps, 100 Mbps, and 1 Gbps Ethernet/IEEE 802.3 networks and devices featuring generic 8-16-bit FIFO ports. For Ethernet, an external PHY or SerDes device is required to complete the interface to the media. Each eTSEC supports multiple standard media-independent interfaces, of which the FIFO interface bypasses the Ethernet MAC. Four eTSECs are available, providing flexible options for connectivity and control access at different speeds.
The MPC8548E is a very flexible device and can be configured to meet many system application needs. In order to build a system, many factors should be considered. The MPC8548E can be used for control processing in applications such as routers, switches, internet access devices, firewall and other packet filtering processors, network attached storage, storage area networks, imaging, and general-purpose embedded computing. Here illustrates is the MPC8548E in a virtual private network (VPN) access router that is enabled through PCI Express and Ethernet. It shows the MPC8548E in a redundant array of independent disks (RAID) controller application.
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MPC854XE: PowerQUICC III Processors <ul><li>Source: Freescale Semiconductor </li></ul>
Introduction <ul><li>Purpose </li></ul><ul><ul><li>An overview study on PowerQUICC III Processors </li></ul></ul><ul><li>Outline </li></ul><ul><ul><li>Key Features and Block Diagram. </li></ul></ul><ul><ul><li>E500 Core Block Diagram, on-chip Memory, Memory Management. </li></ul></ul><ul><ul><li>Programmable interrupt controller, I2C Interface, DUART </li></ul></ul><ul><ul><li>PCI Express, Integrated Security Engine. </li></ul></ul><ul><ul><li>DMA Controller, Ethernet Controller. </li></ul></ul><ul><ul><li>Application circuit. </li></ul></ul><ul><li>Content </li></ul><ul><ul><li>22 pages </li></ul></ul>
Key Features <ul><li>Based on the scalable e500 system-on-chip (SoC) platform and processor core built on Power Architecture technology, the MPC8548/E PowerQUICC III processor delivers performance and features. </li></ul><ul><li>512-Kbyte L2 cache/SRAM. </li></ul><ul><li>Address translation and mapping unit (ATMU). </li></ul><ul><li>DDR/DDR2 memory controller. </li></ul><ul><li>Programmable interrupt controller (PIC). </li></ul><ul><li>Integrated security engine (SEC) optimized to process all the algorithms associated with IPSec, IKE, WTLS/WAP, SSL/TLS, and 3GPP. </li></ul><ul><li>Dual I2C controllers, Boot sequencer, DUART, Local bus controller (LBC). </li></ul><ul><li>Four enhanced three-speed Ethernet controllers (eTSECs). </li></ul><ul><li>Four Integrated DMA controller. </li></ul><ul><li>Two PCI/PCI-X controllers, Serial RapidIO™ interface unit. </li></ul><ul><li>PCI Express 1.0a compatible: Supports ×8, ×4, ×2, and ×1 link widths. </li></ul>
MPC8548E Block Diagram MPC8548E Block Diagram
e500 Core Complex Block Diagram e500 Core
On-Chip Memory Unit <ul><li>512 Kbytes of on-chip memory. </li></ul><ul><li>L2 cache partitioning is configurable. </li></ul><ul><li>SRAM operation is byte-accessible. </li></ul><ul><li>Data ECC on 64-bit boundaries (single-error correction, double-error detection). </li></ul><ul><li>Tag parity (1 bit covering all tag bits). </li></ul><ul><li>Cache mode supports instruction caching, data caching, or both. </li></ul><ul><li>External masters can force data to be allocated into the cache through programmed memory ranges or special transaction types. </li></ul><ul><li>Separate locking for instructions and data so that locks can be set and cleared separately. </li></ul><ul><li>Supports locking the entire cache or selected lines. </li></ul><ul><li>Flash clearing done through writes to L2 configuration registers. </li></ul><ul><li>Locks for the entire cache may be set and cleared by accesses to memory-mapped control registers. </li></ul>
Memory Management <ul><li>32-bit effective address translated to 32-bit real address for the e500v1core and 36-bit real addressing for the e500v2 core. </li></ul><ul><li>16-entry, fully-associative TLB array for variable-sized pages </li></ul><ul><li>TLB entries for variable- (4-Kbyte–256-Mbyte, 4-Kbyte–4-Gbyte pages and fixed-size (4-Kbyte) pages. </li></ul><ul><li>4-entry, fully-associative TLB array for variable-sized pages </li></ul><ul><li>64-entry, 4-way set-associative TLB for 4-Kbyte pages </li></ul>MMU Structure
L2 Look-Aside Cache/SRAM <ul><li>Full cache mode (512-Kbyte cache). </li></ul><ul><li>Full memory-mapped SRAM mode (512-Kbyte SRAM mapped as a single 512-Kbyte block or two 256-Kbyte blocks) </li></ul><ul><li>Partial SRAM and partial cache mode, in which one eighth, one quarter, or one half the total on-chip memory can be allocated to 1 or 2 SRAM regions. </li></ul>L2 Cache/SRAM Configuration
DDR Memory Controller <ul><li>Dynamic power management mode: </li></ul><ul><li>The DDR memory controller can reduce power consumption by negating the SDRAM CKE signal when no transactions are pending to the SDRAM. </li></ul><ul><li>Auto-precharge mode: </li></ul><ul><li>Clearing DDR_SDRAM_INTERVAL [BSTOPRE] causes the memory controller to issue an auto-precharge command with every read or write transaction. </li></ul><ul><li>Auto-precharge mode can be enabled for separate chip selects by setting CS n _CONFIG[AP_ n _EN]. </li></ul>DDR Memory Controller Block Diagram
Programmable Interrupt Controller <ul><li>Programming model compliant with the OpenPIC architecture </li></ul><ul><li>Support for 12 external and 48 internal interrupt sources. Serial interrupts are not supported. </li></ul><ul><li>Four interprocessor interrupt channels, Four 32-bit messaging interrupt channels. </li></ul><ul><li>Eight shared message signalled interrupt sources and up to 32 sharers for shared interrupt register. </li></ul><ul><li>Four global high-resolution timers that can be clocked with the platform clock or the RTC input. </li></ul><ul><li>Fully-nested interrupt delivery, Processor initialization control. </li></ul><ul><li>Programmable resetting of the PIC unit through the global configuration register </li></ul><ul><li>16 programmable interrupt priority levels </li></ul><ul><li>Support for connection of external interrupt controller device such as an 8259 programmable interrupt controller </li></ul><ul><li>Recovery from spurious interrupts </li></ul>
I2C Interfaces <ul><li>Two-wire interface </li></ul><ul><li>Multiple-master operation </li></ul><ul><li>Arbitration lost interrupt with automatic mode switching from master to slave </li></ul><ul><li>Calling address identification interrupt, Bus busy detection. </li></ul><ul><li>START and STOP signal generation/detection </li></ul><ul><li>Acknowledge bit generation / detection. </li></ul><ul><li>Software-programmable clock frequency </li></ul><ul><li>Software-selectable acknowledge bit </li></ul><ul><li>On-chip filtering for spikes on the bus </li></ul>
DUART UART Block Diagram • Receive and transmit buffers. • Clear to send (CTS) input port and request to send (RTS) output port for data flow control. • 16-bit counter for baud rate generation. • Interrupt control logic.
PCI Express Interface Controller PCI Express Controller Block Diagram <ul><li>Complies with the PCI Express Base Specification, Revision 1.0a. </li></ul><ul><li>Supports root complex (RC) and endpoint (EP) configurations. </li></ul><ul><li>32- and 64-bit address support. </li></ul><ul><li>x8, x4, x2, and x1 link support. </li></ul><ul><li>Supports posting of processor-to-PCI Express and PCI Express-to-memory writes. </li></ul><ul><li>Supports strong and relaxed transaction ordering rules. </li></ul><ul><li>Baseline and advanced error reporting support. </li></ul><ul><li>One virtual channel (VC0). </li></ul><ul><li>256-byte maximum payload size. </li></ul><ul><li>Supports three inbound general-purpose translation windows and one configuration window. </li></ul>
Integrated Security Engine (SEC) Integrated Security Engine Functional Blocks <ul><li>An operation begins with a write of a pointer to a crypto-channel fetch register that points to a data packet descriptor. </li></ul><ul><li>The channel requests the descriptor and decodes the operation to be performed. </li></ul><ul><li>The controller satisfies the requests by assigning execution units to the channel and by making requests to the master interface. </li></ul>
Serial RapidIO Interface RapidIO Endpoint and RMU <ul><li>Small or large size transport information field </li></ul><ul><li>34-bit addressing </li></ul><ul><li>Up to 256-byte data payload </li></ul><ul><li>Up to eight outstanding unacknowledged RapidIO transactions </li></ul><ul><li>Hardware recovery only </li></ul><ul><li>All transaction flows and all priorities </li></ul>
PCI/PCI-X Bus Interface PCI/X Controller Block Diagram <ul><li>PCI-X rev 1.0a compatible. </li></ul><ul><li>Support for up to 133-MHz point-to-point connection. </li></ul><ul><li>Support for 32- and 64-bit interface. </li></ul><ul><li>64-bit dual address cycle (DAC) support. </li></ul><ul><li>On-chip arbitration with support for five high-priority request and grant signal pairs. </li></ul><ul><li>Support for accesses to all PCI-X memory and I/O address spaces. </li></ul><ul><li>Support for four split transactions. </li></ul><ul><li>Complete allowable disconnect boundary (ADB) support. </li></ul><ul><li>All PCI-X ordering rules enforced. </li></ul><ul><li>Implementation of relaxed ordering. </li></ul><ul><li>PCI-X 3.3-V compatible. </li></ul>
DMA Controller <ul><li>Four high-speed/high-bandwidth channels accessible by local and remote masters </li></ul><ul><li>Basic DMA operation modes (direct, simple chaining) </li></ul><ul><li>Extended DMA operation modes (advanced chaining and stride capability) </li></ul><ul><li>Cascading descriptor chains </li></ul><ul><li>Misaligned transfers </li></ul><ul><li>Programmable bandwidth control between channels </li></ul><ul><li>Up to 256 bytes for DMA sub-block transfers to maximize performance </li></ul><ul><li>Three priority levels supported for source and destination transactions </li></ul><ul><li>Interrupt on error and completed segment, list, or link </li></ul>
MPC8548E Applications VPN Access Router Enabled by PCI Express and Ethernet RAID Controller Application Using MPC8548E
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