Welcome to the training module on Freescale MPC8313E PowerQUICC II Pro Processor. This training module will provide an overwiew on the features and specifications of MPC8313E.
The Freescale MPC8313E is an ideal lower power processor for power and security needs, digital media servers, consumer network-attached storage, office, and industrial applications. This processor provides more CPU performance, additional functionality, and faster interfaces while addressing important time to market, power consumption, and board real estate requirements.
The MPC8313E incorporates a unique configuration of the e300 core supporting up to 333MHz speed with up to around 700 MIPS CPU performance. The L1 instruction data caches and on-chip memory management units (MMUs) support up to 16 KB of memory. High speed communications supports upto Gigabit Ethernet (SGMII) and high speed USB 2.0. The security engine provides hardware acceleration for the DES, 2DES, Advanced Encryption Standard (AES), Secure Hash Algorithm (SHA)-1 and MD-5 algorithms. This processor supports boot options via NOR,NAND flash, CF or MMC. The IEEE 1588 standard for Precision Clock Synchronization Protocol for Networked Measurement and Control Systems defines a message-based protocol. The MPC8313E also features a DDR1/DDR2 SDRAM memory controller (which introduces a 32-bit double data rate). The MPC8313E has a low power requirement of less than 1.5W at 333MHz in addition to fan-less operation, wake-on-LAN, wake-on-USB, wake-on-PME, and a wake-on-external signal support.
Traditional physical interfaces use RGMII or GMII designs with a parallel line interface between GigE MAC and PHY. These interfaces utilize 25 traces running at 125MHz or 12 traces at 250MHz, respectively. With the new Serial GMII (SGMII) interface, parallel connections can be shifted to serial allowing for longer connections and eliminating the need for synchronized signaling. This SGMII format uses 4 or 8 traces that all run at 1.25GHz, giving a 4x performance increase over traditional PHYs. Additionally, the Low Voltage Differential Signaling (LVDS) format greatly improves signal integrity.
IEEE 1588 support in the MPC8313E enables accurate synchronization of clocks with varying precision, resolution, and oscillator stability in distributed systems. It enhances applications that need local clocks at each control node and provides sub-microsecond synchronization over long distances using standard cabling. The hardware assist features that are available with the MPC8313E processor include RX and TX timestamp capture close to the physical interface which reduces stack jitter and improves clock synchronization accuracy. Every RX packet and only necessary TX packets are time stamped. Also, the flexible clocking options support both low cost and high accuracy designs with an on-chip clock and an external oscillator while the phase and frequency compensation circuitry enables slave clock recovery.
Utilizing flexible recognition of PTP (Precision Time Protocol) frames allows for detecting and reporting reception of PTP frames and extensibility for future protocol changes and updates including IPV6 support. The external signal interfaces include two trigger input signals, two alarm output signals, three phase-aligned programmable timer output pulse signals (PPS), and a phase aligned output clock. These clocks are defined by a Best Master Clock (BMC) algorithm in which each clock in a distributed system identifies the most accurate clock and labels it ‘master’. All other ‘slave’ clocks synchronize to this master using time stamps. Hardware implementation allows real-time synchronization with nanosecond or sub nanosecond synchronization accuracy allowing for redundant channels and switch/router implementations. Also, the software included with this product can be used to implement a full source- or sink- capable IEEE 1588-compliant Ethernet code.
The integrated security engine (SEC 2.2) in the MPC8313E is designed to off-load computationally intensive security functions, such as authentication, and bulk encryption from the processor core of the MPC8313E. It is optimized to process all the algorithms associated with IPSec, SSL/TLS, iSCSI, SRTP, and 802.11i. The SEC can act as a master on the internal system bus to allow the SEC to off-load the data movement bottleneck normally associated with slave-only cores. The host processor accesses the SEC through its device drivers using system memory for data storage. The security engine contains one crypto-channel, a controller, and a set of crypto execution units (EUs).
The power consumption of the MPC8313E processor, shown at the top of this page, is organized by power state. D0 is the normal operation state where power is supplied to the entire chip. The D1 state is similar to standby and runs with the e300 core in doze mode. In this state, most functional units are disabled as well as memory and I/O accesses while snooping remains active. The D2 state puts the e300 core in nap mode where the chip runs on reduced power but the PLLs are still running and snooping logic is disabled. The D3 (hot) state occurs with the e300 core in a sleep mode where the PLL is not running but 1V VDD is still applied to the entire chip. A soft reset enables the return to D0 state from this state. Also, if PME is enabled, context must be maintained. Specific to the 8313 family, the D3 (warm) state runs with VDD removed from a portion of the die. The final state is the D3 (cold) state with full power down. When power is restored to the chip, it must go through the normal Power-On Reset (POR).
This chart shows power consumption in low power modes plotted against temperature at 333/167 MHz Core/CSB - Coherent System Bus . As can be seen here, total power consumption is reduced as temperature is reduced.
DDR2 provides numerous benefits over DDR1 memories. In addition to faster speeds which lead to higher performance (higher bandwidth), DDR2 consumes less power due to the lower voltages required for the memories. Also, DDR2 eliminates on board termination resistor requirements through the use of on chip termination. This decreases board space and improves signal integrity. The graph here shows that one 1GB SODIMM DDR2 memory running at 533Mbps can save ~56% power consumption over a similar DDR1 memory running at 400Mbps.
Now let us take a look at the development and application support provided by FreeScale for the MPC8313E. The MPC8313E Reference Design Board (RDB) includes a printed circuit board (PCB) assembly plus a software board support package (BSP) distributed in a CD image. Development environments include support for general purpose embedded or industrial applications, media servers, residential gateways, and WLAN access points. The beta release of the CodeWarrior 8.8 Development Tools Suite is available now on the Freescale CodeWarrior website.
The diagram illustrates how the MPC8313E can perform the function of the CPU + interface ASIC on a low-end printer application. In this application, the CPU interfaces to the main ASIC through the high-bandwidth PCI bus. Low-end multi-function printers (MFPs) are able to share the same platform simply by adding a scanner/fax engine. The interface ASIC provides the various network interfaces that are used to access the printer. Image data coming through the scanner or fax interface is sent to the main ASIC, which processes the image by implementing algorithms for image compression/decompression and rendering. The image data is then processed in the FPU in the CPU core at high speeds and sent to the printer engine. Required networking interfaces including USB, PCI, and Gigabit Ethernet are integrated on the MPC8313E, allowing for the CPU and interface ASIC to be consolidated in one device. At the same time, the system is required to consume low power. The MPC8313E provides several power management methods to reduce power consumption.
The diagrams illustrate how an industrial control application is able to take advantage of the IEEE 1588 feature of MPC8313E. As shown, on the top of the slide, IEEE 1588 allows precision control over a distributed Ethernet network. Precise timing delivery allows drive units to be placed where required. In the bottom of the figure, timing synchronization at the drive enables flexibility in system configuration. Issues due to mismatched cable lengths are minimized. Servos can be added or deleted without having to rewire other servos. Industrial control applications typically augment IEEE 1588 hardware to provide trigger inputs and outputs.
In summary, we would like to emphasize that the MPC8313E PowerQUICC II Pro processor is a highly integrated device which thereby reduces the need for additional components and design time. The Power Architecture has low heat generation and extended temperature ranges for fanless operation. The MPC8313E power management supports the ACPI 3.0 specification for low standby power. Freescale’s extensive family of tools help get designs to market quickly and is scalable across the PowerQUICC family.
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The security engine’s execution units (EUs) and primary features include:
Data encryption standard execution unit (DEU), supporting DES and 3DES
Advanced encryption standard unit (AESU), supporting AES
Message digest execution unit (MDEU), supporting MD5, SHA1, SHA-224, SHA-256, and HMAC with any algorithm
One crypto-channel supporting multi-command descriptor chains
Power Consumption MPC8313 0.452527744 192.675 183.5 0.545357524 107.31 102.2 D3 warm 0.901111111 425.775 405.5 0.671203438 196.77 187.4 D3 hot 0.916496945 472.5 450 0.928809049 293.16 279.2 D2 515.55 491 315.63 300.6 D1 Maximum - compared to previous D mode Maximum (FFF) - hot temp, mW Maximum (FFF) - hot temp, mA Typical - compared to previous D mode Typical (Nom) - room temp, mW Typical (Nom) -room temp, mA Core/CSB 333/167 VDD/VDDC = 1.05 V Tj = 105 deg C Ta = 104.3 deg C (101.3 + 3 deg guardband) Hot Temp Conditions VDD/VDDC = 1.05 V Ta = 25 deg C Room Temp Conditions Full power down state. When power is restored, 8313 must go through normal POR. D3 cold VDD removed from a portion of the die (e300, DDR, eLBC, PIC) D3 warm (8313 specific) e300 in sleep mode. Its PLL not running. 1-V VDD still applied to the whole chip. Able to return to D0 with a soft reset. If PME enabled, context must be maintained. D3 hot e300 in nap mode. Reduced power, Snooping logic disabled. PLLs still running. D2 e300 in doze mode. Most functional units disabled. Memory and I/O accesses disabled. Snooping active. D1 Power on for the entire chip D0 Description Power State
Saving Power with DDR2 vs. DDR1 DDR2 Can Save > 50% Power Consumption as compared to DDR1 50% reduction in size FBGA TSOP Package Size Improved Signal Integrity / Less Board Space / Power On-Die Termination Discrete Resistors Termination Lower Power Consumption 1.8V 2.5V VDD/VDDq Higher Performance 266/333Mbps 266/333Mbps Data rate/pin Advantage DDR2 DDR1