• Save
MCF5223x: Integrated ColdFire V2 Ethernet Microcontrollers
Upcoming SlideShare
Loading in...5
×
 

MCF5223x: Integrated ColdFire V2 Ethernet Microcontrollers

on

  • 991 views

Overview of MCF5223x Ethernet Microcontrollers

Overview of MCF5223x Ethernet Microcontrollers

Statistics

Views

Total Views
991
Views on SlideShare
991
Embed Views
0

Actions

Likes
0
Downloads
0
Comments
0

0 Embeds 0

No embeds

Accessibility

Categories

Upload Details

Uploaded via as Microsoft PowerPoint

Usage Rights

© All Rights Reserved

Report content

Flagged as inappropriate Flag as inappropriate
Flag as inappropriate

Select your reason for flagging this presentation as inappropriate.

Cancel
  • Full Name Full Name Comment goes here.
    Are you sure you want to
    Your message goes here
    Processing…
Post Comment
Edit your comment
  • Welcome to the training module on Freescale MCF5223X: Integrated ColdFire V2 Ethernet Microcontrollers. This training module provides an overview of MCF5223x Ethernet Microcontrollers.
  • The MCF5223x family of 68K/ColdFire devices are single-chip solutions that provide 32-bit control with an Ethernet interface. It combines a 10/100 Fast Ethernet Controller (FEC) and Ethernet Physical Layer (EPHY)  with the Version 2 ColdFire core for exceptional performance at a reasonable cost. The MCF5223x embedded controller provides the designer with the right set of peripherals and memory size for a compact Ethernet-enabled platform that cuts development time and cost to help your products get to market quicker.
  • The MCF5223x family integrates standard ColdFire peripherals, including three universal asynchronous receiver/transmitters (UARTs) for medium and long distance connections, an inter-integrated circuit (I2C) and a queued serial peripheral interface (QSPI) for in-system communications to connected peripherals. On-chip memories connected tightly to the processor core include up to 256 Kbytes of Flash and 32 Kbytes of static random access memory (SRAM).
  • Connecting 32-bit controlled applications in the industrial, commercial and consumer markets is fast becoming a necessity rather than an option. Many new applications, such as remote data collection, home automation and networked appliances, require secure, high-performance connectivity at an economical price. To help ensure secure connectivity, the MCF5223x family of ColdFire devices are single-chip solutions that provide 32-bit control with an Ethernet interface for these applications.
  • Here shows the comparison of different members of MCF5223X family. MCF52230/1/2 features 128 KB of embedded flash memory, 32 KB of SRAM, 80 LQFP, 112 LQFP (MCF52230 and MCF52231 only). MCF52233/6 features 256 KB of embedded flash memory, 32 KB of SRAM, 80 LQFP, 112 LQFP (MCF52233 only). MCF52234/5 features 256 KB of embedded flash memory, 32 KB of SRAM, 112 LQFP, 121 MAPBGA.
  • Here shows the blcok diagram of MCF5223x family. All family members are pin-to-pin compatible within the MCF5223x family (in like packages). MCF52231 adds a CAN module, MCF52233 adds 128k bytes of Flash, MCF52234 adds CAN module and 128k bytes of Flash, and MCF52235 adds a Cryptographic Acceleration Unit, a CAN module, and 128k bytes of Flash to the standard MCF5223x peripheral set. The MCF5223x family integrates standard ColdFire peripherals, including three universal asynchronous receiver/transmitters (UARTs) for medium and long distance connections, an inter-integrated circuit (I2C) and a queued serial peripheral interface (QSPI) for in-system communications to connected peripherals.
  • The V2 ColdFire core is implemented using a semi-custom, standard cell-based design methodology. The resulting integrated processor allows significant reductions in component count, power consumption, board space, and cost, resulting in higher system reliability and performance. The ColdFire micro architecture and design includes exceptional integration capabilities by using 100% synthesized design, compiled memories, a hierarchical on-chip bus structure, and industry-leading debug modules. The processor core is comprised of two separate pipelines that are decoupled by an instruction buffer. The two stage Instruction Fetch Pipeline (IFP) is responsible for instruction-address generation and instruction fetch. The instruction buffer is a first-in-first-out (FIFO) buffer that holds prefetched instructions awaiting execution in the Operand Execution Pipeline (OEP). The OEP includes two pipeline stages. The first stage decodes instructions and selects operands; the second stage performs instruction execution and calculates operand effective addresses, if needed.
  • The EMAC design provides a set of DSP operations that can improve the performance of embedded code while supporting the integer multiply instructions of baseline ColdFire architecture. The ColdFire family supports two MAC implementations with different performance levels and capabilities. The original MAC features a three-stage execution pipeline optimized for 16-bit operands, with a 16x16 multiply array and a single 32-bit accumulator. The EMAC features a four-stage pipeline optimized for 32-bit operands, with a fully pipelined 32 × 32 multiply array and four 48-bit accumulators.
  • The MAC unit is integrated into the Operand Execution Pipeline (OEP). This unit implements a three-stage arithmetic pipeline optimized for 16x16 multiplies. Both 16- and 32-bit operands are supported by this design in addition to a full set of extensions for signed and unsigned integers plus signed, fixed point fractional input operands. The MAC unit provides hardware support for a limited number of DSP operations used in embedded code. It also provides signal processing capabilities for ColdFire in a variety of applications including digital audio and servo control.
  • The CAU is an instruction level coprocessor that is accessed with ColdFire coprocessor instructions. The CAU supports acceleration of the following cryptographic algorithms: DES, 3DES, AES, MD5 and SHA-1. The CAU register file consists of eight, 32-bit registers. All registers can be read with the coprocessor store instruction (cp0st.l) and written with the coprocessor load instruction (cp0ld.l).
  • The RNGA module is a digital integrated circuit capable of generating 32-bit random numbers. It is designed to comply with FIPS-140 standards for randomness and non-determinism. The random bits are generated by clocking shift registers with clocks derived from ring oscillators. The configuration of the shift registers ensures statistically good data (i.e. data that looks random). The oscillators with their unknown frequencies provide the required entropy needed to create random data.
  • The Real-Time Clock (RTC) module consists of time-of-day (TOD) clock counter, alarm, minute stopwatch, and associated control and bus interface hardware. The incoming 1 Hz signal is used to increment the seconds, minutes, hours, and days TOD counters. The alarm functions, when enabled, generate RTC interrupts when the TOD settings reach programmed values. The sampling timer generates fixed-frequency interrupts, and the minute stopwatch allows for efficient interrupts on minute boundaries.
  • The reset controller is provided to determine the cause of reset, assert the appropriate reset signals to the system, and keep a history of what caused the reset. The low voltage detection module, which generates low-voltage detect (LVD) interrupts and resets, is implemented within the reset controller module.
  • The MCF5223X supports 4 modes of operation mode, including run, wait, doze, and stop. When the MCU operates in low power mode, it is able to shut down most peripherals independently and the external CLKOUT pin. The system enters a low-power mode by executing a STOP instruction. Which mode the device actually enters (stop, wait, or doze) depends on what is programmed in LPCR[LPMD]. Entry into any of these modes idles the CPU with no cycles active, powers down the system and stops all internal clocks appropriately.
  • The SRAM module provides a general-purpose memory block that the ColdFire processor can access in a single cycle. Because the SRAM module is physically connected to the processor's high-speed local bus, it can service processor-initiated access or memory-referencing commands from the debug module. The SRAM is dual-ported to provide access for the DMA or other on-chip masters. Also, the SRAM is partitioned into two physical memory arrays to allow simultaneous access to both arrays by the processor core and another bus master.
  • The chip configuration module (CCM) controls the chip configuration and mode of operation for the MCF5223x. This module selects external clock or phase-lock loop (PLL) mode with internal or external reference, Output pad drive strength, Low-power configuration, Processor status (PSTAT) and processor debug data (DDATA) functions, and BDM or JTAG mode. The three functions of the CCM module are reset configuration, output pad strength configuration, and clock mode selections.s
  • This module is ideal for program and data storage for single-chip applications and allows for field reprogramming with no external high-voltage sources. The Flash Module itself is 512 Kbytes and supports read, write, and program/erase operations. Bulk erase and page erase operations are supported. Page erase size depends on array size but is currently no larger than 2 Kbytes. Data is programmed in longword (32-bit) fashion. Reads are executed as 2-1-1-1 burst accesses at up to 80 MHz. The voltage required to program the CFM is generated internally by on-chip charge pumps. Program and erase operations are automated. One of the main features of the CFM is its security operation. This feature prevents unauthorized user access to the CFM during single-chip operation. Security can be disabled via a special JTAG bulk erase command in the event of accidental lock out during system development.
  • EzPort is a serial flash programming interface that allows the flash memory contents on a 32 bit general purpose micro-controller to be read, erased, and programmed from off-chip in a compatible format to many stand-alone flash memory chips. The EzPort uses a serial bus interface compatible with SPI in order for the processor to read data from a serial Flash device. It can operate in one of two different modes: enabled and disabled. When enabled, the EzPort ‘steals’ access to the Flash memory, preventing access from other cores or peripherals. The rest of the micro-controller should be disabled when the EzPort is enabled to avoid conflicts. When the EzPort is disabled, the rest of the micro-controller can access Flash memory as normal.
  • The FlexBus module is used as the external system bus interface for ColdFire devices. It can be used to interface to Flash, SRAM, and other external memories or external peripherals that use a parallel bus. The FlexBus module controls the chip selects and control signal timing for external bus accesses. Most implementations support up to six FlexBus chip select signals. The number of chip selects available is device dependent. The FlexBus supports 8, 16, and 32 bit port sizes and byte, word, longword, and line (16 byte) sized transfers to any port size.
  • The Direct Memory Access (DMA) controller module provides a quick and efficient process for moving blocks of data with minimal processor overhead. The DMA module provides up to four independent channels that allow byte, word, longword or 128 bit block with bursting capability for data transfers. These transfers can be single or dual address to off-chip devices or dual address to on-chip devices. The DMA transfer operation can be initiated internally or externally. It can be initiated internally by setting the Start bit in the DMA control register, by pulling one of the two external DMA request pins low, or by the internal UARTs. Single address transfers take one bus cycle. Dual address transfers take two bus cycles. Channel arbitration takes place on transfer boundaries.
  • This module contains the System Bus Controller, Interrupt controller, Chip Select controller, DRAM controller and the General Purpose Input/ Output (GPIO) functions. The Chip Select controller provides a glueless interface to most standard SRAMs, EPROMs, flash, and peripherals. Each of the eight chip select outputs has an address register, mask register, and burst capability. The mask register determines block size, and has the ability to address 8, 16, or 32-bit ports. The chip select outputs feature wait state generation and automatic acknowledge generation. They also feature address setup and address hold features.
  • The UART channel provides a full-duplex asynchronous/synchronous receiver and transmitter deriving an operating frequency from the internal bus clock or an external clock using the timer pin. The transmitter converts parallel data from the CPU to a serial bit stream, inserting appropriate start, stop, and parity bits. It outputs the resulting stream on the transmitter serial data output. The receiver converts serial data from the receiver serial data input to parallel format, checks for a start, stop, and parity bits, or break conditions, and transfers the assembled character onto the bus during read operations. The receiver may be polled, interrupt driven, or use DMA requests for servicing.
  • The Ethernet physical transceiver (Ethernet physical interface) is an IEEE 802.3 compliant 10BASE-T/100BASE-TX Ethernet PHY transceiver. The Ethernet physical interface module supports the medium-independent interface (MII) and the MII management interface. The EPHY requires a 25-MHz crystal for its basic operation. The Ethernet physical interface can be configured to support 10BASE-T or 100BASE-TX applications. The Ethernet physical interface is configurable via internal registers which are accessible through the MII management interface as well as limited configurability using the EPHY register map.
  • The Ethernet Media Access Controller (MAC) is designed to support 10 and 100 Mbps Ethernet/IEEE 802.3 networks. The MAC must be used in conjunction with the on-board transceiver interface and transceiver function to complete the interface to the media. The FEC is implemented with a combination of hardware and microcode. The off-chip (Ethernet) interfaces are compliant with industry and IEEE 802.3 standards. The RAM is the focal point of all data flow in the Fast Ethernet Controller and is divided into transmit and receive FIFOs. The FIFO boundaries are programmable using the FRSR register. User data flows to/from the DMA block from/to the receive/transmit FIFOs. Transmit data flows from the transmit FIFO into the transmit block and receive data flows from the receive block into the receive FIFO.
  • The I 2 C module is a two-wire, bidirectional serial bus that provides a simple, efficient method of data exchange between devices. It is compatible with the widely used “I 2 C” bus standard and is used as an interchip bus interface for devices such as EEPROMs, LCD controllers, A/D converters, and keypads. This two-wire multi-master bus minimizes the interconnection between devices and is suitable for applications requiring occasional communications over a short distance between many devices.
  • The queued serial peripheral interface module provides a serial peripheral interface with queued transfer capability. It allows users to queue up to 16 transfers at once, eliminating CPU intervention between transfers. Transfer RAM in the QSPI is indirectly accessible using address and data registers. The GPIO module must be configured to enable the peripheral function of the appropriate pins prior to configuring the QSPI module.
  • The JTAG interface is normally used to test board interconnects, which are a main cause of circuit board failure. It can also be used for some limited debug support. However, ColdFire devices that include background debug mode normally would not utilize this feature. JTAG eliminates the need and expense of a bed of nails board tester and supports circuit board test strategies that are based on the IEEE 1149.1 standard. JTAG provides access to all of the data and chip control pins from the standard four-pin test access port and the active-low JTAG reset pin. One of the most commonly used features of JTAG is to perform boundary-scan operations to test circuit board electrical continuity. This function can detect open and short circuits on the circuit board for connections that interface to the ColdFire I/O.
  • Thank you for taking the time to view this presentation on MCF5223X: Integrated ColdFire V2 Ethernet Microcontrollers . If you would like to learn more or go on to purchase some of these devices, you may either click on the part list link, or simple call our sales hotline. For more technical information you may either visit the Freescale site, or if you would prefer to speak to someone live, please call our hotline number, or even use our ‘live chat’ online facility.

MCF5223x: Integrated ColdFire V2 Ethernet Microcontrollers MCF5223x: Integrated ColdFire V2 Ethernet Microcontrollers Presentation Transcript

  • MCF5223x: Integrated ColdFire V2 Ethernet Microcontrollers
    • Source: Freescale Semiconductor
  • Introduction
    • Purpose
      • This training module provides an overview of MCF5223x Ethernet Microcontrollers.
    • Outline
      • Feature Overview
      • Target applications
      • Comparison of different Family
      • Key features
    • Content
      • 29 pages
  • Features
    • 10/100 Fast Ethernet Controller with Ethernet PHY.
    • Optional cryptographic acceleration unit (CAU) and random number generator.
    • Up to 57 Dhrystone 2.1 MIPS @ 60 MHz.
    • Enhanced MAC module and hardware divide.
    • 32K bytes SRAM; Up to 256K bytes flash 100K W/E cycles, 10 years data retention.
    • Optional controller area network (CAN) 2.0B controller 4 ch. 32-bit timers with DMA support; 4 ch. 16-bit. capture/compare/PWM timers; 2 ch. periodic interrupt timer; 8/4 ch. 8/16-bit PWM timer.
    • Up to 73 general-purpose I/O.
    • System integration (PLL, SW Watchdog).
    • Single 3.3V supply.
    • Real-time clock.
  • Integration
    • Up to 32 KB SRAM.
    • Up to 256 KB flash: 100 KB W/E cycles, 10 years data retention.
    • 10/100 Fast Ethernet controller (FEC) with PHY.
    • Ethernet media access controller (EMAC) module.
    • Cryptographic accelerator unit with random number generator.
    • CAN 2.0B controller
    • Three UARTs.
    • Queued serial peripheral interface (QSPI).
    • Inter-integrated circuit (I 2 C) bus interface.
    • Four 32-bit timer channels with
    • DMA capability.
    • 4-channel, 16-bit timer for capture, compare and pulse width modulation (PWM).
    • 2-channel periodic interrupt timer.
    • 4-channel, 16-bit or 8-channel, 8-bit PWM generator.
    • Two 4-channel, 12-bit analog-to-digital converters (ADCs).
    • 4-channel DMA controller.
    • Up to 73 general-purpose I/Os.
    • System integration (PLL, SW watchdog).
    • Single 3.3-volt supply.
  • Target Applications
    • Medical instrumentation and monitors.
    • Remote data collection.
    • Power-over-Ethernet.
    • ZigBee control nodes.
    • Security/access control panels.
    • Health care pumps and monitors.
    • Lighting control nodes.
    • Home/industrial automation.
  • Comparison of Different MCF5223X Families
  • MCF5223x Family Block Diagram
  • Version 2 ColdFire CPU core
    • Implements instruction set architecture A+ (ISA_A+)
    • Background debug mode with real-time trace capability
    • Hardware divider is standard
    • DSP support MAC or EMAC block
    • Two-stage instruction fetch pipeline
      • Instruction address generation
      • Instruction fetch
    • Three-longword entry instruction buffer decouples IFP/OEP
    • Two-stage operand execution pipeline
      • Decode and select/operand cycle
      • Address generation execute cycle
  • Enhanced Multiply-Accumulate Unit (EMAC)
    • High-performance solution for maximum signal processing bandwidth.
    • Executes both 16 x 16 and 32 x 32 products with 48-bit accumulation in 1 clock cycle.
    • Speeds up regular ColdFire MULS and MULU instructions.
    • Uses operands in any two data registers and 10 dedicated registers.
      • Four 32-bit accumulators (ACCx) with 16-bit extensions (ACCEXTx) hold the accumulated results
      • MASK constrains addresses for circular queues
      • Overflow/saturation, signed/unsigned, fractional/integer and round/truncate math governed by MACSR[7:4]
      • Dedicated N, Z, V, EV condition code bits reside in MACSR[3:0]
      • Per accumulator overflows reported by MACSR[11:8]
  • Multiply-Accumulate Unit
    • Features:
    • Integrated into the Operand Execution Pipeline
    • Implements a 3 stage arithmetic pipeline optimized for 16x16 multiplies
    • Provides hardware support for a limited number of DSP operations used in embedded code
    • Functionality:
    • Functionality is provided in three related areas:
    • Signed and Unsigned Integer Multiplies
    • Multiply-accumulate operation supporting:
      • 16x16 [un]signed Multiply-accumulate in 1 Clk Cycle
      • 32 x32 [un]signed Multiply-accumulate in 3 Clk Cycles
      • Also supports signed fixed point fractional operands
      • Product may be Shifted once right or left prior to Accumulation
    • Register-based Arithmetic operations
  • Cryptographic Acceleration Unit (CAU)
    • Dedicated, instruction-level coprocessor for DES, 3DES, AES, MD5 and SHA-1 primitives.
    • Requires no new instructions; register file accessed with existing coprocessor load(cp0ld.l) and store (cp0st.l) opcodes.
    • Gate count is reduced by a factor of 6.5 over slave bus MDHA and SKHA blocks used previously.
    • Achieves performance better than wire line on symmetric key algorithms and near or better than wire line on hashing functions.
    • Flexible design can accommodate future needs for new algorithms.
    • Random number generator still resides off platform.
  • Random Number Generator Accelerator (RNGA)
    • The RNGA module is a digital integrated circuit capable of generating 32-bit random numbers.
    • The random bits are generated by clocking shift registers with clocks derived from ring Oscillators.
    • The oscillators with their unknown frequencies provide the required entropy needed to create random data.
    • The RNGA has two primary modes of operation, Normal Mode and Sleep Mode.
    • These are entered by setting the appropriate bits in the RNGA Control Register.
  • Real-Time Clock
    • The RTC module includes the following features:
      • Full clock — days, hours, minutes, seconds
      • Minute countdown timer with interrupt
      • Programmable daily alarm with interrupt
      • Once-per-day, once-per-hour, once-per-minute, and once-per-second interrupts
  • Reset Controller Module
    • Seven sources of reset:
      • External reset input.
      • Power-on reset (POR).
      • Phase locked-loop (PLL) loss of lock.
      • PLL loss of clock.
      • Software.
      • Low-voltage detector (LVD).
      • JTAG CLAMP, HIGHZ and EXTEST instructions.
    • Software-assertable RSTO pin independent of chip reset state.
    • Software-readable status flags indicating the cause of the last reset.
    • LVD control and status bits for setup and use of LVD reset or interrupt.
  • Low Power Modes
    • Run Mode:
    • Run mode is the normal system operating mode.
    • Current consumption in this mode is related directly to the system clock frequency.
    • Wait Mode:
    • Wait mode is intended to be used to stop only the CPU and memory clocks until a wakeup event is detected.
    • Peripherals may be programmed to continue operating and can generate interrupts, which cause the CPU to exit from wait mode.
    • Doze Mode:
    • Each peripheral defines individual operational characteristics in doze mode.
    • Peripherals which continue to run and have the capability of producing interrupts may cause the CPU to exit the doze mode and return to run mode.
    • Stop Mode:
    • All clocks to the system are stopped and the peripherals cease operation.
    • When exiting stop mode, most peripherals retain their pre-stop status and resume operation.
  • SRAM
    • RAM uses two single port arrays and a two-way banked access scheme.
    • Creates a second port to the RAM memory.
    • Manages the dual port memory resource.
    • The SRAM is dual-ported to provide access for the DMA or other on-chip masters.
    • The SRAM is partitioned into two physical memory arrays to allow simultaneous access to both arrays by the processor core and another bus master.
  • Chip Configuration Module (CCM)
    • The CCM selects the following:
      • External clock or phase-lock loop (PLL) mode with internal or external reference.
      • Output pad drive strength.
      • Low-power configuration.
      • Processor status (PSTAT) and processor debug data (DDATA) functions.
      • BDM or JTAG mode.
    • Three functions are defined:
      • Reset configuration
      • Output pad strength configuration
      • Clock mode selections
  • ColdFire Flash Module (CFM)
    • The flash module itself can be up to 512 Kbytes of Flash memory.
    • Concurrent erase or blank verify of all flash array blocks.
    • Supports up to 80 MHz flash array read operations with 2-1-1-1 burst accesses.
    • Single power supply (Vdd, 3.3V) used for all module operations. No need for separate programming voltage.
    • Automated program and erase operation.
    • Read-while-write capability on some devices.
    • 100,000 W/E cycles at room temperature and 10 years data retention.
    • Optional interrupt on command completion.
    • Protection scheme to prevent accidental program or erase.
    • Access restriction control for supervisor/user and data/program space operations.
    • Security for single-chip operations.
    • Auto sense amplifier timeout for low-power, low-frequency read operations.
  • EzPORT
    • Serial Interface that is compatible with a subset of the SPI format.
    • Reset the MCU, allowing to boot from the Flash memory after the memory has been Configured.
    • Two modes of operation:
      • Enabled mode : preventing access flash memory from other cores or peripherals.
      • Disabled mode : the rest of the MCU can access Flash memory as normal .
  • FlexBus – System Bus Controller
    • Independent, user-programmable chip-select signals that can interface with SRAM, PROM, EPROM, EEPROM, Flash, or other peripherals.
    • 8-, 16-, and 32-bit port sizes.
    • Byte, word, longword, and line size transfers.
    • Programmable burst/burst-inhibited transfers selectable for each chip select and transfer direction.
    • Internal and external termination of bus cycles.
      • Up to 63 wait states used for auto-acknowledge cycles.
    • New secondary wait state counter added for burst cycles.
    • Programmable address setup and hold time.
  • Direct Memory Access
    • Up to four fully independent DMA channels.
    • Single and dual address transfer operation.
    • Data transfer of 8, 16, 32 or 128-bit block w/ bursting capability.
    • Auto-alignment capable on source or destination transfers.
    • DMA transfer operation can be initiated internally or externally.
    • Channel arbitration on transfer boundaries.
    • 16-bit or 24-bit byte count register (device implementation dependent).
    • Two address pointers, source and destination.
    • Supports memory to memory, peripheral to memory, and memory to peripheral transfers.
    • Independent transfer widths for source and destination.
    • Source and destination pointer may be programmed to increment after transfer or not.
    • Continuous-mode or cycle-steal transfers.
  • System Integration Module
    • Glueless bus interface with chip selects.
    • 8-, 16- & 32-bit support for DRAM, SRAM, ROM, FLASH & I/O devices.
    • 8 chip-select signals, 2 that are programmable with base address registers, 6 at an offset of one base register.
    • Programmable wait states & port sizes.
    • IEEE 1149.1 test (JTAG) compliant.
    • 16-bit general purpose I/O interface.
    • Programmable interrupt controller
      • Low interrupt latency.
      • 4 external interrupt request inputs.
      • Programmable auto vector generator.
  • Standard Peripheral Block: UART
    • Full-duplex, asynchronous serial port
    • Quadruple-buffered receiver; double-buffered transmitter
    • Independently programmable receiver and transmitter clock sources
    • Data is 5-8 bits plus odd, even, no parity, or force parity and 1, 1½ or 2 stop bits
    • Automatic wake-up mode for multi-drop applications
    • Four maskable interrupt conditions
    • Transmit and receive DMA service capability
  • Ethernet Physical Transceiver (EPHY)
    • Full-/half-duplex support in all modes
    • Supports Medium-independent interface (MII)
    • Supports auto-negotiation
    • Auto-negotiation next page ability
    • Single RJ45 connection
    • 1:1 common transformer
    • Baseline wander correction
    • Digital adaptive equalization
    • Far-end fault detect
    • 125 MHz clock generator and timing recovery
    • Loopback modes
  • Fast Ethernet Controller (FEC)
    • IEEE® 802.3-compliant 10/100 Mbps Ethernet MAC.
    • Standard medium independent interface (MII) to physical layer.
    • Programmable max frame length supports IEEE 802.1 VLAN tags and priority.
    • Full and half duplex operation.
      • 50 MHz minimum platform clock frequency for full duplex
      • 25 MHz minimum platform clock frequency for half duplex
    • Bus-mastering design minimizes CPU intervention.
    • Transmit FIFO re-sends following collision.
    • Automatic receive FIFO flushing for runts and address recognition rejects.
  • I 2 C Module
    • Compatibility with I 2 C bus standard.
    • Interface for EEPROMs, LCD controllers, ADC, and keypads.
    • Two-wire bidirectional serial bus.
    • Multiple master operation.
    • Programmable for one of 64 clock frequencies.
    • Interrupt driven, byte-by-byte transfer.
    • Automatic switching.
    • Start and stop signal generation and detection.
    • Repeated START signal generation.
  • Queued Serial Peripheral Interface (QSPI)
    • Full-duplex, synchronous serial port.
    • Dedicated, 16-entry receive, transmit and command queues.
    • Transfer sizes from 8 to 16 bits inclusive.
    • Four peripheral chip selects.
    • Platform clock feeds fixed ÷2 followed by ÷1 to ÷255 prescaler to generate bit clock.
    • Standard four CPOL/CPHA combinations.
    • Optional pre- and post-transfer delays.
    • Wraparound mode for continuous transfers.
  • JTAG
    • JTAG pins:
      • TDI: test data input.
      • TDO: test data output.
      • TCK: test clock.
      • TMS: test mode select.
      • TRST: test reset.
  • Additional Resource
    • For ordering the MCF5223X, please click the part list or
    • Call our sales hotline
    • For additional inquires contact our technical service hotline
    • For more product information go to
      • http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=MCF5223X&webpageId=1113331549638725695448&nodeId=0162468rH3YTLC00M95448&fromPage=tax
    Newark Farnell