Welcome to the training module on Freescale’s S12XE 16-Bit Automotive Microcontrollers. This training module provides an overview of S12XE family MCUs and internal functional circuits.
S12XE family of microcontrollers featuring the XGATE coprocessor combines 32-bit level performance with all the existing advantages of 16-bit architecture, such as cost effectiveness, code-size efficiency and excellent electromagnetic compatibility. The XGATE coprocessor enabling it to more efficiently handle interrupt events and execute non-critical applets. There is a high level of compatibility between the S12XE and S12XD families. The S12XS family provides an economical, compatible extension to the S12XE Family. The S12XE has larger memory options, error correction code (ECC), enhanced EEPROM (EEE) functionality and an advanced memory protection unit as standard. These advanced features help simplify product development, increase flexibility and reduce overall systems costs for automotive body and multiplexing applications.
The S12XE Family features an enhanced version of the performance-boosting XGATE co-processor, which has improved interrupt handling capability and is fully compatible with existing XGATE module. The S12XE Family also features an enhanced MSCAN module which, when used in conjunction with XGATE, delivers FULL CAN performance with virtually unlimited number of mailboxes and retains backwards compatibility with the MSCAN module featured on existing S12 products. In addition, the S21XE family is composed of standard on-chip peripherals including up to 64Kbytes of RAM, 8 asynchronous serial communications interfaces (SCI), 3 serial peripheral interfaces (SPI), an 8-channel enhanced capture timer (ECT), two 16-channel, 12-bit ADCs, an 8-channel PWM, 2 inter-IC bus blocks (IIC), an 8-channel 24-bit periodic interrupt timer (PIT), and an 8-channel 16-bit standard timer module (TIM).
Here shows a view of all S12XE family members, their Flash memory capacity, RAM, EEPROM, and peripherals.
The CPU12X is a high-speed, 16-bit processing CPU. The CPU12X instruction set is a proper superset of the M68HC11 instruction set. The CPU12X retains all of the instruction set of the CPU12 unchanged. The only exception that requires consideration is that the interrupt stack frame on the CPU12X is increased by one byte due to the extended Condition Code Register. Dedicated address generation logic and pipelined execution improves the CPU12X performance relative to the CPU12 architecture.
The XGATE module is a peripheral co-processor that allows autonomous data transfers between the MCU’s peripherals and the internal memories. It has a built in RISC core that is able to pre-process the transferred data and perform complex communication protocols. the XGATE is a 16-bit RISC processor core running up to double the S12XE CPU bus speed, its RISC core is able to pre-process the transferred data and perform complex communication protocols. The XGATE module is intended to increase the MCU’s data throughput by lowering the S12X_CPU’s interrupt load. The XGATE can deal with lots of different kinds of events in a system but it is especially good at dealing with messages from other systems. It can take each of the LIN events and only alert the CPU when a whole valid message has arrived .The XGATE can also detect when a LIN message is not for the system and either ignore it or re-send it on another bus.
Here are the External bus interface signals that are used by S12XE devices. Two operations can be performed on the external bus: read and write. During a write operation, data is transferred from the S12XE microcontroller to the peripheral connected to the external bus. During a read, data is transferred in the opposite direction, i.e., from the peripheral into the S12X microcontroller. The ADDR lines are always driven by the external bus interface even when there is no external bus access performed.
The clock generator creates the clocks used by the MCU. The individual clocks are gated by conditions of different modes such as STOP and WAIT and by setting respective configuration bits. The peripheral modules use Bus Clock. Some peripheral modules also use Oscillator Clock. The clock monitor performs a coarse check on the incoming clock signal. The Clock Quality Checker more accurately checks the clock in addition to the clock monitor. The COP (Computer Operating Properly) watchdog enables a developer to force a reset if not served properly. The RTI (Real Time Interrupt) can be used to generate a hardware interrupt at a fixed periodic rate. RESET is an active low bidirectional reset pin. As an input it initializes the MCU asynchronously to a known start-up state. As an open-drain output it indicates that an system reset (internal to MCU) has been triggered.
The period interrupt timer (PIT) is an array of 24-bit timers that can be used to trigger peripheral modules or raise periodic interrupts. The main parts of the PIT are status, control and data registers, two 8-bit down-counters, eight 16-bit down-counters and an interrupt/trigger interface. The 24-bit timers are built in a two-stage architecture with eight 16-bit modulus down-counters and two 8-bit modulus down-counters. The PIT module contains eight hardware trigger signal lines PITTRIG[7:0], one for each timer channel. Each time-out event can be used to trigger an interrupt service request. For each timer channel, an individual bit in the PIT interrupt enable register exists to enable this feature.
The ADC is a 16-channel, 12-bit, multiplexed input, successive approximation analog-to-digital converter. It is structured into analog and digital sub-blocks. The analog sub-block contains all analog electronics required to perform a single conversion. Separate power supplies VDDA and VSSA allow to isolate noise of other MCU circuitry from the analog sub-block. The Sample and Hold (S/H) Machine accepts analog signals from the external world and stores them as capacitor charge on a storage node. The analog input multiplexer connects one of the 16 external analog input channels to the sample and hold machine. The external trigger feature allows the user to synchronize ATD conversions to the external environment events rather than relying on software to signal the ATD module when ATD conversions are to take place.
The inter-IC bus (IIC) is a two-wire, bidirectional serial bus that provides a simple, efficient method of data exchange between devices. Being a two-wire device, the IIC bus minimizes the need for large numbers of connections between devices, and eliminates the need for an address decoder. It has 2 signals: IIC_SCL — Serial Clock Line Pin and IIC_SDA — Serial Data Line Pin. IIC_SCL is the bidirectional serial clock line (SCL) of the module, compatible to the IIC bus specification. IIC_SDA is the bidirectional serial data line (SDA) of the module, compatible to the IIC bus specification.
This module is a communication controller implementing the CAN 2.0A/B protocol: it has five receive buffers with a FIFO storage scheme. A flexible maskable identifier filter is provided to support two full-size (32-bit) extended identifier filters, or four 16-bit filters, or eight 8-bit filters. The MSCAN module adds a new manual control for recovery from Bus-off conditions. In the manual mode, the bus-off recovery is under software control after 128 × 11 received bits.
The PWM module has eight channels with independent control of left and center aligned outputs on each channel Each of the eight channels has a programmable period and duty cycle as well as a dedicated counter. A flexible clock select scheme allows a total of four different clock sources to be used with the counters Each of the modulators can create independent continuous waveforms with software-selectable duty rates from 0% to 100%. The PWM outputs can be programmed as left aligned outputs or center aligned outputs.
The SCI features new hardware support for the following: IrDA protocol, LIN detection of break signal and bus signal collisions, wake up interrupts on active edges, and alternate pin polarity on the receive and transmit pins.
The SPI module allows a duplex, synchronous, serial communication between the MCU and peripheral devices. Software can poll the SPI status flags or the SPI operation can be interrupt driven. It supports 16-bit data transfers as well as 8-bit transfers. This is controlled via a new transfer word (XFRW) in a control register (IBCR2 bit 5).
The basic timer consists of a 16-bit, software-programmable counter driven by a enhanced programmable prescaler. This timer can be used for many purposes, including input waveform measurements while simultaneously generating an output waveform. Pulse widths can vary from microseconds to many seconds. This timer contains 8 complete input capture/output compare channels and one pulse accumulator. The input capture function is used to detect a selected transition edge and record the time. The output compare function is used for generating output signals or for timer software delays.
VREG_3V3 is a tri output voltage regulator that provides two separate 1.84V (typical) supplies differing in the amount of current that can be sourced and a 2.82V (typical) supply. The regulator input voltage range is from 3.3V up to 5V (typical). It has Three parallel, linear voltage regulators with bandgap reference, Low-voltage detect (LVD) with low-voltage interrupt (LVI), Power-on reset (POR), Low-voltage reset (LVR), High Temperature Detect (HTD) with High Temperature Interrupt (HTI).
The interrupt controller module for S12XE allows up to seven levels of interrupts (I-bit) to be available to the user. The XIRQ, SWI, BDM, unimplemented opcode, and system reset interrupts are available. each interrupt source can be allocated one of seven possible interrupt levels New interrupt vectors include one for detection of spurious interrupts like where an interrupt source is removed before the vector is fetched, one for the new SYS instruction, one for CPU MPU violations, and one for XGATE MPU violations or software errors.
The S12XE Family of MCUs supports similar tools and third party developers as other Freescale S12X products, offering a widespread, established network of tools and software vendors.
In this example, the MC9S12XE is implementing the features of a typical car body controller application. The module interfaces with the main CAN buses distributed in the car using the on-chip MSCAN module whereas the LIN bus communicates with functions local to the body controller. In both cases the communication functions are managed by the XGATE independently of the CPU. The MC9S12XE provides direct control of power drivers for lights and pumps and reading of sensors, using the on-chip PWM and ATD modules. Finally, the SPI interface to the RF receiver provides the interface to the car remote access system.
In this application, the MC9S12XE provides gateway functionality between its on-chip CAN and LIN modules. Much of the low-level communications functionality is handled by the XGATE, which frees the CPU to manage higher level communications and other direct connections to the module.
Thank you for taking the time to view this presentation on Freescale’s S12XE 16-Bit Automotive Microcontrollers . If you would like to learn more or go on to purchase some of these devices, you may either click on the part list link, or simply call our sales hotline. For more technical information you may either visit the Freescale site – link shown – or if you would prefer to speak to someone live, please call our hotline number, or even use our ‘live chat’ online facility.
Introduction of 16-Bit Automotive Microcontrollers S12XE
Introduction <ul><li>Purpose </li></ul><ul><ul><li>This training module provides an overview of S12XE family MCUs and internal functional circuits. </li></ul></ul><ul><li>Outline </li></ul><ul><ul><li>Overview S12XE MCUs </li></ul></ul><ul><ul><li>S12XE family members </li></ul></ul><ul><ul><li>Introduction of internal functional modules </li></ul></ul><ul><ul><li>Application block diagram </li></ul></ul><ul><li>Content </li></ul><ul><ul><li>22 pages </li></ul></ul>
Overview of S12XE <ul><li>Excellent System Performance </li></ul><ul><ul><li>Increased CPU bus frequency up to 50 MHz; </li></ul></ul><ul><ul><li>32-bit performance with all the advantages and efficiencies of a 16 bit MCU </li></ul></ul><ul><li>Scalability and Compatibility </li></ul><ul><ul><li>Extends S12X memory size up to 1 MB </li></ul></ul><ul><ul><li>Provides an upgrade path for the S12XD family </li></ul></ul><ul><li>High System Integrity </li></ul><ul><ul><li>At the MCU level from features such as the ECC Supervisor Mode and the MPU which eases AUTOSAR integration </li></ul></ul><ul><li>Flexibility </li></ul><ul><ul><li>Supports customer requirements, with high memory, enhanced ATD and a large number of peripherals and packaging options </li></ul></ul><ul><li>Development Support </li></ul><ul><ul><li>extensive suite of hardware and software development tools available </li></ul></ul>
S12XE Family Members Memory options Communications Timers
S12XE CPU – CPU12X <ul><li>Full 16-bit data paths supports efficient arithmetic operation and high-speed math execution </li></ul><ul><li>Supports instructions with odd byte counts, including many single-byte instructions. </li></ul><ul><li>CPU12X has immediate access to at least three bytes of machine code at the start of every instruction. </li></ul><ul><li>Extensive set of indexed addressing capabilities. </li></ul>Programming Model
XGATE Block Diagram <ul><li>Programmable, high performance I/O coprocessor module with up to 100 MIPS RISC performance </li></ul><ul><li>Transfers data to or from all peripherals and RAM without CPU intervention or CPU wait states </li></ul><ul><li>Performs logical, shifts, arithmetic, and bit operations on data </li></ul><ul><li>Can interrupt the S12X CPU signalling transfer completion </li></ul><ul><li>Triggers from any hardware module as well as from the CPU possible </li></ul><ul><li>Two interrupt levels to service high priority tasks </li></ul><ul><li>Enables Full CAN capability when used in conjunction with MSCAN module </li></ul><ul><li>Full LIN master or slave capability when used in conjunction with the integrated LIN SCI modules </li></ul>
Clocks and Reset Generator <ul><li>Phase-locked-loop (IPLL) clock frequency multiplier </li></ul><ul><ul><li>Internally filtered. No external components required </li></ul></ul><ul><ul><li>Configurable option to spread spectrum for reduced EMC radiation </li></ul></ul><ul><li>Fast wake up from STOP in self clock mode for power saving and immediate program execution </li></ul>
Periodic Interrupt Timer (PIT) <ul><li>Up to 8 timers with independent time-out periods </li></ul><ul><li>Time-out periods selectable between 1 and 224 bus clock cycles </li></ul><ul><li>Time-out interrupt and peripheral triggers </li></ul>
Inter-Integrated Circuit <ul><li>Compatible with I2C bus standard </li></ul><ul><li>Multi-master operation </li></ul><ul><li>Software programmable for one of 256 different serial clock frequencies </li></ul><ul><li>Software selectable acknowledge bit </li></ul><ul><li>Interrupt driven byte-by-byte data transfer </li></ul><ul><li>Arbitration lost interrupt with automatic mode switching from master to slave </li></ul><ul><li>Calling address identification interrupt </li></ul><ul><li>Start and stop signal generation / detection </li></ul>
MSCAN <ul><li>Up to five MSCAN modules </li></ul><ul><li>CAN 2.0 A, B software compatible </li></ul><ul><li>Five receive buffers with FIFO storage Three transmit buffers with internal prioritization </li></ul><ul><li>Flexible identifier acceptance filter programmable </li></ul><ul><li>Wake-up with integrated low pass filter </li></ul><ul><li>Loop back for self test </li></ul><ul><li>Listen-only mode to monitor CAN bus </li></ul><ul><li>Bus-off recovery by software intervention or automatically </li></ul><ul><li>16-bit time stamp of transmitted/received messages </li></ul><ul><li>FULL-CAN capability when used in conjunction with XGATE </li></ul>
PWM Block Diagram <ul><li>Eight independent PWM channels with programmable period and duty cycle </li></ul><ul><li>Dedicated counter for each PWM channel </li></ul><ul><li>Period and duty cycle are double buffered. </li></ul><ul><li>Programmable center or left aligned outputs on individual channels </li></ul><ul><li>Eight 8-bit channel or four 16-bit channel PWM resolution </li></ul><ul><li>Four clock sources (A, B, SA, and SB) provide for a wide range of frequencies </li></ul>
Serial Communication Interface <ul><li>Full-duplex or single-wire operation </li></ul><ul><li>Standard mark/space non-return-to-zero (NRZ) format </li></ul><ul><li>13-bit baud rate selection </li></ul><ul><li>Programmable 8-bit or 9-bit data format </li></ul><ul><li>Separately enabled transmitter and receiver </li></ul><ul><li>1/16 bit-time noise detection </li></ul><ul><li>Two receiver wakeup methods </li></ul>
Serial Peripheral Interface The SPI includes these distinctive features: • Master mode and slave mode • Selectable 8 or 16-bit transfer width • Bidirectional mode • Slave select output • Mode fault error flag with CPU interrupt capability • Double-buffered data register • Serial clock with programmable polarity and phase • Control of SPI operation during wait mode
Voltage Regulator • Three parallel, linear voltage regulators with bandgap reference • Low-voltage detect (LVD) with low-voltage interrupt (LVI) • Power-on reset (POR) • Low-voltage reset (LVR) • High Temperature Detect (HTD) with High Temperature Interrupt (HTI) • Autonomous periodical interrupt (API)
Additional Resource <ul><li>For ordering the S12XE MCUs, please click the part list or </li></ul><ul><li>Call our sales hotline </li></ul><ul><li>For additional inquires contact our technical service hotline </li></ul><ul><li>For more product information go to </li></ul><ul><ul><li>http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=S12XE&nodeId=01624686365dlqbJwn </li></ul></ul>