This is a training module on the Freescal i.MX233 applications processors
Welcome to the training module on the i.mx233 application processors. We will talk about the Block diagram, different boot modes, peripherals of the i.Mx233 processor, external memory controller and software interface with WinCE and Linux
This page gives information about the Embedded road map for iMX devices which has ARM-9, ARM-11 and Cortex A8 based architectures.
The i.MX233 applications processor based on the ARM926EJ-S™ can run at speeds up to 454MHz and is targeted for cost sensitive consumer applications. The power management unit (PMU) integrates a DC-DC switching converter and multiple linear regulators to provide power sequencing for the device itself and to drive I/O peripherals such as memories and SD cards as well as providing battery charging capability for Li-Ion batteries. The i.MX233 also integrates mixed signal analog audio with a 1.5W Mono speaker amplifier, a stereo headphone DAC with 99dB Signal-to-Noise ratio and a stereo ADC with 85dB Signal-to-Noise ratio with integrated amplifiers.
This page gives additional information about the peripheral features like analog based features of the Audio Codec, headphone driver, power management, battery charger, 12 bit- ADC, and LCD controller with RGB interface and touchscreen.
The unique architectural design of the i.MX233 processor enables the development of cost efficient solutions for a wide range of applications, like portable media players, portable navigation devices, e-books, audio peripherals, industrial HMI, etc.
The i.MX233 applications processor simplifies development by integrating mixed signal IP and provides a cost-efficient, system-on-chip solution to maximize performance and extend battery life. With an ARM9 core operating up to 454MHz, the i.MX233 processor is designed to maximize performance and extend battery life It has Integrated power management, analog audio and A/D channels, an Image processing unit supporting 24-bit VGA displays provides rich user interfaces. It has On-chip SDIO controller for wireless (WiFi, Bluetooth), memory card, or other SDIO connectivity options, including boot from SLC, MLC and managed NANDs capability, Supporting 20-bit BCH error correction to improve reliability.
The i.MX23 SOC contains a data co-processor consisting of four virtual channels. Each channel is essentially a memory-to-memory copy engine. The linked list control structure can be used to move byte-aligned blocks of data from a source to a destination. In the process of copying from one place to another, the DCP can be programmed to encrypt or decrypt the block using AES-128 in one of several chaining modes. An SHA-1 hash can be calculated as part of the memory-copy operation
Boot mode initiates ROM drivers to bring a program into the i.MX233 OCRAM. There are 4 different boot modes available they are USB slave boot, I2C master boot, SPI master which Loads images from EEPROMs or NORs and SSP boot mode.
This page shows a diagram of the power block which includes switching converters, five linear regulators, battery charge support, as well as battery monitoring, supply brownout detection, and silicon process/temperature sensors. The i.MX233 power supply is designed to offer maximum flexibility and performance, while minimizing external component requirements. The DC-DC converters efficiently scale battery voltage (or a regulated 4.2 V derived from a 5 V source) to the required supply voltages. The i.MX233 DC-DC converter enables a low-power system and features programmable output voltages and control modes.
The i.MX233 supports off-chip DRAM storage via the EMI controller, which is connected to the four internal AHB/AXI busses. The DRAM controller supports up to two external chip-select signals for the i.MX233 platform. Programmable registers within the DRAM controller allow great flexibility for device timings, low-power operation, and performance tuning. The EMI uses two primary clocks: the AHB bus HCLK and the DRAM source clock EMI_CLK.
The i.MX23 contains an integrated USB 2.0 PHY macrocell capable of connecting to PC host systems at the USB full-speed (FS) rate of 12 Mbits/s or at the USB 2.0 high-speed (HS) rate of 480 Mbits/s. The integrated PHY provides a standard UTM interface. The USB_DP and USB_DN pins connect directly to a USB device connector.
The general-purpose media interface (GPMI) controller is a flexible interface to up to four NAND Flash. The NAND Flash mode has configurable address and command behaviour, providing support for future devices not yet specified. The GPMI resides on the APBH. The GPMI also provides an interface to the ECC8 and BCH modules to allow direct parity processing. Hardware BCH/ECC Interface Provides a forward error-correction function to improve the reliability of various storage media that may be attached to the i.MX233.
The high-level block diagram of the LCD interface provided on the i.MX23 is shown on this page Many products based on the i.MX233 include an LCD panel with an integrated controller/driver. These smart LCDs are available in a range of sizes and capabilities, from simple text-only displays to QVGA, 16/18/24 bpp colour TFT panels. It includes major features like: • Bus master and PIO operating modes for LCD writes requiring minimal CPU overhead. • 8/16/18/24 bit LCD data bus support available depending on the package size. • Programmable timing and parameters for system, VSYNC and DOTCLK LCD interfaces to support a wide variety of displays.
The pixel pipeline is used to perform alpha blending of graphic or video buffers with graphics data before sending to an LCD display or TV encoder. The PXP provides a performance-optimized engine that can meet the needs of both SDRAM and SDRAM-less systems. The PXP also supports image rotation for hand-held devices that require both portrait and landscape image support. The PXP is organized as having a background image (S0) and one or more overlay images that can be blended with the background. Each overlay image must be a multiple of eight pixels in both height and width and the offset of the overlay into the background image must be a multiple of eight pixels.
To provide the maximum application flexibility, the i.MX233 integrates a wide range of I/O ports. It can efficiently interface to nearly any type of flash memory, serial peripheral bus, or LCD. It is also ready for advanced connectivity applications such as Bluetooth and WiFi via its integrated 4-bit SDIO controller and high-speed (3.25 Mb/s) UARTs. The i.MX23 also integrates an entire suite of analog components, including a high-resolution audio codec with headphone amplifier, 16-channel 12-bit ADC, 10-bit Video DAC, Mono Speaker Amplifier, high-current battery charger, linear regulators for 5-V operation, high-speed USB Host PHY, and various system monitoring and infrastructure systems.
This page gives information about the i.MX233 Evaluation Kit which is a Single Board Development Platform – Price, Performance, Personality. It has an i.MX233 Applications Processor, 2 x 64MB DDR1, 1GB NAND FLASH, 4.3” WQVGA Touchscreen LCD Display, SD/MMC Card Slot, USB Host/Device, Ethernet supported via SPI header, 3-Axis Accelerometer footprint, Expansion Port for optional Peripheral Card.
This page gives information about Win CE software support for the iMX233 devices, it has WinCE BSP ER3 for display, audio and memory application And WinCE BSP ER4 for power management features, WinCE BSP ER5 – for bug fixes, Possible integration of CE6 R3. it has Video codec for MP4, AVI (H.264 and MPEG4) and Audio codec for WMA, AAC, MP3 with codec protection.
Similar to the previous slide iMX233 supports Linux BSP also.
Product features of the reference design “ wireless media player” are: • Stream audio content from internet • Stream audio/video content from a PC • Play audio/video from iPod, USB stick or SD card • Display slideshow of pictures from PC or internet based service
Thank you for taking the time to view this presentation on “ i.MX233” . If you would like to learn more or go on to purchase some of these devices, you may either click on the part list link, or simply call our sales hotline. For more technical information you may either visit the Freescale Semiconductor’s site, or if you would prefer to speak to someone live, please call our hotline number, or even use our ‘live chat’ online facility. You may visit element14 e-community to post your questions.
Introduction <ul><li>Purpose </li></ul><ul><ul><li>An Brief Introduction to Application Processor: i.MX233 </li></ul></ul><ul><li>Outline </li></ul><ul><ul><li>Features and Applications </li></ul></ul><ul><ul><li>Block Diagram of Processor and Data Co-Processor (DCP) </li></ul></ul><ul><ul><li>Boot Modes, Logical Power Block, Integrated USB 2.0 PHY </li></ul></ul><ul><ul><li>i.MX233 – External Memory Controller and i.MX233 Peripherals </li></ul></ul><ul><ul><li>i.MX233 Evaluation Kit (EVK) and WinCE / Linux Software Support </li></ul></ul><ul><li>Content </li></ul><ul><ul><li>21 pages </li></ul></ul>
Data Co-Processor (DCP) <ul><li>The DCP module provides support for general encryption and hashing functions typically used for security functions. </li></ul><ul><li>The DCP has been designed to support a wide variety of encryption and hashing algorithms. It supports up to 16 encryption algorithms </li></ul><ul><li>The DCP module processes data based on chained command structures written to system memory by software (in a manner similar to the DMA engine). </li></ul><ul><li>The data flow through the DCP module can be configured in one of five fashions, depending on the functionality activated by the control packet: </li></ul>
i.MX233 – External Memory Controller <ul><li>Support for mDDR (1.8V) and DDR1 (2.5V) , with all voltages supplied by integrated power management unit </li></ul><ul><li>Up to 150MHz with 16-bit interface </li></ul><ul><li>4-ports with a hybrid AHB/AXI mix, allowing for high-bandwidth masters to make more efficient requests </li></ul><ul><li>Full support of mDDR power modes including self-refresh and clock gating </li></ul><ul><li>Hardware assisted on-the-fly frequency changing </li></ul>
Integrated USB 2.0 PHY <ul><li>The i.MX233 contains an integrated USB 2.0 PHY macro cell capable of connecting to PC host systems </li></ul><ul><li>The UTMI block handles the line_state bits, reset buffering, suspend distribution, transceiver speed selection, and transceiver termination selection </li></ul><ul><li>The UTM provides a 16-bit interface to the USB controller. This interface is clocked at 30 MHz. </li></ul><ul><li>The integrated PHY provides a standard UTM interface. The </li></ul><ul><li>USB_DP and USB_DN pins connect directly to a USB device connector. </li></ul>
General-Purpose Media Interface (GPMI) <ul><li>General-Purpose Media Interface Controller </li></ul><ul><li>Enables access to media devices that have NAND </li></ul><ul><li>Supports up to four NAND Flash devices </li></ul><ul><li>Provides an interface to ECC module </li></ul><ul><li>Supports 3.3V only </li></ul><ul><li>NAND Types supported </li></ul><ul><li>SLC NAND </li></ul><ul><li>MLC NAND </li></ul><ul><li>Managed NAND – eMMC 4.2/4.3, LBA </li></ul>
i.MX233 Peripherals – LCDIF <ul><li>Display Controller (LCDIF) </li></ul><ul><li>Up to 24-bit DOTCLK, system-mode, VSYNC with programmable timings. </li></ul><ul><li>On-the-fly RGB->YCbCr 4:2:2 for </li></ul><ul><li>ITU-R/BT.656 DV interface (with </li></ul><ul><li>interlacing) </li></ul><ul><li>Rich support for RGB formats </li></ul><ul><li>including pixel packing and swizzling. </li></ul><ul><li>128-pixel FIFO provides robustness for up to VGA resolution at 60Hz. </li></ul><ul><li>AXI Master for efficiency </li></ul><ul><li>Direct internal connection to TVE </li></ul>
PXP and Display – System Overview <ul><li>The PXP is organized as having a background image (S0) and overlay images that can be blended with the background. </li></ul><ul><li>The S0 plane can be unscaled RGB image or YUV images with colorspace conversion (YUV->RGB) and scaling </li></ul><ul><li>The OLn plane can consist of up to 8 overlay regions. </li></ul><ul><li>Each overlay region must be a multiple of 8x8 pixels block, and its width and height offset to the background must be multiple of 8 pixels. </li></ul><ul><li>The overlay regions be combined with S0 by alpha blending, colour key substitution, or raster operations </li></ul><ul><li>The resulting image may be rotated in 90 increments or flipped horizontally or vertically </li></ul>
i.MX233 Peripherals <ul><li>I2C </li></ul><ul><ul><li>EEPROM, Sensors </li></ul></ul><ul><ul><li>DMA controlled with M/S mode up to 400KHz </li></ul></ul><ul><li>4-Channel 16-Bit Timers with Rotary Decoder </li></ul><ul><li>Five-Channel Pulse Width Modulator (PWM) </li></ul><ul><li>Real-Time Clock </li></ul><ul><ul><li>Options for 24MHz, 32KHz or 32.768KHz </li></ul></ul><ul><ul><li>Storage of “persistent bits” </li></ul></ul><ul><ul><li>Wake from alarm </li></ul></ul><ul><li>UARTs </li></ul><ul><ul><li>2 x 3.25Mbps App UARTs </li></ul></ul><ul><ul><li>1 x 115Kbps Debug UART </li></ul></ul><ul><li>S/PDIF Transmit </li></ul><ul><li>Dual Serial Audio Interface (SAIF), Three Stereo Pairs </li></ul><ul><ul><li>Full-duplex stereo transmit and stereo receive operations </li></ul></ul><ul><ul><li>Bluetooth hands-free connection </li></ul></ul><ul><ul><li>I2S, left-justified, right-justified, and nonstandard formats </li></ul></ul>
Additional Resource <ul><li>For ordering i.MX233 devices, please click the part list or </li></ul><ul><li>Call our sales hotline </li></ul><ul><li>For more product information go to </li></ul><ul><ul><li>http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=i.MX233&fsrch=1 </li></ul></ul><ul><li>Visit element14 to post your question </li></ul><ul><ul><li> www.element-14.com </li></ul></ul><ul><li>For additional inquires contact our technical service hotline or even use our “Live Technical Chat” online facility </li></ul>