Flexis QE 32-bit  ColdFire® V1 Microcontrollers  <ul><li>Source: FREESCALE </li></ul>
Introduction <ul><li>Purpose </li></ul><ul><li>This   training   module   provides   detailed   information   on   the   M...
ColdFire ®  Family Summary <ul><li>Compatible family of processor cores architected for SoC and reuse </li></ul><ul><ul><l...
MCF51QE Family Architecture
Low Power Benefits  <ul><ul><li>Low-power run and wait modes that enable reduced current and reduced speed modes for perip...
V1 ColdFire Core Features <ul><li>Architecture </li></ul><ul><ul><li>Variable-length RISC architecture and implementation ...
ColdFire Core Architecture
Rapid General Purpose Input/Output (RGPIO)
Interrupt Controller <ul><li>The priorities of the interrupt requests between comparable HCS08 and V1 ColdFire devices are...
Peripherals <ul><li>24-channel, 12-bit ADC  </li></ul><ul><li>2 Analog Comparators  </li></ul><ul><li>2 Serial Communicati...
Memory Map <ul><li>Fixed address memory map </li></ul><ul><ul><li>Restricted to 24-bit address = 16 Mbyte space </li></ul>...
Programming Model <ul><li>User Programming Model </li></ul><ul><ul><li>16 x 32-bit General Purpose Registers </li></ul></u...
MCF51QE128 Series Comparison 80LQFP 64LQFP 64LQFP Package 16 16 16 KBI Yes Yes Yes ICS Up to 24 20 20 ADC Channels 2 2 2 I...
Development Tools EVBQE128: It can be used as a standalone application or can be controlled by a host PC via its built-in ...
CodeWarrior Development Studio for Microcontrollers v6.0 <ul><li>CodeWarrior Development Studio provides everything the pr...
Target Applications
Application Block Diagram: Blood Pressure Monitor
Additional Resource <ul><li>For ordering the MCF51QE MCUs, please click the part list or </li></ul><ul><li>Call our sales ...
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Flexis QE 32-bit ColdFire® V1 Microcontrollers

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Detailed information on the MCE51QE microcontrollers

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  • Welcome to the training module on Freescale Flexis QE 32-bit ColdFire® V1 Microcontroller . This training module provides detailed information on the MCF51QE microcontrollers.
  • From its inception, ColdFire has been designed to provide a compatible family of processor cores that are architected for system-on-a-chip design flows and reuse. The entire family has been 100% synthesizable since its inception in 1995. The cores use a standard rising-edge D flip-flop implementation which is design-for-test friendly and easily adaptable to a wide range of process technologies. ColdFire has always had a strong embedded debug architecture which allows common development tools to be used for Freescale products as well as customer-specific designs. the core architecture includes support for a coprocessor interface to accelerate operations at the instruction- or function-level. An example is our Cryptographic Acceleration Unit, the CAU, which has been included on a number of devices. The CAU provides a significant performance boost to a number of security algorithms popular today.
  • The MCF51QE128, MCF51QE64, and MCF51QE32 are members of the low-cost, low-power, high-performance Version 1 (V1) ColdFire family of 32-bit microcontroller units (MCUs). All MCUs in the family use the enhanced V1 ColdFire core and are available with a variety of modules, memory sizes, and package types. CPU clock rates on these devices can reach 50.33 MHz. Peripherals operate up to 25.165 MHz.
  • Through an optimized architecture that provides lower operating voltage and current, these Flexis devices offer industry-leading ultra-low-power benefits to minimize operating costs and extend battery life. The data table presents the current draw in a number of operating modes including run mode with CPU operation at 2 MHz and full-speed 50 MHz and low-power run mode with CPU operation at 32 kHz. It also shows Stop2 - the lowest power mode - with dissipation of 370 nanoamps for both devices, Stop3 - another low power mode - and finally, the wakeup time from exiting Stop3 as 6 microseconds for MCF51QE128 device.
  • The V1 core is a variable-length RISC architecture and implementation, supporting Revision C of the ColdFire Instruction Set Architecture. The implementation includes 24-bit address and 32-bit data paths, and the core design optionally supports inclusion of various execute engines like the integer divider, multiply-accumulate engines (both the MAC or EMAC) and the cryptographic acceleration coprocessor. The V1 programming model supports the standard ColdFire definition, which includes a user-mode model containing 16 general-purpose 32-bit data and address registers, a 32-bit program counter and an 8-bit Condition Code Register containing indicator flags reflecting the results of instruction execution. The supervisor-mode model adds the Status Register, another stack pointer, a vector base register used during exception processing and a CPU configuration register, which provides software control over a number of key hardware configuration variables.
  • V1 ColdFire core is comprised of two separate pipelines decoupled by an instruction buffer, Instruction Fetch pipeline (IFP) and Operand Execution pipeline (OEP). The IFP is a two-stage pipeline for pre fetching instructions. The prefetched instruction stream is then gated into the two-stage operand execution pipeline which decodes instruction, fetches the required operands and then executes the required function. Because the IFP and OEP pipelines are decoupled by an instruction buffer serving as a FIFO queue, the IFP is able to prefetch instructions in advance of their actual use by the OEP thereby minimizing time stalled waiting for instructions.
  • The Rapid GPIO (RGPIO) module provides a 16-bit general-purpose I/O module directly connected to the processor’s high-speed 32-bit local platform bus. This connection to the processor’s high-speed platform bus plus support for single-cycle, zero wait-state data transfers allows the RGPIO module to provide improved pin performance when compared to more traditional GPIO modules located on the internal slave peripheral bus. This module is a memory-mapped device. The data register bits can be accessed directly or via alternate addresses which support set, clear and toggle functions using simple store instructions.
  • This interrupt controller (CF1_INTC) is intended for use in low-cost microcontroller designs using the Version 1 (V1) ColdFire processor core. In keeping with the general philosophy for devices based on this low-end 32-bit processor, the interrupt controller generally supports less programmability compared to similar modules in other ColdFire microcontrollers and embedded microprocessors. However, this interrupt controller provides the required functionality with a minimal silicon cost. The ColdFire processor architecture defines a 3-bit interrupt priority mask field in the processor’s status register. This field, and the associated hardware, support seven levels of interrupt requests with the processor providing automatic nesting capabilities.
  • The MCF51QE MCUs contain a rich set of peripherals, including 24-channel, 12-bit ADC, 2 Analog Comparators, 2 Serial Communications Interface (SCI/UART), 2 Serial Peripheral Interface (SPI), 2 I²C, and Timers. The analog comparator provides a circuit for comparing two analog input voltages or for comparing one analog input voltage to an internal reference voltage. The SCIs offer asynchronous communications, 13-bit break option, flexible baud rate generator, double buffered transmit and receive and optional H/W parity checking and generation. The inter-integrated circuit provides a method of communication between a number of devices. The interface is designed to operate up to 100 kbps with maximum bus loading and timing.
  • V1 ColdFire cores implement a fixed address map with a 24-bit address space. This provides a 16 MByte definition, which is sufficient for the devices targeted for this application space. Even though the address space is restricted to 24 bits, we still represent addresses as 32-bit values because there are still certain hardware structures that retain the full vector width. The system address map is partitioned into 4 regions: flash, based at zero; RAM, based at hex 800,000; the rapid GPIO module, based at hex c00,000; and a 32 Kbyte region for all the slave peripherals.
  • There are two Programming Models configurable: User model and Supervisory model. The user programming model includes sixteen 32-bit general-purpose registers, split equally into 8 data registers and 8 address registers. There is a 32-bit program counter which defines the current instruction being executed and an 8-bit Condition Code Register, which contains indicator flags to record the results of a previous instruction’s execution. This includes flags to signal a negative result, zero, overflow and a carry out. These flags are used by conditional branch instructions to determine whether the branch should be taken or not. The supervisor programming model includes all the user registers plus a status register, another stack pointer, a vector base register used during exception processing and a CPU configuration register, which provides software control of hardware configuration settings.
  • Here shows the comparison of different MCF51QE series regarding its Flash memory capacity, SRAM, interfaces like IIC, SPI, ADCs, ICS (Internal Clock Source ) , KBI and packages available.
  • The EVBQE128 board has been designed for the evaluation, demonstration and debugging of the Freescale Flexis QE128 Microcontrollers, including MC9S08QE128 and MCF51QE128. It can be used as a standalone application or can be controlled by a host PC via its built-in microDART™ interface. The DEMOQE128 demo board is a low-cost development system designed for demonstrating, evaluating, and debugging the Freescale microcontrollers. The board supports two interchangeable plug-in daughter cards to quickly evaluate the 8-bit S08 and 32-bit ColdFire V1 QE128 microcontrollers.
  • CodeWarrior Development Studio for Microcontrollers is a single tool suite that supports software development for Freescale’s 8-bit and 32-bit ColdFire V1 microcontrollers. Designers can further accelerate application development with the help of Processor Expert, an award-winning rapid application development tool integrated into the CodeWarrior tool suite.
  • The MCF51QE V1 ColdFire core was designed to be used by applications that have reached their performance limit on 8-bit processors but want to reduce the time to market for higher performance implementations. Some of these possible applications include security systems, health monitoring systems, home appliances, and many, many more. The V1 ColdFire core is also perfect for designers interested in achieving a low-cost and low-overhead link to future 32-bit designs.
  • The Blood Pressure Monitor reference design demonstrates how the sensing, data communication and processing capabilities of Freescale products interact to create a complete medical handheld solution. This Blood Pressure Monitor design was crafted to serve as reference for those designs that need expansion flexibility. Enabled to use both the 8-bit MC9S08QE128 and 32-bit MCF51QE128,
  • Thank you for taking the time to view this presentation on Flexis QE 32-bit ColdFire® V1 Microcontroller . If you would like to learn more or go on to purchase some of these devices, you may either click on the part list link, or simply call our sales hotline. For more technical information you may either visit the Freescale site – link shown – or if you would prefer to speak to someone live, please call our hotline number, or even use our ‘live chat’ online facility.
  • Flexis QE 32-bit ColdFire® V1 Microcontrollers

    1. 1. Flexis QE 32-bit ColdFire® V1 Microcontrollers <ul><li>Source: FREESCALE </li></ul>
    2. 2. Introduction <ul><li>Purpose </li></ul><ul><li>This training module provides detailed information on the MCF51QE microcontrollers. </li></ul><ul><li>Outline </li></ul><ul><ul><li>Introducing the ColdFire family </li></ul></ul><ul><ul><li>MCF51QE architecture </li></ul></ul><ul><ul><li>Introducing ColdFire Core </li></ul></ul><ul><ul><li>MCF51QE internal features </li></ul></ul><ul><ul><li>Development tools </li></ul></ul><ul><ul><li>Target Application & Application Block Diagram </li></ul></ul><ul><li>Content </li></ul><ul><ul><li>18 pages </li></ul></ul>
    3. 3. ColdFire ® Family Summary <ul><li>Compatible family of processor cores architected for SoC and reuse </li></ul><ul><ul><li>100% synthesizable and technology-independent designs since inception in 1995 </li></ul></ul><ul><ul><li>DFT emphasis for easy SoC test </li></ul></ul><ul><ul><li>Strong embedded debug architecture </li></ul></ul><ul><li>Family of cores, software compatible with M68000 family legacy </li></ul><ul><ul><li>Five generations available today covering a wide price/performance range </li></ul></ul><ul><ul><li>Generations of microarchitectures are named “versions” (Vx = CFx) – V1,V2,V3,… </li></ul></ul><ul><ul><li>Five generations have provided a 36.6x performance increase in 11 years </li></ul></ul><ul><li>CF1Core developed as the “connection point” in FSL’s Controller Continuum </li></ul><ul><ul><li>Absolute minimal implementation for low-end MCU configurations </li></ul></ul><ul><li>Configurable designs: Options in cost / performance / function </li></ul><ul><ul><li>MCU & MPU implementations, options on cache, local memory + {E}MAC, FPU, MMU </li></ul></ul><ul><li>Compatible family of platforms combining core + integrated peripherals </li></ul><ul><ul><li>CFxCore, AXBS, DMA2, INTC, FlexBus, FEC, SDRAMC, ColdFire legacy peripherals </li></ul></ul><ul><ul><li>CoProcessor interface supports acceleration at instruction- or function-level, e.g., CAU </li></ul></ul>
    4. 4. MCF51QE Family Architecture
    5. 5. Low Power Benefits <ul><ul><li>Low-power run and wait modes that enable reduced current and reduced speed modes for peripherals </li></ul></ul><ul><ul><li>Run currents </li></ul></ul><ul><ul><ul><li>27 mA (50MHz CPU, 3V VDD ) </li></ul></ul></ul><ul><ul><ul><li>50 µA (32KHz CPU, 3V VDD) </li></ul></ul></ul><ul><ul><li>Two ultra-low-power stop modes </li></ul></ul><ul><ul><ul><li>Stop 2 - 370 nA </li></ul></ul></ul><ul><ul><ul><li>Stop 3 - 520 nA </li></ul></ul></ul><ul><ul><li>Fast start-up from Stop mode (6 µs) </li></ul></ul><ul><ul><li>Flash programming from 1.8V to 3.6V </li></ul></ul><ul><ul><li>Low-power ADC </li></ul></ul><ul><ul><li>Flexible Clock Modules </li></ul></ul>
    6. 6. V1 ColdFire Core Features <ul><li>Architecture </li></ul><ul><ul><li>Variable-length RISC architecture and implementation </li></ul></ul><ul><ul><li>Supports Revision C of the ColdFire Instruction Set Architecture </li></ul></ul><ul><ul><li>Implementation contains 24-bit address and 32-bit data paths </li></ul></ul><ul><ul><li>Support for optional execute engines </li></ul></ul><ul><li>Programming Model </li></ul><ul><ul><li>Supports the standard ColdFire user programming model with 16 general purpose, 32-bit data and address registers, PC and Condition Code Register </li></ul></ul><ul><ul><li>Simplified supervisor programming model adds status register, supervisor stack pointer, vector base register, and CPU configuration register </li></ul></ul><ul><li>Performance and Power </li></ul><ul><ul><li>Up to 50 MHz core frequency in a low-voltage, low-power </li></ul></ul><ul><ul><li>0.25-micron process technology </li></ul></ul><ul><ul><li>0.85 Dhrystone 2.1 MIPS per MHz performance when executing from flash, 1.05 DMIPS per MHz when executing from RAM </li></ul></ul><ul><ul><li>Aggressive clock gating reduces power dissipation </li></ul></ul>
    7. 7. ColdFire Core Architecture
    8. 8. Rapid General Purpose Input/Output (RGPIO)
    9. 9. Interrupt Controller <ul><li>The priorities of the interrupt requests between comparable HCS08 and V1 ColdFire devices are identical. </li></ul><ul><li>Supports a mode of operation (via software convention with hardware assists) equivalent to the S08’s interrupt processing with only one level of nesting. </li></ul><ul><li>Leverages the current ColdFire interrupt controller programming model and functionality, but with a minimal hardware implementation and cost. </li></ul>
    10. 10. Peripherals <ul><li>24-channel, 12-bit ADC </li></ul><ul><li>2 Analog Comparators </li></ul><ul><li>2 Serial Communications Interface (SCI/UART) </li></ul><ul><li>2 Serial Peripheral Interface (SPI) </li></ul><ul><li>2 I²C </li></ul><ul><li>Timers </li></ul><ul><ul><li>One 16-bit, 6-channel timer </li></ul></ul><ul><ul><li>Two 16-bit, 3-channel timer </li></ul></ul><ul><ul><li>Input Capture, Output Compare and PWM for improved motor control </li></ul></ul><ul><ul><li>Real Time Clock </li></ul></ul>
    11. 11. Memory Map <ul><li>Fixed address memory map </li></ul><ul><ul><li>Restricted to 24-bit address = 16 Mbyte space </li></ul></ul><ul><ul><li>Shown as 32-bit value: 0x(ss)nn_nnnn where ss = {00,ff} </li></ul></ul><ul><li>Standardized map </li></ul><ul><li>Efficiently supports use of short-a5-relative addressing mode (d16,A5) for all data memory accesses. </li></ul>
    12. 12. Programming Model <ul><li>User Programming Model </li></ul><ul><ul><li>16 x 32-bit General Purpose Registers </li></ul></ul><ul><ul><ul><li>- 8 Data Registers, D0-D7 </li></ul></ul></ul><ul><ul><ul><li>- 8 Address Registers, A0-A7 </li></ul></ul></ul><ul><ul><li>32-bit Program Counter (PC) </li></ul></ul><ul><ul><li>8-bit Conditional Code Register (CCR) </li></ul></ul><ul><li>Supervisor Programming Model </li></ul><ul><ul><li>User programming model plus… </li></ul></ul><ul><ul><ul><li>- Status Register (SR) </li></ul></ul></ul><ul><ul><ul><li>- Supervisor Stack Pointer (Other_A7) </li></ul></ul></ul><ul><ul><ul><li>- Vector Base Register (VBR) </li></ul></ul></ul><ul><ul><ul><li>- CPU Configuration Register (CPUCR) </li></ul></ul></ul>S bit
    13. 13. MCF51QE128 Series Comparison 80LQFP 64LQFP 64LQFP Package 16 16 16 KBI Yes Yes Yes ICS Up to 24 20 20 ADC Channels 2 2 2 I²C 8 Kb 8 Kb 8 Kb SRAM 128 Kb 64 Kb 32 Kb Flash V1 Cold Fire Core V1 Cold Fire Core V1 Cold Fire Core Core MCF51QE128 MCF51QE64 MCF51QE32 Features
    14. 14. Development Tools EVBQE128: It can be used as a standalone application or can be controlled by a host PC via its built-in microDART™ interface. Demo Board DEMOQE128: The board supports two interchangeable plug-in daughter cards to quickly evaluate the 8-bit S08 and 32-bit ColdFire V1 QE128 microcontrollers.
    15. 15. CodeWarrior Development Studio for Microcontrollers v6.0 <ul><li>CodeWarrior Development Studio provides everything the professional embedded developer needs: </li></ul><ul><ul><li>CodeWarrior C/C++ Compiler Suite </li></ul></ul><ul><ul><li>Runtime Libraries </li></ul></ul><ul><ul><li>Assembler </li></ul></ul><ul><ul><li>Standard Template Library (STL) </li></ul></ul>
    16. 16. Target Applications
    17. 17. Application Block Diagram: Blood Pressure Monitor
    18. 18. Additional Resource <ul><li>For ordering the MCF51QE MCUs, please click the part list or </li></ul><ul><li>Call our sales hotline </li></ul><ul><li>For additional inquires contact our technical service hotline </li></ul><ul><li>For more product information go to </li></ul><ul><ul><li>http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=MCF51QE&nodeId=0162468rH3YTLC00M924B2 </li></ul></ul>

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