eCOG1X 16-bit Microcontrollers

  • 301 views
Uploaded on

Introduction of the eCOG1X 16-bit microcontroller and its key features

Introduction of the eCOG1X 16-bit microcontroller and its key features

More in: Technology , Business
  • Full Name Full Name Comment goes here.
    Are you sure you want to
    Your message goes here
    Be the first to comment
No Downloads

Views

Total Views
301
On Slideshare
0
From Embeds
0
Number of Embeds
0

Actions

Shares
Downloads
0
Comments
0
Likes
1

Embeds 0

No embeds

Report content

Flagged as inappropriate Flag as inappropriate
Flag as inappropriate

Select your reason for flagging this presentation as inappropriate.

Cancel
    No notes for slide
  • Welcome to the training module on Cyan eCOG1X 16-bit Microcontrollers. This training module introduces the eCOG1X 16-bit microcontroller, and its key features.
  • eCOG1X is a member of the Cyan Technology eCOG1 family of low cost, low power microcontrollers targeting embedded communications applications. The eCOG1X product family is a range of low-power, feature rich microcontrollers based on a 16-bit Harvard architecture with a 24-bit linear code address space (32Mbyte) and 16-bit linear data address space (128Kbytes).  The devices are highly configurable, with options including combinations of USB 2.0 OTG interface, 10/100 Mbps Ethernet MAC and 12-bit analogue I/O. Each variant is available with 512Kbytes of Flash and 24Kbytes of SRAM.
  • Here is the block diagram of the eCOG1x microcontroller. The eCOG1X flash based microcontroller contains a 16-bit RISC processor with powerful mathematical instructions. There are 512Kbytes (256K x 16 bits) of embedded flash memory and 24Kbytes (12K x 16 bits) of internal SRAM available on-chip, which can be used for both code and data storage. The internal Memory Manager maps both internal and external physical memories into the code and data space address maps of the CPU. The eCOG1X has a rich set of serial peripherals, including UARTs, I2C, SPI, smart card and infra-red protocol engines. A full set of hardware timer functions is available in eCOG1X, providing eight independent timers capable of performing functions such as clock generation, PWM generation and infrared signal modulation. The external host interface (EHI) enables fast data transfer between eCOG1X and an external microprocessing device. The eCOG1X includes an Ethernet MAC peripheral which can be used with a suitable external PHY device. USB 2.0 compatible peripheral supporting low speed, high speed and On-The-Go modes.
  • The eCOG1X has an advanced high speed, low power CPU with a powerful instruction set targeted at high level languages, in particular C. The CPU is capable of operating at speeds up to 70MHz. The CPU has a Harvard architecture, which means it has separate buses for code and data spaces. The eCOG1 instruction set includes 42 instructions with 6 addressing modes. Most instructions operate on 16-bit word data value.
  • The Memory Management Unit (MMU) allows the combination of a variety of internal and external memories into a single logical memory structure. The memory structure, or memory model, has both code space and data space address locations, because the Harvard architecture CPU has a separate code and data bus. The MMU provides code space translations for program code, and data space translations for variables and constants. The translation of logical memory addresses to physical memory addresses is required as almost all physical memories start with an address of 0x0000. To avoid any address conflicts due to common memory base addresses and to create a linear address range, a logical memory address to physical memory address translation is provided by the MMU.
  • Next few pages gives an introduction of the eCOG1X device peripherals. The eCOG1X includes two identical DUART modules, DUART1 and DUART2. Each DUART module provides two separate UART channels, labelled A and B. The two UART channels in each DUART are independent; each has a 16 bit divider that produces the 16x oversampling clock enable for the receiver and the half bit time clock enable for the transmitter. The lowest possible UART input clock frequency that allows for the correct divided down baud rate should be used to minimize the power consumption.
  • The Dual Universal Synchronous Asynchronous Receiver Transmitter (DUSART) is a general purpose dual serial port, each of which can support one of the many fixed protocols. It also provides hooks so that simple serial protocols can be defined by software. The hardware design has generic serial functions shared between a number of different protocol controllers. The generic USART serial port is duplicated for each channel and shared between each protocol control engine using an array of multiplexers. This allows any of the protocols to be selected for either channel, allowing for maximum flexibility. Note that each serial protocol may only be used once, the same protocol cannot be used simultaneously on both channels.
  • The Serial Peripheral Interface (SPI) is one of the protocols supported by the DUSART module. This gives the eCOG1X both SPI master and slave capability with the option of supporting multiple slaves in master mode. Only a master can initiate a transmission and the master provides the clock for the transfer (SCLK). A slave must use the SCLK provided by the master for the transfer. Some support logic is included in the SPI top level design to distinguish the data directions of both controllers and to supply flow control mechanisms for linking the data ports with the controllers’ framing functions.
  • The Inter-IC Communication standard (I 2 C), is a bidirectional, multi-drop, multi-master, two wire interface for connecting microcontrollers to their peripheral devices such as memories and interface ICs. It is capable of serial data transfer up to speeds of 100kbps (standard), 400kbps (fast mode) and 3.4Mbits/s (high speed mode). The DUSART is responsible for controlling the I 2 C serial bus by handling all of the low level signaling and serialization of the data stream. This includes functions such as start and stop bit detection, address matching and arbitration, and clock synchronization. The diagram illustrates the functionality of I2C as implemented in the DUSART. It shows how I2C can be configured for either USART channel and how both USART channels and the I 2 C controller require register and peripheral interfaces to exchange control and data with the register bank.
  • The IFR function in the DUSART provides a configurable CODEC designed for the transmission and reception of infra-red data frames. Input signals should be demodulated externally before being supplied to the device for decoding. The IFR transmit data output signal may be provided both modulated and unmodulated. For a modulated output signal, the IFR transmit data output controls the PWM2 timer, and the output from this timer is the modulated data output. For an unmodulated output signal, the normal IFR transmit data output is used. The module is designed to be flexible, supporting current consumer protocols (RC-5, ASK, PPM) and potentially future infra-red protocols via a programmable register interface. An outline structure of the IFR controller module is shown in the figure.
  • The Smart Card Interface (SCI) module contains all of the logic functionality required of the terminal (controller) part of a smart card interface. Activation and deactivation sequences are supported with various degrees of (configurable) automation. Protocol type T=0 is supported, refer to the Smart Card standard ISO 7816 parts 1-10. It should be noted that while all of the necessary sequencing for card insertion, activation and deactivation is in place, there is no built-in support for voltage level switching, ‘tamper detection’ or short circuit protection. It is therefore necessary that an external interface circuit is included between the chip and the smart card terminal itself.
  • The User Serial Port (USR) module is an extension to the DUSART that allows direct software access to the features of either USART A or USART B. This port may be used as an additional UART. It is therefore possible to configure and use up to 6 separate UARTS in eCOG1X, consisting of 4 UARTS from the two dedicated DUART sections, and the UART and User Serial Port from the DUSART section. The purpose of the USR function is to provide a flexible serial I/O port, with multiple word parallel access and automatic parity insertion and checking, while minimising the required amount of software bandwidth. User defined serial protocols may be adopted by simply reconfiguring the USR register bank.
  • The I2S (Inter-IC Sound) standard bus was developed by Philips Semiconductors to provide a simple, low pin count serial link for digital audio data. I2S is a synchronous serial protocol for sending and receiving digital audio data in stereo PCM format. The eCOG1X I2S peripheral provides both master and slave capability, programmable data size and clock frequencies, and simultaneous bidirectional data transfers.
  • The LCD controller provides the eCOG1X with hardware support for driving simple static or multiplexed LCDs. The diagram shows an example connection to the microcontroller for this LCD driving scheme. The common backplane outputs must have tristate capability and the external resistors provide the third voltage level at half the power supply voltage. The segment driver outputs are standard logic outputs. The eCOG1X LCD controller peripheral uses this driving scheme, with 1 to 4 common backplane outputs and 32 segment outputs. It supports 1, 2, 3 or 4 way multiplexing to provide control of up to 128 display segments. The port multiplexer assigns peripheral functions to external device pins and can enable subsets of the LCD controller outputs for applications using smaller displays. The LCD controller automatically generates the required output waveforms on the backplane and segment outputs from the data values written into the segment data registers.
  • The Dual Smart Card Interface (DSCI) module provides two complete smart card interface peripherals, independent of the single SCI function available within the DUSART peripheral. The two SCI cores in DSCI are identical and are independent except for the shared clock and interrupt signals. The data input and output signals can be linked by the port configurator into a single bidirectional open-drain signal or left as two separate signals, as appropriate for the hardware interface to any particular smart card.
  • The eCOG1X includes an Ethernet MAC peripheral which can be used with a suitable external PHY device. Both the transmit and receive data paths have their own separate 128 byte FIFO to provide data flow buffering. Data packets are stored in internal SRAM, accessed via the DMA controller. The EMAC peripheral is controlled through a set of control/status registers (CSRs), located at an address defined by the MMU.
  • The eCOG1X includes a USB 2.0 compatible peripheral module. It operates in USB host and peripheral modes, with support for On-The-Go functions. It supports low speed (1.5Mb/s), full speed (12Mb/s), and high speed (480Mb/s) modes. The USB core requires 4Kbytes of working memory, used for the endpoint data buffers. This is taken from the top of the internal memory and cannot then be accessed directly by the processor. Reading and writing to this memory is always done either through the USB core FIFO registers or with the DMA peripheral and the slave FIFO.
  • The eCOG1X includes a flexible analogue control interface peripheral (ACI) providing analogue inputs and outputs. Both channels of the ADC are identical, except for the two internal analogue signals which are connected separately, one to each ADC channel multiplexer. Both ADC channels have their input signals connected via an eight-way analogue multiplexer. The DAC is an asynchronous two channel 12-bit Digital to Analogue Converter. The ACI module includes an internal bandgap voltage reference, nominally 1.22V, for use with the ADCs and DACs. The analogue block also includes a power on reset module which senses the analogue supply voltage. The internal voltage reference circuit also generates a voltage linearly proportional to temperature; this internal signal is available to the ADC as a temperature sensor input.
  • Thank you for taking the time to view this presentation on “ eCOG1X 16-bit Microcontrollers ” . If you would like to learn more or go on to purchase some of these devices, you may either click on the part list link, or simply call our sales hotline. For more technical information you may either visit the Cyan site – link shown – or if you would prefer to speak to someone live, please call our hotline number, or even use our ‘live chat’ online facility.

Transcript

  • 1. eCOG1X 16-bit Microcontrollers
    • Source: Cyan Technology
  • 2. Introduction
    • Purpose
      • This training module introduces the eCOG1X 16-bit microcontroller, and its key features.
    • Outline
      • Device overview
      • Block diagram
      • Key features
    • Content
      • 20 pages
  • 3. Overview
    • 70MHz, 16 bit Harvard architecture CPU
    • Powerful instruction set
    • Memory management unit combines internal and external memories transparently into single memory map
      • 512K bytes (256K x 16 bits) of embedded flash memory
      • 24K bytes (12K x 16 bits) of internal high-speed SRAM
    • 10/100 Mbits/s Ethernet MAC with standard MII interface
    • USB 2.0 compatible peripheral supporting low speed, high speed and On-The-Go modes
    • Dual independent synchronous/asynchronous multi-protocol serial ports supporting any two of I2C, SPI, smart card, infra-red and user defined serial protocols
    • 2 x dual UARTs
    • 4x32 LCD Controller
    • Two channel 12-bit successive approximation ADC
    • Two channel 12-bit DAC
  • 4. Block Diagram
  • 5. CPU
    • 16-bit RISC
    • Sleep mode to support low power applications
    • Harvard architecture (separate address and data buses for faster memory accesses)
    • 16-bit data space addressing range (64Kbytes)
    • 25-bit code space addressing range (32Mbytes)
    • Support for debugging and multiple breakpoints
    • Single level of interrupt
    • Powerful mathematical functions including:
      • 16 by 16 signed and unsigned multiply
      • 32 by 16 unsigned divide
      • Single cycle barrel shifter
  • 6. Memory Management Unit (MMU) CPU Core Internal FLASH Internal SRAM External Memory MMU External Memory Internal Flash External Memory Internal SRAM Code Data CPU Core Physical to Logical Translation
  • 7. Peripherals – DUART
    • Frame sizes of 5, 6, 7 or 8 bits of data
    • Receive timeout detection of 1 to 63 bit periods
    • Prescaled UART clock to reduce power consumption
    • Programmable bit rate generator
    • 8-bit and 16-bit transmit data registers & 8-bit receive data register
    • Operates completely independently of the CPU
  • 8. Peripherals - DUSART
    • The following protocols are supported by the DUSART peripheral:
      • Standard UART
      • Serial Peripheral Interface (SPI)
      • I 2 C multi-master, multi-drop 2 wire bus
      • Low rate IrDA and general purpose infrared controller protocol (IFR)
      • ISO 7816 smart card interface (SCI)
      • Generic User Serial Port (USR)
  • 9. DUSART – Serial Peripheral Interface (SPI)
    • The SPI function includes the following features:
      • Master and slave operation
      • Programmable serial clock polarity and phase
      • Data transfer size 1 to 16 bits
      • Programmable serial clock frequency (master mode)
      • Up to four chip select outputs (master mode)
      • Slave mode chip select uses up to four inputs with a pattern match and mask function.
  • 10. DUSART – Inter-IC Communication standard (I 2 C)
    • The I 2 C function includes the following features:
      • Start, stop, and restart operations
      • Address matching and arbitration
      • Supports multi-master and master/slave operations
      • Automatic acknowledge generation
      • 7 bit, 10 bit and broadcast addressing
  • 11. DUSART – Infra-Red Interface (IFR)
    • A configurable CODEC for the transmission and reception of infra-red data frames.
    • Input signals should be demodulated externally before being supplied to the device for decoding.
    • The data output signal may be provided both modulated and unmodulated.
  • 12. DUSART – Smart Card Interface (SCI)
    • The SPI function includes the following features
      • Card activation sequencer with hardware delay timer
      • Card deactivation sequencer with hardware delay timer
      • Data transmit sequencer with hardware guard time, error detection and retransmission
      • Data receive sequencer with hardware error detection and retransmit request
      • Programmable signal polarities
      • UART serial port operation
      • Normal or inverse data convention
  • 13. DUSART – User Serial Port (USR)
    • The USR function includes the following features
      • Provides direct access to internal USART features
      • Allows custom serial protocols to be emulated
      • Up to 255 symbols per frame
      • Automatic parity generation and checking
      • Start bit edge detection
      • Transmit and receive data interrupts.
  • 14. Peripherals – Inter-IC Sound (I 2 S)
    • The I 2 S peripheral has the following main features
      • Programmable data word size up to 32 bits for each channel
      • Internal or external clock source
        • Internal clock source is set in the SSM
        • Alternate clock input supports frequencies that cannot be achieved by the SSM
      • Master or slave mode
        • The master device outputs SCLK and WS to the slave device
        • Selection of master or slave mode is independent of the clock source selection
      • Master clock output, required by some CODECs for oversampling and digital filtering
        • MCLK frequency = selected input clock frequency
      • Programmable divider for bit clock SCLK
      • Word select clock WS is set according to the number of data bits selected
        • WS clock frequency = SCLK frequency divided by number of data bits x 2 (stereo audio has two data values per sample)
      • Programmable clock and data signal polarities.
  • 15. Peripherals – LCD Controller
    • The LCD controller peripheral has the following main features.
      • For use with simple static and multiplexed LCDs
      • 32 segment and 4 backplane (common) driver outputs
      • Supports 1, 2, 3 or 4 way multiplexing
      • Provides continuous control of up to 128 display segments
      • Automatic display operation with static data
      • Programmable 8-bit input clock prescaler
      • The port multiplexer can enable subsets of the segment outputs
  • 16. Peripherals – Dual Smart Card Interface (DSCI)
    • The DSCI peripheral has the following main features.
      • Two independent smart card interface blocks.
      • Flexible smart card clock generation with support for clock stop.
      • Dedicated serial port for each smart card.
      • Card activation and deactivation sequences, with manual or automatic start on card insertion and removal.
      • Flexible software interface with interrupt support.
  • 17. Peripherals – Ethernet MAC
    • The main features of the EMAC peripheral include:
      • Supports both 10Mbits/s and 100Mbits/s operation with the appropriate external PHY device fitted
      • Media Independent Interface (MII) for PHY device configuration
      • Complies with IEEE 802.3 CSMA/CD standard
      • Single address filtering
      • Buffer descriptors may be arranged as a ring or a chain
    • The EMAC peripheral contains four main functional blocks:
      • Control/status registers
      • DMA controller
      • Transmit data path
      • Receive data path.
  • 18. Peripherals – USB Interface
    • The USB core in the eCOG1X offers the following features:
      • Low speed (LS), Full Speed (FS) and High Speed (HS) operation
      • USB host, peripheral and On-The-Go (OTG) use
      • Internal PHY for LS, FS and OTG operation
      • ULPI interface for use with external HS PHY
  • 19. Analog Functions
    • Two-channel successive approximation Analogue to Digital Converter (ADC)
      • Simultaneous sampling on the two ADC channels
      • Maximum conversion rate of 200ks/s at 12 bits resolution
    • Two-channel 12-bit Digital to Analogue Converter (DAC)
    • Internal 1.2V nominal bandgap voltage reference
    • Power on reset and low I/O supply voltage sensor
    • Internal temperature sensor and analogue supply voltage sensor
    • Analogue multiplexer with one internal and seven external input signals for each ADC
    • Single-ended and differential input configurations
  • 20. Additional Resource
    • For ordering eCOG1X MCUs, please click the part list or
    • Call our sales hotline
    • For additional inquires contact our technical service hotline
    • For more product information go to
      • http://www.cyantechnology.com/mcu/mcu_eCOG1X.php