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Cyclone III FPGA Overview Part2
Cyclone III FPGA Overview Part2
Cyclone III FPGA Overview Part2
Cyclone III FPGA Overview Part2
Cyclone III FPGA Overview Part2
Cyclone III FPGA Overview Part2
Cyclone III FPGA Overview Part2
Cyclone III FPGA Overview Part2
Cyclone III FPGA Overview Part2
Cyclone III FPGA Overview Part2
Cyclone III FPGA Overview Part2
Cyclone III FPGA Overview Part2
Cyclone III FPGA Overview Part2
Cyclone III FPGA Overview Part2
Cyclone III FPGA Overview Part2
Cyclone III FPGA Overview Part2
Cyclone III FPGA Overview Part2
Cyclone III FPGA Overview Part2
Cyclone III FPGA Overview Part2
Cyclone III FPGA Overview Part2
Cyclone III FPGA Overview Part2
Cyclone III FPGA Overview Part2
Cyclone III FPGA Overview Part2
Cyclone III FPGA Overview Part2
Cyclone III FPGA Overview Part2
Cyclone III FPGA Overview Part2
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Cyclone III FPGA Overview Part2

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Overview of the major features of the Cyclone III family FPGA with emphasis on areas that are new or changed from the Cyclone II family

Overview of the major features of the Cyclone III family FPGA with emphasis on areas that are new or changed from the Cyclone II family

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  • 1. Cyclone III FPGA Overview Part II
    • Source: Altera Corporation
  • 2. Introduction
    • Purpose
      • This module will overview the major features of the Cyclone III family FPGA with emphasis on areas that are new or changed from the Cyclone II family.
    • Outline
      • Give some insight into what new applications and capabilities features provide
    • Contents
      • 25 pages
    • Duration
      • 20 Minutes
  • 3. Memory Interfaces That Automatically Calibrate, Track, and Adjust 
    • Intellectual property (IP) auto calibrates for process differences
      • For both FPGA and memory
      • Removes timing uncertainties
    • Monitors voltage and temperature variations
      • Adjusts resynchronization phase (PLL output)
      • Does not interrupt operation
      • Supports DDR, DDR2, QDR II memories
  • 4. MegaCore Ease of Use
    • Configures Altera controller and physical interface megafunction PHY
  • 5. Full Rate Controller
  • 6. Half Rate Controller
    • Simplify design requirements by halving application side frequency and doubling data width
    • Example: 75MHz Nios II core operating with 150 MHz DDR2 memory
    •  
  • 7. Dedicated Differential Output Buffers
    • Dedicated LVDS Output Buffers on the left and right banks
      • Increased performance, 840 Mbps
      • No external resistors required
    • Improved LVDS Input Buffers on all banks
      • Increased performance, 875 Mbps  
  • 8. OCT With Calibration
    • Output buffer impedance may vary slightly due to PVT
    • With OCT Calibration, after configuration the output buffer impedance is automatically adjusted to match two external resisters (RUP & RDN), which are either 50 Ohms or 25 Ohms
    • Designer uses Quartus II software assignment editor to make a <Termination> assignment, with a value of <Series 50 Ohms with Calibration> or <Series 25 Ohms with Calibration >
  • 9. Cyclone III I/O Interface Guidelines
    • Cyclone III devices can drive out and receive 1.2V - 3.3V signals directly
      • Drive out 3.3V LVTTL at up to 8mA and 3.3V LVCMOS at up to 2mA
    • For higher drive strengths at 3.3V and PCI/PCI-X interfaces use 3.0V VCCIO
      • Cyclone III 3.0V I/O standards meet the 3.3V I/O standards specifications defined by EIA/JEDEC Standard JESD8-B
  • 10. Clocking Resources
    • Clock routing resources
      • Up to 20 global clocks
      • Global clock routing can also be used for global signals
      • Powered down when not in use to save power
    • Full-featured and robust PLLs
      • Up to four low-jitter (200 ps) PLLs
      • Five programmable outputs per PLL
      • Wide frequency range of 5 to 440 MHz
      • Dynamically change both frequency and phase
      • Cascadable to allow broader frequency generation
  • 11. Cyclone III: PLLs
  • 12. Cascading PLLs
  • 13. PLL Dynamic Phase Adjustment
    • Dynamic adjustment of PLL phase setting
    • Increase / decrease 1 step at a time
      • Step increments depend on PLL configuration
  • 14. Clock Switch Over
    • Automatically switch from 1 clock to another in the event a clock stops
    • Manually switch from 1 clock source to another
  • 15. PLL Modes
  • 16. PLLs: Maximum System Integration
    • Low Cost
      • Up to 10 internal & 2 external clocks from 1 clock source
      • Support for low cost 5 MHz clock inputs
    • Flexibility
      • Support multiple or unknown input frequencies in
      • Display application using dynamic reconfiguration
      • PLL cascading feature without going off chip
    • External memory interface support
      • X72 DDR/DDR2 interfaces using a single PLL
      • Dynamic phase adjustments for DQS capture alignment
  • 17. Cyclone III: Clocking and PLLs
  • 18. Configuration Mode Overview
  • 19. Understanding Configuration Timing
    • Application with fast “Wake-up” time specification needs to utilize fast POR time and fast configuration modes
    • POR time and configuration time user configurable with mode select pins(MSEL3..0)
    • Fast POR option requires fast* Vcc ramp
  • 20. Remote System Upgrade
  • 21. Programming Flash in System
    • Program or examine Flash device from Quartus II programmer window
      • Cyclone III works as a Flash programmer with Flash loader SOF
      • Quartus II downloads SOF automatically & programs Flash
    • Eliminates additional hardware and software for on board Flash programming
      • Unique tool for Altera
  • 22. Cyclone III Family
  • 23. Nios II Embedded Processor
    • Choose the exact set of CPUs, peripherals, and memory you need for your application
      • Achieve over 160 DMIPs of performance
      • Build custom instructions
      • Accelerate with hardware—C2H compiler automatically converts C subroutines into hardware for Nios II embedded processor
    • Low cost
      • Integrate your peripherals and microprocessor into a single chip
      • Support for multiple processors in a single device
      • Implement a processor on a Cyclone III FPGA
  • 24. Quartus II Design Software
    • Industry-leading software for performance and productivity
      • Supports all Cyclone III devices in free Web Edition
        • Including the EP3C120, largest FPGA in its class
    • Key features
      • PowerPlay technology to reduce power up to 25 percent
      • TimeQuest timing analyzer for easy timing closure
      • DSP Builder to rapidly bring your DSP design into hardware
      • SOPC Builder to rapidly and easily build whole systems
  • 25. Cyclon III Base Kits
    • Cyclone III FPGA Start Kit
      • Cyclone III EP3C25F324 FPGA
      • HSMC connector
      • On-board memories
      • 256 Mbit DDR
      • 1 Mbyte Sync SRAM
      • 16 Mbyte Flash
    • Cyclone III Dev Kits
      • Cyclone III EP3C120F780 FPGA
      • 2x HSMC connector
      • 10/100/1000 Ethernet
      • On-board memories
      • 256Mbit DDR2
      • 8 Mbyte Sync SRAM
      • 64 Mbyte Flash
    Figure 1 Start Kit Dev Kit
  • 26. Additional Resource
    • For ordering the Cyclone III family FPGA , please click the part list or
    • Call our sales hotline
    • For additional inquires contact our technical service hotline
    • For more product information go to
    • http://www.altera.com/products/devices/cyclone3/cy3-index.jsp

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