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An Study on DS91M125 125 MHz 1:4   M-LVDS Repeater with LVDS Input
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An Study on DS91M125 125 MHz 1:4 M-LVDS Repeater with LVDS Input

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Study on DS91M125 125 MHz 1:4 M-LVDS Repeater with LVDS Input …

Study on DS91M125 125 MHz 1:4 M-LVDS Repeater with LVDS Input

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  • Welcome to the training module on the DS-91-M-125, 125 MHz 1:4 M-LVDS Repeater with LVDS Input by National Semiconductor.
  • In this module we will discuss the features, logic diagrams, driver parameters, multipoint network and application.
  • This is the Logic diagram of the DS91M125 device. It has one Differential Input and four LVDS output. Each output has an associated independent driver enable pin as shown here.
  • The DS91M125 is a 1:4 M-LVDS repeater designed for driving and distributing clock or data signals to up to four multipoint networks. Multipoint LVDS or M-LVDS is a new family of bus interface devices based on LVDS technology that is specifically designed for multipoint and multi drop cable and backplane applications. It differs from standard LVDS in providing increased drive current to handle double terminations that are required in multi-point applications. Controlled transition times minimize reflections that are common in multipoint configurations due to un-terminated stubs. A single DS91M125 channel is a 1:4 repeater that accepts M-LVDS/LVDS/CML/LVPECL signals and converts them to M-LVDS signal levels. The DS91M125 has a flow-through pin out for easy PCB layout. It provides a new alternative for high speed multipoint interface applications. It is packaged in a space saving SOIC-16 package.
  • The DS91M125 devices can be used in applications where Multidrop Multipoint clock and Data Distribution is required and High-Speed, Low Power, Short-Reach application.
  • Here we show a comparison of key RS-485, M-LVDS, and LVDS driver characteristics.
  • Here shows the receiver types comparing the standard RS-485, and LVDS signals. M-LVDS has 2 types of receiver types. Type 1 has the threshold level centered at 0V differential and gives higher noise margin. Type-2 receiver has threshold level shifted by +100mV differential.
  • The M-LVDS Receivers intended for general data transport over multipoint bus where up to 32 Nodes can be connected. M-LVDS Standard specifies Maximum signaling rate of 500Mbps based on 1 ns minimum transition time. M-LVDS drivers has stronger drive current (IOD) This enables this device to drive signals across multipoint network that are typically doubly terminated.
  • Here we show Test Circuit for Differential Driver application.
  • Here we show Test Circuit for Differential Driver Full Load application.
  • Here we show Test Circuit for Driver Tri-State Delay application.
  • Shown are the typical Performance curve of the device V by S. There is the Driver Propagation by temperature and Driver Rise Time by Temperature.
  • M-LVDS devices are primarily used in clock distribution networks such as clock distribution interfaces of AdvancedTCA (ATCA) and MicroTCA (μTCA) based systems. AdvancedTCA (ATCA) based systems require synchronization of its internal and external networks. Synchronization Clock Interface is a section of the ATCA Base Specification (PICMG 3.0) that specifies M-LVDS as the signalling technology of choice. In an ATCA system, there are three redundant clocks (totalling 6) distributed to up to 16 backplane slots in a multipoint fashion: • CLK1A and CLK1B are for redundant 8 kHz standard digital telephony transmission system clocks. • CLK2A and CLK2B are for 19.44 MHz clocks for synchronization of the SONET/SDH networks. • CLK3A and CLK3B are for user-defined signals (clock or data).
  • Thank you for taking the time to view this presentation on DS91M125 . If you would like to learn more or go on to purchase some of these devices, you may either click on the part list link, or simple call our sales hotline. For more technical information you may either visit the National Semiconductor Corporation site, or if you would prefer to speak to someone live, please call our hotline number, or even use our ‘live chat’ online facility.

Transcript

  • 1. An Study on DS91M125 125 MHz 1:4 M-LVDS Repeater with LVDS Input
        • Source: National Semiconductor
  • 2. Introduction
    • Purpose
      • Study on DS91M125 125 MHz 1:4 M-LVDS Repeater with LVDS Input
    • Outline
      • Logic Diagram
      • Features
      • Application and ATCA block diagram
      • Comparison of Key Driver Parameters
      • Multipoint Network
    • Content
      • 14 pages
  • 3. Logic Diagram
    • The DS91M125 is a 1:4 M-LVDS repeater designed for driving and distributing clock or data signals
    • A single DS91M125 channel is a 1:4 repeater that accepts M-LVDS/LVDS/CML/LVPECL signals and converts them to M-LVDS signal levels.
    • Each output has an associated independent driver enable pin.
  • 4. Features ■ DC - 125 MHz / 250 Mbps low jitter, low skew, low power operation ■ Independent Driver Enable pins ■ Outputs Conform to TIA/EIA-899 M-LVDS Standard ■ Controlled transition times minimize reflections ■ Inputs Conform to TIA/EIA-644-A LVDS Standard ■ 8 kV ESD on M-LVDS output pins protects adjoining components ■ Flow-through pin out simplifies PCB layout ■ Industrial operating temperature range (−40°C to +85°C) ■ Available in a space saving SOIC-16 package
  • 5. Applications
    • ■ Multidrop / Multipoint clock and data distribution.
    • ■ High-Speed, Low Power, Short-Reach alternative to
    • TIA/EIA-485/422.
    • ■ Clock distribution in AdvancedTCA (ATCA) and MicroTCA (μTCA, uTCA) backplanes.
  • 6. Comparison of Key Driver Parameters
  • 7. M-LVDS Standard Receiver Types
    • The input threshold levels differentiate the two types of M-LVDS receivers.
    • Type 1 receivers have threshold levels centred at 0V differential and provide higher noise margin than Type 2 receivers.
    • Type 1 receivers are used in clock or data transmission applications
    • Type 2 receivers have threshold levels shifted by +100 mV differential.
    • Type 2 receivers are used in the failsafe, Wired-OR function.
  • 8. Multipoint Network
    • The M-LVDS Receivers intended for general data transport over multipoint bus where up to 32 Nodes can be connected.
    • M-LVDS Standard specifies Maximum signaling rate of 500Mbps based on 1 ns minimum transition time.
    • M-LVDS drivers has stronger drive current (IOD) This enables this device to drive signals across multipoint network that are typically doubly terminated.
  • 9. Differential Driver Test Circuit Differential Driver Test Circuit Differential Driver Waveforms
  • 10. Differential Driver Full Load Test Circuit Differential Driver Full Load Test Circuit Differential Driver DC Open Test Circuit
  • 11. Driver Tri-State Delay Test Circuit Driver Tri-State Waveforms Driver Tri-State Delay Test Circuit
  • 12. Typical Performance Curves Driver Propagation V/S Temperature Driver Rise Time V/S Temperature
  • 13. AdvancedTCA (ATCA) Clock Distribution Interface
  • 14. Additional Resource
    • For ordering the DS91M125, please click the part list or
    • Call our sales hotline
    • For additional inquires contact our technical service hotline
    • For more product information go to
      • http://www.national.com/pf/DS/DS91M125.html#General%20Description