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An Overview of LPC2101/02/03
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An Overview of LPC2101/02/03



This training module provides an overview of LPC2101/02/03 microcontrollers, their key features, and applications.

This training module provides an overview of LPC2101/02/03 microcontrollers, their key features, and applications.



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    An Overview of LPC2101/02/03 An Overview of LPC2101/02/03 Presentation Transcript

    • An Overview of LPC2101/02/03
      • Source: NXP
    • Introduction
      • Purpose
        • This training module provides an overview of LPC2101/02/03 microcontrollers, their key features, and applications.
      • Outline
        • Introduction
        • Selection guide
        • Applications
        • Block diagram
        • Key features
      • Content
        • 20 pages
    • General Description
      • 16/32bit ARM7TDMI-S microcontroller
      • Fast 70MHz Performance at 63 Dhrystone MIPs
      • FLASH Program Memory Size 8K x 8
      • RAM Size 2K x 8
      • 32 Input/Output Port (GPIO)
      • 10-bit A/D converters provides eight analog inputs
      • Two 32-bit timers/external event counters
      • Two 16-bit timers/external event counters
      • Low power Real-Time Clock (RTC) with dedicated 32 kHz clock input
      • Multiple serial interfaces including two UARTs (16C550)
      • Two Fast I2C-buses (400 kbit/s), SPI and SSP  
      • In-System Programming (ISP) and In-Application Programming (IAP)
      • Operating voltage range of 1.65 V to 1.95 V (1.8 V ± 0.15 V).
    • Comparison Table PLCC44, LPFP48 (2) I 2 C, (2) UARTs (1) SPI, (1) SPI/SSP 8ch / 10-bits 8KB 32KB LPC2103 PLCC44, LPFP48 (2) I 2 C, (2) UARTs (1) SPI, (1) SPI/SSP 8ch / 10-bits 4KB 16KB LPC2102 PLCC44, LPFP48 (2) I 2 C, (2) UARTs, (1) SPI, (1) SPI/SSP 8ch / 10-bits 2KB 8KB LPC2101 Packages Serial Interfaces ADC RAM Flash Product
    • Applications
      • • Industrial control
      • • Medical systems
      • • Access control
      • • Point-of-sale
      • • Communication gateway
      • • Embedded soft modem
      • • General purpose applications
    • Block Diagram
    • ARM7 Core
      • The ARM7TDMI-S is a general purpose 32-bit microprocessor, which offers high performance and very low power consumption.
      • The ARM architecture is based on Reduced Instruction Set Computer (RISC) principles.
      • ARM7TDMI-S employs Pipeline techniques to operate memory systems and all parts of the processing continuously.
      • The ARM7TDMI-S processor employs a THUMB architecture, which makes it ideally suited to high-volume applications with memory restrictions and code density.
      • ARM7TDMI-S processor has two instruction sets:
        • The standard 32-bit ARM instruction set.
        • A 16-bit THUMB instruction set
      • The particular flash implementation in the LPC2101/02/03 allows for full speed execution also in ARM mode.
    • Memory Acceleration Module (MAM)
      • It includes three 128-bit buffers called the Prefetch Buffer, the Branch Trail Buffer and the Data Buffer
      • The Memory Accelerator Module is divided into several functional blocks:
        • A Flash Address Latch and an incrementing function to form prefetch addresses
        • A 128-bit Prefetch Buffer and an associated Address latch and comparator
        • A 128-bit Branch Trail Buffer and an associated Address latch and comparator
        • A 128-bit Data Buffer and an associated Address latch and comparator
        • Control logic
        • Wait logic
    • Memory Organisation On-chip Flash program memory On-chip Static RAM
    • Watchdog Timer (WDT) • Internally resets chip if not periodically reloaded. • Supports Debug mode. • Watchdog timer is enabled by software but requires a hardware reset or a watchdog reset/interrupt to be disabled. • Incorrect/Incomplete feed sequence causes reset/interrupt if enabled. • Flag indicates watchdog reset. • Includes programmable 32-bit timer with internal pre-scaler. • Time period can be selected from (TPCLK x 256 x 4) to (TPCLK x 232 x 4) in multiples of TPCLK x 4.
    • Real-Time Clock
      • Measures the passage of time to maintain a calendar and clock
      • Provides Seconds, Minutes, Hours, Day of Month, Month, Year, Day of Week, and Day of Year
      • Dedicated power supply pin can be connected to a battery or to the main 3.3 V.
      • Can be used with dedicated 32 kHz oscillator or programmable prescaler from APB clock.
    • I 2 C interfaces
      • Standard I 2 C compliant bus interfaces may be configured as Master, Slave, or Master/Slave.
      • Arbitration is handled between simultaneously transmitting masters without corruption of serial data on the bus.
      • Programmable clock allows adjustment of I2C transfer rates.
      • Data transfer is bidirectional between masters and slaves.
      • Serial clock synchronization allows devices with different bit rates to communicate via one serial bus.
      • Serial clock synchronization is used as a handshake mechanism to suspend and resume serial transfer.
      • I 2 C-bus can be used for test and diagnostic purposes
    • Analog-to-Digital Converter (ADC)
      • LPC2101/02/03 has a single 10-bit successive approximation ADC with eight channels
      • Measurement range 0 V to VDD(3V3) (typically 3 V; not to exceed VDDA voltage level)
      • Each converter capable of performing more than 400,000 10-bit samples per second, 10 bit conversion time ≥ 2.44 μs
      • Burst conversion mode for single or multiple inputs
      • Optional conversion on transition on input pin or timer Match signal
      • Dedicated result register for every analog input to reduce interrupt overhead
    • Universal Asynchronous Receiver/Transmitter
      • 16 byte Receive and Transmit FIFOs.
      • Register locations conform to 16C550 industry standard.
      • Receiver FIFO trigger points at 1, 4, 8, and 14 bytes
      • Built-in fractional baud rate generator with autobauding capabilities
      • Transmission FIFO control enables implementation of software (XON/XOFF) flow control on both UARTs.
      • UART1 is equipped with standard modem interface signals. This module also provides full support for hardware flow control (auto-CTS/RTS).
    • SPI Interface
      • Single complete and independent SPI controller
      • Compliant with Serial Peripheral Interface (SPI) specification
      • Synchronous, serial, full duplex communication
      • Combined SPI master and slave
      • Maximum data bit rate of one eighth of the input clock rate
      • 8 to 16 bits per transfer
    • 16-bit Timers / External Event Counters
      • Two 16-bit timer/counters with a programmable 16-bit prescaler.
      • External event counter or timer operation.
      • Three 16-bit capture channels that can take a snapshot of the timer value when an input signal transitions. A capture event may also optionally generate an interrupt.
      • Four 16-bit match registers that allow:
        • – Continuous operation with optional interrupt generation on match.
        • – Stop timer on match with optional interrupt generation.
        • – Reset timer on match with optional interrupt generation.
      • Four external outputs per timer/counter corresponding to match registers, with the following capabilities:
        • – Set LOW on match.
        • – Set HIGH on match.
        • – Toggle on match.
        • – Do nothing on match.
    • Flash Memory System and Programming
      • Boot loader provides both In-System and In-Application programming interfaces for programming the on-chip flash memory
      • The boot loader controls initial operation after reset and also provides the means to accomplish programming of the flash memory.
      • This can be programming of a blank device, erasure and re-programming of device, programming of the flash memory by the application program in a running system.
      • In-System Programming: In-System programming (ISP) is programming or reprogramming the on-chip flash memory using the boot loader software and a serial port. This can be done when the part resides in the end-user board.
      • In Application Programming: In-Application (IAP) programming is performing erase and write operation on the on-chip flash memory, as directed by the end-user application code.
    • Embedded ICE Logic
      • No target resources are required by the software debugger in order to start the debugging session.
      • The software debugger talks via a JTAG (Joint Test Action Group) port directly to the core.
      • Instructions are inserted directly in to the ARM7TDMI-S core.
      • The ARM7TDMI-S core or the System state can be examined, saved, or changed depending on the type of instruction inserted.
      • Instructions can be executed at a slow debug speed or at a fast system speed.
    • Keil MCB2103 Evaluation Board
      • This board consist of below components:
      • NXP LPC2103 microcontroller
      • One serial interface
      • One JTAG interface
      • Analog input (via potentiometer)
      • Eight LEDs
      • Keil Evaluation Tools for ARM
    • Additional Resource
      • For ordering the LPC210x microcontrollers, please click the part list or
      • Call our sales hotline
      • For additional inquires contact our technical service hotline
      • For more product information go to
        • http://www.nxp.com/#/pip/pip=[pip=LPC2101_02_03_3,pfp=45994]|pp=[t=pip,i=LPC2101_02_03_3]|