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An Introduction to very low power 16-bit Digital Signal Controllers


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An Introduction to very low power 16-bit Digital Signal Controllers

An Introduction to very low power 16-bit Digital Signal Controllers

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  • This is an introduction to the Freescale Semiconductor very low power 16 bit Digital Signal Controllers.
  • Welcome to the training module on the very low power 16-bit Digital Signal Controllers . This training module gives a brief introduction to its features, target applications, its peripherals and block diagram of a few applications.
  • The MC56F8006/MC56F8002 series combine, on a single chip, the processing power of a digital signal processor (DSP) and the functionality of a microcontroller unit (MCU) with a flexible set of peripherals to create an extremely cost-effective solution. This device uses the 56800E core, which is based on a dual Harvard-style architecture consisting of three execution units operating in parallel. This allows as many as six operations per instruction cycle. A full set of programmable peripherals supports various applications. Any signal pin associated with these peripherals can also be used for general-purpose input/output (GPIO). Power-saving features include an extremely low-power mode and the ability to shut down each peripheral independently.
  • Here we explain about the application of this device. The MC56F8006 family is aimed at power- and cost-sensitive motor control applications, such as three-phase BLDC motors, variable frequency drives, permanent magnet synchronous motors and handheld tool motors. In addition to motor control. Targeting segments for these devices include  board-mounted digital power supplies for servers, industrial and telecom power supplies, smart power metering, and advanced lighting control in commercial buildings and factories.
  • This page shows a Block diagram of the Device and illustrates how the 56800E system buses communicate with internal memories and the IPBus interface and the internal connections among each unit of the 56800E core. The 56800E core is based on a dual Harvard-style architecture consisting of three execution units operating in parallel, allowing as many as six operations per instruction cycle. The MCU-style programming model and optimized instruction set allow straightforward generation of efficient, compact DSP and control code. The instruction set is also highly efficient for C compilers to enable rapid development of optimized control applications. The new Freescale MC56F8006 DSC family boasts a standby current of less than 1µA. Also, with the core operating at 32MHz and the peripheral clock at maximum (96MHz) with all peripherals running, the Freescale MC56F8006 draws just 50mA, which is very competitive compared to other devices with similar math processing ability.
  • This page gives you the DSC Attributes, The multiply-accumulation (MAC) operation is the fundamental operation used in the DSP. The core of the MC56F8006 series has a dual Harvard architecture optimized for MAC operations. The two operands c( ) and x( ), are directed to a multiply operation, and the result is summed. This process is built into the chip by allowing two separate data-memory accesses to feed a single-cycle MAC. The entire process must occur under program control to direct the correct operands to the multiplier and save the accumulated result as needed. Because the memory and the MAC are independent, the DSC can perform two memory moves, a multiply and an accumulate, and two address updates in a single operation cycle. As a result, DSP and MCU benchmarks execute very efficiently.
  • This page gives the Advantages of the DSC features . They are intend to reduce the cost and complexity of digital power conversion applications, such as board-mounted digital power supplies in servers, industrial and telecom power supplies, and smart power metering. The MC56F8006 has powerful signal processing capabilities which can be applied to advanced lighting control in commercial buildings and factories.
  • The ADC can perform an analog-to-digital conversion on any of the software selectable channels. In 12-bit and 10-bit mode, the selected channel voltage is converted into a 12-bit digital result. In 8-bit mode, the selected channel voltage is converted into a 9-bit digital result. When the conversion is completed, the result is placed in the data register. In 10-bit mode, the result is rounded to 10 bits and placed in the data register. In 8-bit mode, the result is rounded to 8 bits and placed in ADCR. The conversion complete flag (COCO) is then set and an interrupt is generated if the conversion complete interrupt has been enabled.
  • The programmable gain amplifier, or PGA, is intended to operate in conjuction with the on-chip analog-to-digital converter (ADC). By itself, the PGA has no useful function. When used to pre-process ADC inputs, it amplifies and converts differential signals to a single-ended value, which is passed on to the ADC for conversion to digital format. The PGA differential amplifier is a switched-capacitor (SC) circuit that amplifies a differential input signal and converts it to single-ended output.
  • The high-speed comparator module (HSCMP) provides a circuit for comparing two analog input voltages. The comparator circuit is designed to operate across the full range of the supply voltage (rail-to-rail operation). The HSCMP module is capable of generating an interrupt on either the rising or falling edge of the comparator output (or both). The interrupt request is asserted when both CMP0_SCR[IER] bit and CMP0_SCR[CFR] are set.
  • This module provides the 2X system clock frequency to the system integration module (SIM), which it uses to generate the various chip clocks. The on-chip clock synthesis module allows product design using an internal relaxation oscillator to run the device at user selectable frequencies up to 32 MHz bus clock. The on-chip clock synthesis (OCCS) module interfaces to the oscillator and PLL. This device has more options for clock generation than do the other members of the MC56F8000 family.
  • The SIM is a system catchall for the glue logic that ties together the system-on-chip. It controls distribution of resets and clocks and provides a number of control features. The OCCS configuration controls the operating frequency of the SIM master clocks. In the OCCS, either an external clock (CLKIN), a crystal oscillator, or the relaxation oscillator can be selected as the master clock source (master clock). An external clock can be operated at any frequency up to 64 MHz. The crystal oscillator can only be operated at 8 MHz. The SIM uses master clocks from the OCCS module to produce the peripheral and system (DSC core and memory) clocks. A 3x master clock input from OCCS operates at three times the system and peripheral bus rate and therefore a maximum of 96 MHz.
  • The computer operating properly (COP) module is used to help software recover from runaway code. The COP is a free-running down counter that, once enabled, is designed to generate a reset upon reaching zero. Software must periodically service the COP in order to reload the counter and prevent a reset. The COP sits on the unswitched digital supply, and can continue operation while the SoC is in partial power down mode. When the COP is enabled, each positive edge of the prescaled clock (COSC, ROSC, peripheral, or 1 kHz oscillator) causes the counter to decrement by one. If the count reaches a value of 0x0000, then the chip is reset.
  • Here we show the JTAG block diagram. The JTAG port has four read/write registers: Instruction Register (JTAGIR), Chip Identification (CID) register, Bypass Register (JTAGBR), Boundary Scan Register (BSR). The master TAP consists of a synchronous finite 16-bit state machine, an eight-bit instruction register, a bypass register, and an identification code register. This device has a 56800E core containing its own test access port (TAP), or core TAP , a TAP linking module (TLM) is included to manage the TAP access. Normal operation of this part will use the chip TAP as the master TAP controller, thereby disabling the 56800E TAP (core TAP) controller. The TAP controller is a simple state machine used to sequence the JTAG port through its varied operations. The JTAG port supervises the shifting of data into and out of the EOnCE module through the TDI and TDO pins.
  • This page shows a portable, battery-powered pulse oximeter, a medical device that indirectly measures the oxygen saturation of a patient's blood. The MC56F8006/MC56F8002 controls the device. This application requires low-power standby mode and dynamic operation frequency to extend battery life. The high-speed timer module helps to sample in real time the two-wavelength digital light-signal pulses that pass through the detector.
  • Here we illustrates the use of the comparator sampling mode for sensorless BLDC applications. In this application, comparators detect the zero-crossing of Back EMF generated in a motor winding. To avoid false zero-crossing detection due to noise or changes of Back EMF reference, synchronize the PWM pulse and comparator output. In this case, the comparator can be programmed to send its output to the CPU when the comparator comparing window is opened, which is triggered by the PWM module.
  • Here we show an application block diagram of a 3-Phase BLDC motor. It uses the feature of its on-chip peripherals like three high-speed comparators, dual 12-bit analog-to-digital controllers (ADCs), two programmable gain amplifiers (PGAs) and a PWM with up to six outputs. The PGAs operate in concert with the ADCs to amplify small signals, increasing the ADC input dynamic range. The PGAs also perform differential-to-single-ended conversion of analog signals. The PWMs enable power conversion functionality and accuracy for digital power supply and motor control applications. Multiple system faults are detected and processed by on-board hardware to immediately shut down the PWMs in the event of a threatening or dangerous situation
  • Thank you for taking the time to view this presentation on “MC56F8006 ” . If you would like to learn more or go on to purchase some of these devices, you may either click on the part list link, or simply call our sales hotline. For more technical information you may either visit the Freescale site, or if you would prefer to speak to someone live, please call our hotline number, or even use our ‘live chat’ online facility.
  • Transcript

    • 1. An Introduction to very low power 16-bit Digital Signal Controllers
      • Source: Freescale Semiconductor
    • 2. Introduction
      • Purpose
        • An Introduction to very low power 16-bit Digital Signal Controllers
      • Outline
        • Features, Target Application, Block Diagram
        • DSC Attributes, Advantages of DSC
        • ADC, PGA, High speed comparator
        • Crystal oscillator, SIM, computer operating properly
        • JTAG
        • Applications: Pulse oximeter, BLDC motor
      • Content
        • 18 pages
    • 3. Features
      • Single-cycle 16 × 16-bit parallel multiplier-accumulator (MAC)
      • Four 36-bit accumulators, including extension bits
      • Two 2x-16x PGAs (Programmable Gain Amplifier)
      • Three analog comparators
      • Two 12-bit ADCs
      • Six output PWM with programmable fault capability
      • Two 16-bit timers; one 16-bit periodic interval timer; programmable delay timer
      • Ultra low power operation (9 different power modes)
    • 4. Target Applications
      • Motor Control
        • 3 phase BLDC motor control
        • Entry-level field -oriented control
        • PMSM control
        • Large & small home appliances
      • Advanced Power Conversion
        • Board mounted & industrial power supplies
        • Switched-mode power supply & power management
        • Arc fault protection
        • Advance lighting control
      • Power-Sensitive Applications
        • Medical portable diagnostic and Therapeutic devices
        • Handheld power tools
        • Instrumentation
    • 5. MC56F800X Block Diagram
    • 6. DSC Attributes
      • Multiply-accumulate (MAC) operations sustained at one cycle per MAC, including memory
      • Accesses
      • Fetching up to two operands per instruction cycle for the MAC
      • Program control to provide versatile operation and zero overhead looping
      • Input/output to move data in and out of the DSC
    • 7. Advantages of DSC
      • Fewer components
      • Stable, deterministic performance
      • No analog filter adjustments
      • Wide range of applications
      • Filters with much closer tolerances
      • High noise immunity
      • Adaptive filters easily implemented
      • Self-test can be built in
      • Better power-supply rejection
    • 8. Analog-to-Digital Converter (ADC)
    • 9. Programmable Gain Amplifier (PGA)
      • Sampled PGA architecture
      • Common mode noise and offset are automatically cancelled out
      • Sample is able to be synchronized with PWM operation using the PWM sync output and programmable delay block
      • Sampling time can be precisely controlled (to less than 0.1 μs)
      • Several programmable gains (1×, 2×, 4×, 8×, 16×, and 32×)
      • 0.14 MSPS maximum
      • Rail-to-rail input voltage range
      Programmable Gain Amplifier Block Diagram
    • 10. High Speed Comparator (HSCMP) High Speed Comparator Module Block Diagram
    • 11. OCCS Block Diagram with Crystal Oscillator
    • 12. System Integration Module (SIM)
      • The system integration module is responsible for the following functions:
      • Reset sequencing
      • Clock generation and distribution
      • Implementation of stop and wait low power modes
      • System status registers
      • Registers for software access to the JTAG ID of the chip
      • Short addressing controls
      • Test registers
      • External and internal peripheral signal muxing control
    • 13. Computer Operating Properly (COP)
      • Programmable prescaler
      • Programmable timeout period can be from 0x0000 to 0xFFFF.
      • Programmable wait and stop and partial power-down mode operation.
      • COP registers do NOT reset when the device recovers from partial power-down operation.
      • COP timer is disabled while DSC is in debug mode.
      • Causes loss of reference reset 128 cycles after loss of reference clock to the PLL is detected.
      • The COP integrates a 1 kHz oscillator in support of EN60730 and IEC61508.
    • 14. Joint Test Action Group Port (JTAG) JTAG Block Diagram
      • Provide a means of accessing the EOnCE module controller and circuits to control a target system
      • Query the IDCODE from any TAP in the system
      • Force test data onto the peripheral outputs while replacing its Boundary Scan Register (BSR) with a single bit register
      • Enable/disable pull-up devices on peripheral boundary scan pins
    • 15. Application: 1 Pulse Oximeter
    • 16. Application: 2 Sensorless BLDC Use of Comparator Sampling Mode in a Sensorless BLDC Application
    • 17. 3-Phase BLDC Motor Example
    • 18. Additional Resource
      • For ordering MC56F8006 , please click the part list or
      • Call our sales hotline
      • For more product information go to
      • For additional inquires contact our technical service hotline or even use our “Live Technical Chat” online facility