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ADF7021 High Performance Narrowband ISM Transceiver
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ADF7021 High Performance Narrowband ISM Transceiver



To introduce ADF7021 ISM transceiver, its features and internal operations

To introduce ADF7021 ISM transceiver, its features and internal operations



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    ADF7021 High Performance Narrowband ISM Transceiver ADF7021 High Performance Narrowband ISM Transceiver Presentation Transcript

    • ADF7021 High Performance Narrowband ISM Transceiver
      • Source: Analog Devices
    • Introduction
      • Purpose
        • To introduce ADF7021 ISM transceiver, its features and internal operations.
      • Outline
        • SDR communication
        • ADF7021 Overview
        • Block diagram and internal operations
      • Content
        • 16 pages
    • Short Range Wireless Devices
      • Short Range Device (SRD) covers radio transmitters which provide either unidirectional or bi-directional communication and which have a low capability of causing interference to other radio equipment.
      • The applications include:
        • Automatic Meter Reading [AMI / AMR Smart Grid applications]
        • Telecontrol for Home/Building Automation Systems
        • Automotives, including Remote Keyless Entry & Remote Car Start Applications
        • Wireless Sensor Applications
        • Medical Telemetry
        • Alarms
      Worldwide Sub-GHz Bands
    • Narrowband Communications
      • A narrowband channel is generally defined as a channel bandwidth less than or equal to 25 kHz.
      • Transmitter Specifications
        • Adjacent Channel Power (ACP): the amount of spectral energy leaking into adjacent channels
        • Frequency Drift: the amount the transmitter will drift from its nominal operating frequency under extreme test or operating conditions (voltage and temperature)
        • Spurious Emissions: emissions at frequencies other than those of the wanted carrier frequency and its sidebands
      • Receiver Specifications
        • Adjacent Channel Rejection (ACR): the ability of the receiver to reject an interferer located in an adjacent channel
        • Blocking: the ability of the receiver to reject out of band interferers (usually at 1- 10 MHz)
    • ADF7021 Narrowband Solution
      • Low power, high performance, narrowband transceiver
      • Frequency Bands: 80-650MHz and 862-940MHz
      • Modulation schemes: 2FSK, 3FSK, 4FSK
      • Spectral shaping: Gaussian and Raised Cosine Filtering
      • Data rates supported: 0.05kps to 25kbps
      • Programmable output power: -16dBm to +13dBm in 63 steps
      • Receiver sensitivity: -123dBm @ 1kbps FSK
      • Low IF architecture with programmable IF bandwidths of 12.5/18.5/25kHz
      • Other features: PA ramp, AFC, URAT interface
    • Block Diagram
    • Receiver Front End The differential inputs achieve a high level of resilience against spurious reception The quadrature downconversion mixer converts the RF signal to the IF frequency of 100 kHz.
    • Demodulation and Detection
      • The quadrature outputs of the IF filter are first limited and then fed to a digital frequency correlator that performs filtering and frequency discrimination of the 2FSK/3FSK/4FSK spectrum.
      • A linear demodulator provides an output signal that is linearly proportional to the frequency of the limiter outputs.
      • A second-order, digital low-pass filter removes excess noise from the demodulated bit stream at the output of the discriminator.
      • Threshold/slicer detection is used for data recovery of 2FSK and 4FSK.
      • Data recovery of 3FSK can be implemented using either threshold detection or Viterbi detection.
    • Clock and Data Recovery
      • The data rate tolerance of the CDR is dependent on the number of bit transitions in the transmit bit stream.
      • This tolerance is maximized, and the CDR lock time is minimized when a maximum transition bit pattern is used as a preamble.
      • it is advisable to use some form of data encoding to minimize the RLL, which allows the CDR circuit to successfully track the incoming data.
    • Automatic Frequency Control (AFC) Operation
      • External AFC
        • The user reads back the frequency information through the ADF7021 serial port and applies a frequency correction value to the fractional-N synthesizer-N divider.
      • Internal AFC
        • An internal control loop automatically monitors the frequency error and adjusts the synthesizer-N divider using an internal proportional integral (PI) control loop.
      • The adjacent channel rejection (ACR) performance of the receivers can be degraded when AFC is enabled and the AFC correction range is close to the IF filter bandwidth.
      • When AFC errors are removed using either the internal or external AFC, further improvement in receiver sensitivity can be obtained by reducing the IF filter bandwidth.
    • Transmitter Output Power
      • The power amplifier (PA) output current and the output power are programmable over a wide range.
      • The output power is set using R2_DB[13:18].
      • The PA_BIAS bits (R2_DB[11:12]) facilitate an adjustment of the PA bias current to further extend the output power control range
      Setting output power
    • Transmitter Modulation
      • 2FSK
        • Two-level frequency shift keying is implemented by setting the N value for the center frequency and then toggling it with the TxDATA line.
      • 3FSK
        • In 3-level FSK modulation, the binary data (Logic 0 and Logic 1) is mapped onto three distinct frequencies.
        • Bit-to-symbol mapping for 3FSK is implemented using a linear convolutional encoder.
      • 4FSK
        • In 4FSK modulation, two bits per symbol spectral efficiency is realized by mapping consecutive input bit-pairs in the Tx data bit stream to one of four possible symbols.
    • Matching RF Input and Output Internal Rx/Tx Switch External Rx/Tx Switch
    • Serial Interface
      • The serial interface allows the user to program the 16-/32-bit registers using a 3-wire interface (SCLK, SDATA, and SLE).
      • The serial interface operates from a regulator supply.
      • Data is clocked into the register, MSB first, on the rising edge of each clock (SCLK).
    • Interfacing To Microcontroller
      • UART Mode
        • TxRxCLK pin is configured to input transmit data in transmit mode.
        • TxRxDATA pin is configured to output receive data in receive mode.
      • SPI Mode
        • TxRxCLK pin is configured to input transmit data in transmit mode.
        • TxRxDATA pin is configured to output receive data in receive mode.
        • The data clock in both transmit and receive modes is available on the CLKOUT pin.
      UART Mode SPI Mode
    • Additional Resource
      • For ordering ADF7021 transceiver, please click the part list or
      • Call our sales hotline
      • For more product information go to
        • http://www.analog.com/adf7021/
      • For additional inquires contact our technical service hotline or even use our “Live Technical Chat” online facility