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2.4G Radio Transceiver for IEEE802.15.4 and ZigBee Applications
2.4G Radio Transceiver for IEEE802.15.4 and ZigBee Applications
2.4G Radio Transceiver for IEEE802.15.4 and ZigBee Applications
2.4G Radio Transceiver for IEEE802.15.4 and ZigBee Applications
2.4G Radio Transceiver for IEEE802.15.4 and ZigBee Applications
2.4G Radio Transceiver for IEEE802.15.4 and ZigBee Applications
2.4G Radio Transceiver for IEEE802.15.4 and ZigBee Applications
2.4G Radio Transceiver for IEEE802.15.4 and ZigBee Applications
2.4G Radio Transceiver for IEEE802.15.4 and ZigBee Applications
2.4G Radio Transceiver for IEEE802.15.4 and ZigBee Applications
2.4G Radio Transceiver for IEEE802.15.4 and ZigBee Applications
2.4G Radio Transceiver for IEEE802.15.4 and ZigBee Applications
2.4G Radio Transceiver for IEEE802.15.4 and ZigBee Applications
2.4G Radio Transceiver for IEEE802.15.4 and ZigBee Applications
2.4G Radio Transceiver for IEEE802.15.4 and ZigBee Applications
2.4G Radio Transceiver for IEEE802.15.4 and ZigBee Applications
2.4G Radio Transceiver for IEEE802.15.4 and ZigBee Applications
2.4G Radio Transceiver for IEEE802.15.4 and ZigBee Applications
2.4G Radio Transceiver for IEEE802.15.4 and ZigBee Applications
2.4G Radio Transceiver for IEEE802.15.4 and ZigBee Applications
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2.4G Radio Transceiver for IEEE802.15.4 and ZigBee Applications

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Overview of AT86RF230 RF transceiver, discusses its internal circuits and operations

Overview of AT86RF230 RF transceiver, discusses its internal circuits and operations

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  • Welcome to this training module on ATMEL’s AT86RF230 2.4GHz Radio Transceiver for IEEE802.15.4 and ZigBee Applications. This training module provides an overview of the RF transceiver and discusses its internal circuits and operations.
  • IEEE standard 802.15.4 defines the physical layer (PHY) and medium access control (MAC) sublayer specifications for low data rate wireless connectivity with fixed, portable, and moving devices with no battery or very limited battery consumption requirements typically operating in the wireless personal area networks (LR-WPANs). The main objectives of these networks are ease of installation, reliable data transfer, short-range operation, and a reasonable battery life, while maintaining a simple and flexible protocol. 802.15.4 devices listen before they transmit. If there is interference, the device either waits for a period of time and tries again or moves to another channel. Message acknowledgment is also available for improved data delivery reliability. The 802.15.4 protocol is designed for monitoring and control applications where battery life is important.
  • The protocol is the work of and property of the ZigBee Alliance, a consortium of more than 70 companies who have joined together to create and promote the new standard. ZigBee is designed to serve a diverse market of applications that require low cost, low power wireless connectivity. The standard focuses on low data rate, low duty cycle connectivity, a market segment not serviced well by existing standards. ZigBee is a hardware and software standard built on the recently ratified IEEE 802.15.4 standard. It defines the hardware and software, which is described in networking terms as the physical (PHY), and Medium Access Control (MAC) layers. The ZigBee Alliance has added Network (NWK) and application (APL) layer specifications to complete what is called the ZigBee stack.
  • The AT86RF230 is a low-power 2.4 GHz radio transceiver especially designed for ZigBee/IEEE 802.15.4 applications. The AT86RF230 is a true SPI-to-antenna solution. All RF-critical components except the antenna, crystal and de-coupling capacitors are integrated on-chip. Therefore, the AT86RF230 is particularly suitable for applications like wireless sensor networks, industrial control, home and building automation, consumer electronics, and PC peripherals. The AT86RF230 can be operated by using an external microcontroller like ATMEL’s AVR microcontrollers. It provides a complete radio transceiver interface between the antenna and the microcontroller.
  • The AT86RF230 transceiver comprises an analog radio transceiver and digital demodulator. The received RF signal at pins RFN and RFP is differentially fed through the low-noise amplifier (LNA) to the RF filter (PPF) to generate a complex signal. This signal is downconverted with mixers to an intermediate frequency and fed to the integrated channel filter (SSBF). The limiting amplifier provides sufficient gain to drive the succeeding analog-to-digital converter (ADC) and generates a digital received signal strength indication (RSSI) signal with 3 dB granularity. The ADC output signal is sampled by the digital base band receiver (RX BBP). During transmission mode, the modulation signal is generated in the digital transmitter (TX BBP) and applied to the fractional-N frequency synthesis (PLL) generating a coherent phase modulation required for demodulation of O-QPSK signals. The frequency-modulated RF signal is fed to the power amplifier (PA).
  • A differential RF port (RFP/RFN) provides common-mode rejection to suppress the switching noise of the internal digital signal processing blocks. In receive mode, the RF input provides a low-impedance path to ground when transistor M0 (see Figure) pulls the inductor center tap to ground. A DC voltage drop of 20 mV across the on-chip inductor can be measured at the RF pins. In transmit mode, a control loop provides a common-mode voltage of 0.9V. Transistor M0 is off, allowing the PA to set the common-mode voltage. The common-mode capacitance at each pin to ground shall be < 30 pF to ensure the stability of this common-mode feedback loop.
  • The AT86RF230 receiver is spitted into an analog radio front end and a digital base band processor (RX BBP). The RF signal is amplified by a low noise amplifier (LNA) and converted down to an intermediate frequency by a mixer. Channel selectivity is performed using an integrated band pass filter. A limiting amplifier (Limiter) provides sufficient gain to overcome the DC offset of the succeeding analog-to-digital converter (ADC) and generates a digital RSSI signal with 3 dB granularity. The IF signal is sampled and processed further by the digital base band receiver. The RX BBP performs additional signal filtering and signal synchronization. Finally the signal is demodulated and the data are stored to the Frame Buffer.
  • The AT86RF230 transmitter consists of a digital base band processor (TX BBP) and an analog radio front end. The TX BBP reads the frame data from the Frame Buffer and performs the bit-to-symbol and symbol-to-chip mapping. The O-QPSK modulation signal is generated and fed into the analog radio front end. The fractional-N frequency synthesizer (PLL) converts the baseband transmit signal to the RF signal, which is amplified by the power amplifier (PA). The PA output is internally connected to bidirectional differential antenna pins (RFP, RFN), so that no external antenna switch is needed.
  • The crystal oscillator generates the reference frequency for the AT86RF230. All other internally generated frequencies of the radio transceiver are derived from this unique frequency. Therefore, the overall system performance is mainly based on the accuracy of this reference frequency. When using the internal oscillator, the oscillation frequency strongly depends on the load capacitance between the crystal pins XTAL1 and XTAL2. The total load capacitance CL must be equal to the specified load capacitance of the crystal itself. When using an external reference frequency, the signal needs to be connected to pin XTAL1 and the register XTAL_MODE of register 0x12 (XOSC_CTRL) need to be set to the external oscillator mode. The oscillation peak-to-peak amplitude shall be 400 mV, but not larger than 500 mV.
  • The internal voltage regulators supply the low voltage domains of the AT86RF230. The AVREG provides the regulated 1.8V supply voltage for the analog section and the DVREG supplies the 1.8V supply voltage for the digital section. The voltage regulators can be configured by the register 0x10 (VREG_CTRL). If you use an external voltage source to supply the low voltage domains, the internal regulators need to be switched off by setting the register bits to the values AVREG_EXT = 1 and DVREG_EXT = 1. A regulated external supply voltage of 1.8V needs to be connected to the pins DVDD and AVDD. When turning on the external supply, ensure a sufficiently long stabilization time before interacting with the AT86RF230.
  • The battery monitor (BATMON) detects and indicates a low supply voltage. This is done by comparing the voltage on the external supply pin (EVDD) with a programmable internal threshold voltage. The signal bit BATMON_OK of register 0x11 (BATMON) indicates the current value of the battery voltage. If BATMON_OK = 0, the battery voltage is lower than the threshold voltage. And if BATMON_OK = 1, the battery voltage is higher than the threshold voltage. After setting a new threshold, the value BATMON_OK should be read out to verify the current supply voltage value. A supply voltage drop below the programmed threshold value is indicated by the BAT_LOW interrupt.
  • Since the AT86RF230 is a true SPI-to-antenna solution, it can be operated by an external MCU. The figure describes the transceiver to microcontroller interface. The interface comprises a slave SPI and additional control signals. Microcontrollers with a master SPI interface directly to the AT86RF230. The SPI is used for Frame Buffer and register access. The additional control signals are connected to the GPIO/IRQ interface of the microcontroller.
  • The SPI is designed to work in synchronous or asynchronous mode. In synchronous mode, the CLKM output of the radio transceiver is used as the master clock of the microcontroller. In asynchronous mode, the SPI master clock (SCLK) is generated by the microcontroller itself. The SPI is based on a byte-oriented protocol and is always a bidirectional communication between master and slave. The SPI master starts the transfer by asserting SEL = L. Then the master generates 8 SPI clock cycles to transfer a byte to the radio transceiver (via MOSI). At the same time the slave transmits one byte to the master (via MISO). When the master wants to receive one byte of data from the slave it must also transmit one byte to the slave. All bytes are transferred MSB first. An SPI transaction is finished by releasing SEL = H.
  • The AT86RF230 differentiates between six interrupt events. Each interrupt is enabled or disabled by writing the corresponding bit to the interrupt mask register 0x0E (IRQ_MASK). Internally, each interrupt is stored as a separate bit of the interrupt status register. All interrupt lines are combined via a logical “OR” to one external interrupt line (IRQ). If the interrupt issues, the microcontroller shall read the interrupt status register 0x0F (IRQ_STATUS) to determine the reason for the interrupt. Interrupts are not cleared automatically when the event that caused them is not valid anymore.
  • The radio transceiver state is controlled by two signal pins (SLP_TR, RST ) and the register 0x02 (TRX_STATE). A successful state change shall be confirmed by reading the radio transceiver status from register 0x01 (TRX_STATUS). If TRX_STATUS = 0x1F, the AT86RF230 is on a state transition. The pin RST causes a reset of all registers and forces the radio transceiver into TRX_OFF state. If the device is in the P_ON state it remains in the P_ON state. For all states, the state change commands FORCE_TRX_OFF or TRX_OFF lead to a transition into TRX_OFF state. If the radio transceiver is in the BUSY_RX or BUSY_TX state, the command FORCE_TRX_OFF interrupts the active receiving or transmitting process, and forces an immediate transition. The completion of each requested state change shall always be confirmed by reading the register 0x01 (TRX_STATUS).
  • Here describes basic procedures to receive and transmit frames using the AT86RF230. While in state RX_ON the radio transceiver searches for incoming frames on the selected channel. A detection of a valid IEEE 802.15.4 frame is indicated by an IRQ_2 (RX_START) interrupt. The frame reception is completed when issuing the IRQ_3 (TRX_END) interrupt. A frame transmission comprises two actions, a frame download to the Frame Buffer and the transmission of the Frame Buffer content. Both actions can be run in parallel if required by critical protocol timing. After a frame download by a Frame Buffer write access, the frame transmission is initiated by asserting pin SLP_TR or writing the TRX command TX_START to register 0x02 (TRX_STATE), while the radio transceiver is in state PLL_ON. The completion of the transmission is indicated by an IRQ_3 (TRX_END) sinterrupt.
  • An application circuit of the AT86RF230 radio transceiver with a single-ended RF connector is shown in the Figure. The balun B1 transforms the 100 differential RF port (RFP/RFN) to a 50 single-ended RF port. The capacitors C1 and C2 provide AC coupling of the RF signals to the RF pins. The digital interface can be interfaced with a MCU directly.
  • The ATAVRRZ502 is designed for evaluation of the Atmel AT86RF230 2.4 GHz radio transceiver. The accessory kit enables point to point links development, debugging and demonstration. More advanced network topologies can be developed by adding additional RF accessory kits. The kit is top module for the STK®500 AVR starter kit and require a STK500 and STK501 for development purposes.
  • Thank you for taking the time to view this presentation on ATMEL’s AT86RF230 2.4G Radio Transceiver for IEEE802.15.4 and ZigBee Applications . If you would like to learn more or go on to purchase some of these devices, you may either click on the part list link, or simply call our sales hotline. For more technical information you may either visit the ATMEL site – link shown – or if you would prefer to speak to someone live, please call our hotline number, or even use our ‘live chat’ online facility.
  • Transcript

    • 1. 2.4GHz Radio Transceiver for IEEE802.15.4 and ZigBee Applications <ul><li>Source: ATMEL </li></ul>
    • 2. Introduction <ul><li>Purpose </li></ul><ul><ul><li>This training module provides an overview of AT86RF230 RF transceiver, discusses its internal circuits and operations. </li></ul></ul><ul><li>Outline </li></ul><ul><ul><li>IEEE 802.15.4 & ZigBee overview </li></ul></ul><ul><ul><li>AT86RF230 overview </li></ul></ul><ul><ul><li>Internal circuits </li></ul></ul><ul><ul><li>Basic operations </li></ul></ul><ul><li>Content </li></ul><ul><ul><li>20 pages </li></ul></ul>
    • 3. IEEE802.15.4-2003 Standard <ul><li>IEEE802.15.4 is a packet data protocol for lightweight wireless networks. </li></ul><ul><ul><li>Three bands </li></ul></ul><ul><ul><ul><li>2.4 GHz: 16 channels, 250 kbps </li></ul></ul></ul><ul><ul><ul><li>868.3 MHz : 1 channel, 20 kbps </li></ul></ul></ul><ul><ul><ul><li>902-928 MHz: 10 channels, 40 kbps </li></ul></ul></ul><ul><ul><li>16 bit or 64 bit addressing mode </li></ul></ul><ul><ul><li>Simple frame structure </li></ul></ul><ul><ul><li>Link quality indication </li></ul></ul><ul><ul><li>Energy detection </li></ul></ul><ul><ul><li>Low power consumption </li></ul></ul><ul><ul><li>Fully acknowledged protocol for transfer reliability </li></ul></ul>
    • 4. ZigBee <ul><li>Emerging standardized protocol for Ultra Low Power Wireless Personal Area Networks </li></ul><ul><li>Based on the IEEE 802.15.4 standard </li></ul><ul><li>Diverse market penetration </li></ul><ul><ul><li>Building automation </li></ul></ul><ul><ul><li>Personal health care </li></ul></ul><ul><ul><li>Industrial control </li></ul></ul><ul><ul><li>Lighting control </li></ul></ul><ul><ul><li>Access controls </li></ul></ul><ul><li>Low cost, low power, sophisticated networking </li></ul><ul><li>Low data rate & low duty cycle connectivity </li></ul><ul><li>Incorporates all layers of software including the Application Layer and below: NWK, MAC, and PHY </li></ul>
    • 5. Overview of AT86RF230 <ul><li>High performance RF-CMOS 2.4 GHz radio transceiver </li></ul><ul><li>Compliant to IEEE 802.15.4 & ZigBee </li></ul><ul><li>Ultra-low power consumption </li></ul><ul><ul><li>Sleep: 20nA </li></ul></ul><ul><ul><li>Rx: 15.5mA </li></ul></ul><ul><ul><li>Tx: 16.5mA </li></ul></ul><ul><li>1.8V to 3.6V supply voltage with internal regualtor </li></ul><ul><li>128-byte SRAM for data buffering </li></ul><ul><li>Programmable Clock Output to Clock the Host Microcontroller </li></ul><ul><li>Battery monitor </li></ul><ul><li>Fully Integrated PLL with on-chip Loop Filter </li></ul><ul><li>Few External Components Necessary (Crystal, Capacitors and Antenna </li></ul>
    • 6. Functional Block Diagram Analog Radio Transceiver Digital Demodulation
    • 7. Differential RF Port <ul><li>The RF port provides common-mode rejection to suppress the switching noise. </li></ul><ul><li>The RF port is designed for a 100 differential load. </li></ul><ul><li>A DC path to ground or supply voltage is not allowed. </li></ul><ul><li>RF port DC values depend on the operating mode. </li></ul>AT86RF230
    • 8. AT86RF230 Receiver (RX) <ul><li>The receiver consists of an analog radio front end and a digital base band processor (RX BBR). </li></ul><ul><ul><li>LNA amplifies the RF signal. </li></ul></ul><ul><ul><li>The mixer converts the signal down to an intermediate frequency. </li></ul></ul><ul><ul><li>Band pass filter selects the channel. </li></ul></ul><ul><ul><li>A limiting amplifier provides sufficient gain. </li></ul></ul><ul><ul><li>An ADC generates a digital RSSI signal. </li></ul></ul><ul><ul><li>The RX BBP performs additional signal filtering and signal synchronization. </li></ul></ul><ul><ul><li>Finally the signal is demodulated and the data are stored to the Frame Buffer. </li></ul></ul>
    • 9. AT86RF230 Transmitter (TX) <ul><li>The AT86RF230 transmitter consists of a digital base band processor (TX BBP) and an analog radio front end. </li></ul><ul><ul><li>The TX BBP reads the frame data from the Frame Buffer. </li></ul></ul><ul><ul><li>The TX BBP performs the bit-to-symbol and symbol-to-chip mapping as specified by IEEE 802.15.4. </li></ul></ul><ul><ul><li>The O-QPSK modulation signal is generated and fed into the analog radio front end. </li></ul></ul><ul><ul><li>The fractional-N frequency synthesizer (PLL) converts the base band transmit signal to the RF signal. </li></ul></ul><ul><ul><li>The power amplifier (PA) amplifies the RF signal. </li></ul></ul><ul><ul><li>The PA output is internally connected to bidirectional differential antenna pins </li></ul></ul>
    • 10. Crystal Oscillator (XOSC) <ul><li>The main crystal oscillator features are: </li></ul><ul><ul><li>16 MHz amplitude controlled crystal oscillator </li></ul></ul><ul><ul><li>500μs typical settling time </li></ul></ul><ul><ul><li>Integrated trimming capacitance array </li></ul></ul><ul><ul><li>Programmable clock output (CLKM) </li></ul></ul>Using Internal Oscillator Using External Reference Frequency
    • 11. Internal Voltage Regulators <ul><li>The main features of the Voltage Regulator modules are: </li></ul><ul><ul><li>Bandgap stabilized 1.8V supply for analog and digital domain. </li></ul></ul><ul><ul><li>Low dropout (LDO) voltage regulator </li></ul></ul><ul><ul><li>Configurable for usage of external voltage regulator </li></ul></ul><ul><li>The voltage regulators can be configured by the register 0x10 (VREG_CTRL). </li></ul><ul><ul><li>The internal regulators can be switched off by setting the register bits to the values AVREG_EXT = 1 and DVREG_EXT = 1 </li></ul></ul>A regulated external supply voltage of 1.8V can be connected to the pins DVDD and AVDD, but the internal regulators must be switched off. AVREG
    • 12. Battery Monitor <ul><li>The battery monitor (BATMON) detects and indicates a low supply voltage. </li></ul><ul><li>The main features of the battery monitor are: </li></ul><ul><ul><li>Programmable voltage threshold range: 1.7V to 3.675V </li></ul></ul><ul><ul><li>Battery low voltage interrupt </li></ul></ul><ul><li>A supply voltage drop below the programmed threshold value is indicated by the BAT_LOW interrupt. </li></ul>BATMON
    • 13. <ul><li>SPI Signal: </li></ul><ul><ul><li>SEL: SPI select signal </li></ul></ul><ul><ul><li>MOSI: SPI data signal (master output and slave input) </li></ul></ul><ul><ul><li>MISO: SPI data signal (master input and slave output) </li></ul></ul><ul><ul><li>SCLK: SPI clock </li></ul></ul>Microcontroller to AT86RF230 Interface <ul><li>Control Signal: </li></ul><ul><ul><li>CLKM: clock signal from AT86RF230 </li></ul></ul><ul><ul><li>IRQ: AT86RF230 interrupt request </li></ul></ul><ul><ul><li>SLP_TR: AT86RF230 multi purpose control signal </li></ul></ul><ul><ul><li>RST: AT86RF230 reset signal </li></ul></ul>SPI Control Signals
    • 14. SPI Operation <ul><li>The SPI works in synchronous or asynchronous mode. </li></ul><ul><li>Each transfer sequence starts with transferring a command byte from SPI master via MOSI, which defines the access mode and additional mode-dependent information. </li></ul><ul><ul><li>Register access mode: 2-byte read / write operation </li></ul></ul><ul><ul><li>Frame Buffer access mode: upload or download frames to the MCU </li></ul></ul><ul><ul><li>SRAM access mode: access to certain bytes within the Frame Buffer </li></ul></ul>
    • 15. Interrupt Logic <ul><li>The IRQ_MASK register (0x0E) is used to enable or disable interrupt events by writing the corresponding bit to the interrupt mask register. </li></ul><ul><li>The IRQ_STATUS register (0x0F) contains the status of the individual interrupts. </li></ul>
    • 16. Basic Operating Mode <ul><li>Power-on after V DD (P_ON) </li></ul><ul><ul><li>It occurs when the external supply voltage (V DD ) is firstly applied to the radio transceiver. </li></ul></ul><ul><ul><li>The on-chip power-on-reset sets all registers to their default values. </li></ul></ul><ul><li>Sleep state (SLEEP) </li></ul><ul><ul><li>The entire radio transceiver is disabled. </li></ul></ul><ul><ul><li>The register contents remain valid while the content of the Frame Buffer is cleared. </li></ul></ul><ul><li>Clock state (TRX_OFF) </li></ul><ul><ul><li>The CLKM output supplies a clock. </li></ul></ul><ul><li>PLL state (PLL_ON) </li></ul><ul><ul><li>The PLL frequency synthesizer is enabled </li></ul></ul><ul><li>Rx Listen (RX_ON) & Receive State (BUSY_RX) </li></ul><ul><ul><li>The receiver blocks and the PLL frequency synthesizer are enabled. </li></ul></ul><ul><li>Rx Listen State without CLKM(RX_ON_NOCLK) </li></ul><ul><ul><li>If the radio transceiver is listening for an incoming frame and the MCU is not running an application, the MCU can be powered down to decrease the total system power consumption. </li></ul></ul><ul><li>Transmit State (BUSY_TX) </li></ul>
    • 17. Radio Transceiver Usage <ul><li>Frame Receive Procedure </li></ul><ul><li>Frame Transmit Procedure </li></ul>
    • 18. Application Circuit
    • 19. Tools - ATAVRRZ502 Accessory Kit <ul><li>The Kit contains: </li></ul><ul><ul><li>2 Radio boards (require STK500 + STK501 top module) </li></ul></ul><ul><ul><li>2 ATmega1281V TQFP AVR Microcontrollers </li></ul></ul><ul><ul><li>Free Atmel IEEE 802.15.4 MAC software </li></ul></ul><ul><ul><li>PCB layout reference (Gerber files) </li></ul></ul><ul><li>The layout can be divided into 3 sections </li></ul><ul><ul><li>Digital: Reset, IRQ, SPI </li></ul></ul><ul><ul><li>Analog: Power supply, crystal </li></ul></ul><ul><ul><li>RF: antenna signals, supply decoupling </li></ul></ul>digital RF Analog
    • 20. Additional Resource <ul><li>For ordering the AT86RF230 RF transceiver, please click the part list or </li></ul><ul><li>Call our sales hotline </li></ul><ul><li>For additional inquires contact our technical service hotline </li></ul><ul><li>For more product information go to </li></ul><ul><ul><li>http://www.atmel.com/dyn/products/product_card.asp?part_id=3941 </li></ul></ul>

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