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- 1. E-528-529, sector-7, Dwarka, New delhi-110075 (Nr. Ramphal chowk and Sector 9 metro station) Ph. 011-47350606, (M) 7838010301-04 www.eduproz.inEducate Anytime...Anywhere..."Greetings For The Day"About EduprozWe, at EduProz, started our voyage with a dream of making higher education available for everyone. Since itsinception, EduProz has been working as a stepping-stone for the students coming from varied backgrounds. The bestpart is – the classroom for distance learning or correspondence courses for both management (MBA and BBA) andInformation Technology (MCA and BCA) streams are free of cost. Experienced faculty-members, a state-of-the-art infrastructure and a congenial environment for learning - are the fewthings that we offer to our students. Our panel of industrial experts, coming from various industrial domains, leadstudents not only to secure good marks in examination, but also to get an edge over others in their professional lives.Our study materials are sufficient to keep students abreast of the present nuances of the industry. In addition, we giveimportance to regular tests and sessions to evaluate our students’ progress. Students can attend regular classes of distance learning MBA, BBA, MCA and BCA courses at EduProz withoutpaying anything extra. Our centrally air-conditioned classrooms, well-maintained library and well-equipped laboratoryfacilities provide a comfortable environment for learning.Honing specific skills is inevitable to get success in an interview. Keeping this in mind, EduProz has a careercounselling and career development cell where we help student to prepare for interviews. Our dedicated placementcell has been helping students to land in their dream jobs on completion of the course.EduProz is strategically located in Dwarka, West Delhi (walking distance from Dwarka Sector 9 Metro Station and 4-minutes drive from the national highway); students can easily come to our centre from anywhere Delhi andneighbouring Gurgaon, Haryana and avail of a quality-oriented education facility at apparently no extra cost.Why Choose Edu Proz for distance learning?
- 2. • Edu Proz provides class room facilities free of cost. • In EduProz Class room teaching is conducted through experienced faculty. • Class rooms are spacious fully air-conditioned ensuring comfortable ambience. • Course free is not wearily expensive. • Placement assistance and student counseling facilities. • Edu Proz unlike several other distance learning courses strives to help and motivate pupils to get high grades thus ensuring that they are well placed in life. • Students are groomed and prepared to face interview boards. • Mock tests, unit tests and examinations are held to evaluate progress. • Special care is taken in the personality development department. "HAVE A GOOD DAY" Karnataka State Open University(KSOU) was established on 1st June 1996 with the assent of H.E. Governor of Karnatakaas a full fledged University in the academic year 1996 vide Government notificationNo/EDI/UOV/dated 12th February 1996 (Karnataka State Open University Act – 1992).The act was promulgated with the object to incorporate an Open University at the State level forthe introduction and promotion of Open University and Distance Education systems in theeducation pattern of the State and the country for the Co-ordination and determination ofstandard of such systems. Keeping in view the educational needs of our country, in general, andstate in particular the policies and programmes have been geared to cater to the needy.Karnataka State Open University is a UGC recognised University of Distance Education Council(DEC), New Delhi, regular member of the Association of Indian Universities (AIU), Delhi,permanent member of Association of Commonwealth Universities (ACU), London, UK, AsianAssociation of Open Universities (AAOU), Beijing, China, and also has association withCommonwealth of Learning (COL).Karnataka State Open University is situated at the North–Western end of the Manasagangotricampus, Mysore. The campus, which is about 5 kms, from the city centre, has a sereneatmosphere ideally suited for academic pursuits. The University houses at present theAdministrative Office, Academic Block, Lecture Halls, a well-equipped Library, Guest House
- 3. Cottages, a Moderate Canteen, Girls Hostel and a few cottages providing limitedaccommodation to students coming to Mysore for attending the Contact Programmes or Term-end examinations.MC0062-1.1 Introduction to Number SystemsIntroduction to Number SystemsThe binary numbering system and the representation of digital codes with binary representationare the fundamentals of digital electronics. In this chapter a comprehensive study of differentnumbering systems like decimal, binary, octal and hexadecimal, are carried out. The conversionand representation of a given number in any numbering system to other and a detailed analysis ofoperations such as binary addition, multiplication, division and subtraction is introduced. Binarysubtraction can be carried out with the help of adder circuits using complementary numbersystem is been introduced. Special codes like BCD codes are introduced.Objectives:By the end of this chapter, reader is expected • To have the complete understanding of the meaning and usefulness of numbering system. • To carry the arithmetic operations such as addition, subtraction, multiplication and division on binary, octal and hexadecimal numbers. • To convert a given number converted to the different formats.To explain the Usefulness of complementary numbering system in arithmetic, Binary codeddecimal (BCD) numbering systems.MC0062-1.2 The Decimal Number SystemThe Decimal Number SystemThe Decimal Number System uses base 10 and represented by arranging the 10 symbols i.e. 0through 9, where these symbols were known as digits. The position of each symbol in a givensequence has a certain numerical weight. It makes use of a Decimal point.The decimal number system is thus represented as a weighted sum representation of symbols.Table 1.1 represents the weight associated with the symbol in decimal numbering system.…. 10000 1000 100 10 1 • 0.1 0.01 0.001 ….…. 104 103 102 1 0 10 10 Decimal point 10-1 10-2 10-3 ….
- 4. Table 1.1: Weights associated with the position in Decimal numbering system.Example : 835.25 = 8 x 102 + 3 x 101 + 5 x 100 + 2 x 10-1 + 5 x 10-2 = 8 x 100 + 3 x 10 + 5 x 1 + 2 x 0.1 + 5 x 0.01 = 800 + 30 + 5 + 0.2 + 0.05 = 835.25The left most digit, which has the highest weight, is called the most significant digit, and the rightmost digit, which has the least weight, is called the least significant digit. The digits to the rightside of the decimal point are known as fractional part and the digits to the left side of thedecimal point are known as integer part.Any number of zeros can be inserted to the left of most significant digit of integer part and to theright side of the least significant digit of fractional part, which does not alter the value of thenumber represented.Self Assessment Question 1:Represent the following decimal numbers with the associated weightsa) 1395 b) 7456 c) 487.46 d) 65.235MC0062-1.3 The Binary Numbering SystemThe Binary Numbering SystemThe Binary Number System uses base 2 and represented by 0 and 1, these are known as bits alsoas Binary Digits. The position of each bit in a given sequence has a numerical weight. It makesuse of a Binary point.Thus binary number system can be represented as a weighted sum of bits. Table 1.2 representsthe weight associated in binary numbering system.Equivalent weight in …. 16 8 4 2 1 • 0.5 0.25 0.125 ….decimal BinaryBinary Powers …. 24 23 22 21 20 2-1 2-2 2-3 …. point Table 1.2: Weights associated with the position in Binary numbering system.Example: 101.11(2) = 1 x 22 + 0 x 21 + 1 x 20 + 1 x 2-1 + 1 x 2-2Self Assessment Question 2:
- 5. Represent the following decimal numbers with the associated weightsa) 11001.111(2) b) 11.101(2) c) 11011(2) d) 0.11101(2)Counting in BinaryCounting in binary is analogous to the counting methodology used in decimal numberingsystem. The symbols available are only 0 and 1. Count begins with 0 and then 1. Since all thesymbols are exhausted start with combining two-bit combination by placing a 1 to the left of 0and to get 10 and 11. Similarly continuing placing a 1 to the left again 100, 101, 110 and 111 areobtained. Table 1.3 illustrates the counting methodology in binary systems.Decimal Count Binary Count 5 bit notation0 0 000001 1 000012 10 000103 11 000114 100 001005 101 001016 110 001107 111 001118 1000 010009 1001 0100110 1010 0101011 1011 0101112 1100 0110013 1101 0110114 1110 0111015 1111 0111116 10000 1000017 10001 1000118 10010 1001019 10011 1001120 10100 1010021 10101 1010122 10110 10110
- 6. 23 10111 1011124 11000 1100025 11001 1100126 11010 1101027 11011 1101128 11100 1110029 11101 1110130 11110 1111031 11111 11111Table 1.3: illustrations for counting in BinaryBinary to Decimal ConversionWeighted Sum Representation: A Binary Number is represented with its associated weights. Theright most bit, which has a value 20 = 1, is known to be Least Significant Bit (LSB). The weightassociated with each bit varies from right to left by a power of two. In the fractional binarynumber representation, the bits are also placed to the right side of the binary point and theequivalent decimal weights for the bit location are shown in Table 1.2. The value of a givenbinary number can be determined as the weighted sum of individual weights.Example: 101.11(2) = 1 x 22 + 0 x 21 + 1 x 20 + 1 x 2-1 + 1 x 2-2 = 1 x 4 + 0 x 1 + 1 x 1 + 1 x 0.5 + 1 x 0.25 = 4 + 0 + 1 + 0.5 + 0.25 = 5.75(10) 1101(2) = 1 x 23 + 1 x 22 + 0 x 21 + 1 x 20 = 1x8+1x4+0x2+1x1 = 8+4+0+1 = 13(10) 0.111(2) = 0 x 20 + 1 x 2-1 + 1 x 2-2 + 1 x 2-3
- 7. = 0 x 1 + 1 x 0.5 + 1 x 0.25 + 1 x 0.125 = 0 + 0.5 + 0.25 + 0.125 = 0.875(10)Self Assessment Question 3:Convert the following binary numbers to decimala.) 1010(2) b.) 11.101(2) c.) 1011110001(2) d.) 1.11101(2)Decimal to Binary ConversionA given number, which has decimal form, are represented in binary in two ways. • Sum of Weight Method • Repeated Division Method • Repeated Multiplication MethodSum of Weight MethodTable 1.2 represents the weights associated with individual bit position. The weight associatedwith a bit increases by a power of two for the each bit placed to the left. For the bit positions tothe right of binary point the weight decrease by a power to two from left to right.Find out all Binary weight values, less than the given decimal number. Determine a set of binaryweight values when added should sum up equal to the given decimal number.Example: To find out binary equivalent of 43, Note that Binary values which are less than 43 are20 = 1, 21 = 2, 22 = 4, 23 = 8, 24 = 16, 25 = 32. 43 (10) = 32 + 8 + 2 + 1 = 25 + 23 + 21 + 20i.e. The set of weights 25, 23, 21, 20 when summed up equals to the given decimal number 43.By placing a 1 in the appropriate weight positions 25, 23, 21 and 20 and a 0 in the other positions,a equivalent binary representation can be obtained. 25 24 23 22 21 20 1 0 1 0 1 1 (2) = 43 (10)
- 8. Example: To find out binary equivalent of 0.625 (10) = 0.5 + 0.125 = 2-1 + 2-3= 0.101 (2)Example: to find the binary equivalent of 33.3125 (10) 33 (10) = 32 + 1 = 25 + 20 = 1 0 0 0 0 1 (2) 0.3125 (10) = 0.25 + 0.0625 = 2-2 + 2-4 = 0 . 0 1 0 1 (2) 33.3125 (10) = 1 0 0 0 0 1 . 0 1 0 1 (2)Self Assessment Question 4:Represent the following decimal numbers into binary using sum of weight method.a) 1101.11(2) b) 111.001(2) c) 10001.0101(2)Repeated Division MethodRepeated division method is the more systematic method usually used in whole numberdecimal to binary conversion. Since binary number system uses base – 2, given decimal numberis repeatedly divided by 2 until there is a 0 quotient. While division is carried out theremainders generated at each division, i.e. 0 or 1, are written down separately. The firstremainder is noted down as LSB in the binary number and the last remainder as MSB.Example: Write the binary equivalent of 29 (10) and 45 (10).
- 9. Repeated MultiplicationRepeated multiplication method is the more systematic method usually used in fraction part ofdecimal number in decimal to binary conversion. Since binary number system uses base – 2,given fraction is repeatedly multiplied by 2 until there is a 0 fraction part left. Whilemultiplication is carried out the integer parts generated at each multiplication, i.e. 0 or 1, arewritten down separately. The first integer part thus generated is noted down as first fractionalbit in the binary number and the subsequent integers generated are placed left to right.Example: Write the binary equivalent of 0.625 (10) and 0.3125 (10).Example: Write the binary Equivalent of 17.135
- 10. Therefore 17.135 (10) = 1 0 0 0 1 . 0 0 1 0 …… (2)Self Assessment Question 5:Represent the following decimal numbers into binary using repetitive divisions andmultiplication method.a) 1101.11(2) b) 111.001(2) c) 10001.0101(2MC0062-1.4 The Octal Numbering SystemThe Octal Numbering SystemThe Octal Number System uses base 8 and uses symbols 0, 1, 2, 3, 4, 5, 6 and 7, these are knownas Octal digits. The position of each bit in a given sequence has a numerical weight. It makes useof a Octal point.Thus binary number system can be represented as a weighted sum of digits. Table 1.2 representsthe weight associated in binary numbering system.in decimal … 4096 512 64 8 1 • 0.125 0.015625 … …Equivalent weight Octal … 84 83 82 81 80 8-1 8-2 … … pointTable 1.4: Weights associated with the position in Octal numbering system.
- 11. Example: 710.16 (8) = 7 x 82 + 1 x 81 + 0 x 80 + 1 x 8-1 + 6 x 8-2Self Assessment Question 6:Give the weighed sum representation for the following octal numbers.a) 734.52(8) b) 1234.567(8) c) 345.1271(8)Counting in OctalCounting with octal number system is analogous to the counting methodology used in decimaland in binary numbering system. The symbols available are from 0 to 7. Count begins with 0then 1 and till 7. Since all the symbols are exhausted start with combining two-digitcombination by placing a 1 to the left of 0 to get 10, 11, 12 … 17. Similarly, continuing placing a2, 3 …and 7. Again place 1 to the left again 100, 101, 102…107, 110….170, 200 … 270 etc.Octal to Decimal ConversionWeighted Sum Representation: An Octal Number is represented with its associated weights asshown in Table 1.4. The right most value, has a value 80 = 1, is known to be Least SignificantDigit. The weight associated with each octal symbol varies from right to left by a power of eight.In the fractional octal number representation, the bits are placed to the right side of the octalpoint. The value of a given octal number thus can be determined as the weighted sum.Example: 234.32 (8) = 2 x 82 + 3 x 81 + 4 x 80 + 3 x 8-1 + 2 x 8-2 = 2 x 64 + 3 x 8 + 4 x 1 + 3 x 0.125 + 2 x 0.015625 = 128 + 24 + 4 + 0.125 + 0.03125 = 156.15625 (10)65 (8) = 6 x 81 + 5 x 80 =6x8+5x1 = 48 + 5 = 53 (10)0.427 (8) = 4x 8-1 + 2 x 8-2 + 7 x 8-3
- 12. = 4 x 0.125 + 2 x 0.015625 + 7 x 0.001953125 = 0.544921875 (10)Decimal to Octal ConversionA given number, which has decimal form, are represented in binary in two ways. • Sum of Weight Method • Repeated Division Method • Repeated Multiplication MethodSum of Weight MethodTable 1.4 represents the weights associated with individual symbol position in octal numberingsystem. Find out all octal weight values, less than the given decimal number. Determine a set ofbinary weight values when added should sum up equal to the given decimal number.Example: To find out binary equivalent of 99, Note that octal values which are less than 99 are80 = 1, 81 = 8, 82 = 64. 99 (10) = 1 x 64 + 4 x 8 + 3 x 1 � = 1 x 82 + 4 x 81 + 3 x 80 = 1 4 3 (8)Self Assessment Question 7:Represent the following decimal numbers into octal using sum of weight method.a) 789.45 b) 654 c) 0.678 d) 987.654Repeated Division MethodRepeated division method is the more systematic method usually used in whole number decimalto octal conversion. Since Octal number system has base – 8, given decimal number is repeatedlydivided by 8 until there is a 0 quotient. While division is carried out the remainders generated ateach division, are written down separately. The first remainder is noted down as LeaseSignificant Digit (LSD) in the binary number and the last remainder as Most Significant Digit(MSD).Example: Write the binary equivalent of 792 (10) and 1545 (10).
- 13. Repeated MultiplicationRepeated multiplication method is the more systematic method usually used for the fractionalpart of decimal to octal conversion. Given fraction of decimal number is repeatedly multiplied by8 until there is a 0 fraction part left. While multiplication is carried out the integer partsgenerated at each multiplication, are written down separately. The first integer part thusgenerated is noted down as first fractional bit in the octal number and the subsequent integersgenerated are placed left to right.Example: Write the binary equivalent of 0.3125 (10).Example: Write the binary Equivalent of 541.625 (10)
- 14. Therefore 541.625 (10) = 1035.5 (8)Self Assessment Question 8:Represent the following decimal numbers into octal using repetitive multiplication and divisionmethod.a) 789.45 b) 654 c) 0.678 d) 987.654Octal to Binary ConversionThere is a direct relation between the bases of Octal and Binary number systems. i.e. 8 = 23.Which indicates that one symbol of octal can be used to replace one 3-bit representation inbinary system. There are totally 8 combinations with 3-bit binary representation from 000 to 111,which can be mapped octal symbols 0 to 7.Octal Digit Binary Bit0 0001 0012 0103 0114 1005 1016 1107 111
- 15. Table 1.5: Octal number and equivalent 3-bit Binary representationTo convert a given octal number to binary, simply replace the octal digit by its equivalent 3-bitbinary representation as shown in Table 1.5.Example: 4762.513 (8) = 4762.513 = 100 111 110 010 . 101 001 011 (2)Therefore 4762.513 (8) = 100111110010.101001011 (2)Self Assessment Question 9:Represent the following octal numbers into binary.a.) 735.45(8) b.) 654(8) c.) 0.674(8) d.) 123.654(8)1.4.5 Binary to Octal ConversionTo represent a given binary number in octal representation is also a straight forward conversionprocess. Given binary number is clubbed into a group of three bits towards left from the octalpoint and grouped towards right from the octal point. Additional 0’s, if required, can be addedto the left of leftmost bit of integer part and to the right of rightmost bit in the fractional part,while grouping.Example: 1011001.1011 (2) = 001011001 . 101100 (2) = 1 3 1 . 5 4 (8) Therefore 1011001.1011(2) = 131.54(8)Note: Additional 0’s were used while grouping 3-bits.Example: 101111.001 (2) = 101111 . 001(2)
- 16. = 5 7 . 1 (8) Therefore 101111.001 (2) = 57.1 (8)Self Assessment Question 10:Represent the following binary numbers into octal.a) 1101.11(2) b) 10101.0011(2) c) 0.111(2) d) 11100(2)MC0062-1.5 The Hexadecimal NumberingSystemThe Hexadecimal Numbering SystemThe Hexadecimal Number System uses base 16 and uses alpha-numeric symbols 0, 1, 2, 3, 4, 5,6, 7, 8, 9 and A, B, C, D, E, F. It uses ten decimal digits and six numeric symbols. Therefore base-16 is referred for hexadecimal numbering system. Unless like decimal, binary and octal systemswhich were used in weighted number representation, hexadecimal numbering system is usedto replace 4-bit combination of binary. This justifies the usage of hexadecimal numberingsystem in microprocessors, soft-computations, assemblers, and in digital electronicapplications.Counting in hexadecimal numbering system is similar way to the counting methodology used indecimal, binary and in octal numbering systems as discussed earlier in this chapter.Hexadecimal to Binary ConversionThere is a direct relation between the bases used in Hexadecimal and Binary number systems. i.e.16 = 24. Which indicates that one symbol of hex numbering can be used to replace one 4-bitrepresentation in binary system. There are totally 16 combinations with 4-bit binaryrepresentation from 0000 to 1111, which can be mapped hex symbols 0 to 9 and A to F.Octal Digit Binary Bit0 00001 00012 00103 00114 01005 0101
- 17. 6 01107 01118 10009 1001A 1010B 1011C 1100D 1101E 1110F 1111Table 1.6: Hexadecimal number and equivalent 4-bit Binary representationTo convert a given hexadecimal number to binary, simply replace the hex-digit by its equivalent4-bit binary representation as shown in Table 1.6.Example: 1A62.B53 (16) = 1 A 6 2 . B 5 3(16) = 0001 1010 0110 0010 . 1011 0101 0011(2)Therefore 1A62.B53 (16) = 0001101001100010.101101010011 (2)Example: 354.A1 (16) =3 5 4. A 1 (16) 0011 0101 0100 . 1010 0001 (2)Therefore 354.A1 (16) = 001101010100.10100001 (2)Self Assessment Question 11:Represent the following hexadecimal numbers into binary.a) 8AC8.A5(16) b) 947.A88(16) c) A0.67B(16) d) 69AF.EDC(16)Binary to Hexadecimal Conversion
- 18. To represent a given binary number in hexadecimal representation is a straight forwardconversion process. Binary number given is clubbed into a group of 4-bits starting form thehexadecimal point towards left and towards right. Additional 0’s, if required, can be added tothe left of leftmost bit of integer part and to the right of rightmost bit in the fractional part,while grouping. Equivalent hexadecimal symbol is placed for a 4-bit binary group to have theconversion.Example: 1011001.1011 (2) = 01011001 . 1011(2) = 5 9 . B (16) Therefore 1011001.1011 (2) = 59.B (16)Note: Additional 0’s were used while grouping 4-bits.Example: 101111.001 (2) = 00101111 . 0010 (2) = 2 F . 2 (16) Therefore 101111.001 (2) = 2F.2 (16)Note: Hexadecimal to Octal Conversion can be done by first converting a given Hexadecimalnumber to binary and then converting the resultant binary to octal system. Similarly given octalnumber can be converted to hexadecimal by converting first to the binary system and then tohexadecimal system.Self Assessment Question 12:Represent the following binary numbers into Hexadecimal.a.) 1101.11(2) b.) 10101.0011(2) c.) 0.111(2) d.) 11100(2)Hexadecimal to Decimal ConversionHexadecimal numbers can be represented with their associated positional weights as indicatedin Table 1.7. Positional weights increases by a power of 16 towards left of the hexadecimalpoint and decrease by a power of 16 towards right. Equivalent weight in …. 4096 256 16 1 • 0.0625 0.00390625 …. decimal …. 163 162 161 160 Hexadecimal 16-1 16-2 ….
- 19. pointTable 1.7: Weights associated with the position in hexadecimal numbering system.Hexadecimal to Octal ConversionWeighted Sum Representation: Hexadecimal Number is represented with its associated weightsas shown in Table 1.4. The right most value, has a value 80 = 1, is known to be Least SignificantDigit. The weight associated with each octal symbol varies from right to left by a power of eight.In the fractional octal number representation, the bits are placed to the right side of the octalpoint. The value of a given octal number thus can be determined as the weighted sum.Example: 234.32 (8) = 2 x 82 + 3 x 81 + 4 x 80 + 3 x 8-1 + 2 x 8-2 = 2 x 64 + 3 x 8 + 4 x 1 + 3 x 0.125 + 2 x 0.015625 = 128 + 24 + 4 + 0.125 + 0.03125 = 156.15625 (10)65 (8) = 6 x 81 + 5 x 80 =6x8+5x1 = 48 + 5 = 53 (10)0.427 (8) = 4x 8-1 + 2 x 8-2 + 7 x 8-3 = 4 x 0.125 + 2 x 0.015625 + 7 x 0.001953125 = 0.544921875 (10)Self Assessment Question 13:Represent the following hexadecimal numbers into octal numbers.a) 8AC8.A5(16) b) 947.A88(16) c) A0.67B(16) d) 69AF.EDC(16)Decimal to Octal ConversionA given number, which has decimal form, are represented in binary in two ways. • Sum of Weight Method • Repeated Division Method
- 20. • Repeated Multiplication MethodSum of Weight MethodTable 1.4 represents the weights associated with individual symbol position in octal numberingsystem. Find out all octal weight values, less than the given decimal number. Determine a set ofbinary weight values when added should sum up equal to the given decimal number.Example: To find out binary equivalent of 99, Note that octal values which are less than 99 are80 = 1, 81 = 8, 82 = 64. 99 (10) = 1 x 64 + 4 x 8 + 3 x 1 � = 1 x 82 + 4 x 81 + 3 x 80 = 1 4 3 (8)Repeated Division MethodRepeated division method is the more systematic method usually used in whole number decimalto octal conversion. Since Octal number system has base – 8, given decimal number is repeatedlydivided by 8 until there is a 0 quotient. While division is carried out the remainders generated ateach division, are written down separately. The first remainder is noted down as LeaseSignificant Digit (LSD) in the binary number and the last remainder as Most Significant Digit(MSD).Repeated Multiplication
- 21. Repeated multiplication method is the more systematic method usually used for the fractionalpart of decimal to octal conversion. Given fraction of decimal number is repeatedly multipliedby 8 until there is a 0 fraction part left. While multiplication is carried out the integer partsgenerated at each multiplication, are written down separately. The first integer part thusgenerated is noted down as first fractional bit in the octal number and the subsequent integersgenerated are placed left to right. Integer Part 0.625 X 80.625 (10) = 0.5 (8) 5 0.0Therefore 541.625 (10) = 1035.5 (8)Self Assessment Question 14:Represent the following hexadecimal numbers into octal.a) 8AC8.A5(16) b) 947.A88(16) c) A0.67B(16) d) 69AF.EDC(16)MC0062-1.6 Binary ArithmeticBinary ArithmeticLet us have a study on how basic arithmetic can be performed on binary numbers.Binary Addition
- 22. There are four basic rules with Binary Addition 0(2) + 0(2) = 0(2) 0(2) + 1(2) = 0(2) Addition of two single bits result into single bit 1(2) + 0(2) = 1(2) 1(2) + 1(2) = 10(2) Addition of two 1’s resulted into Two bitsExample: perform the binary addition on the followings11 1111 1 1 1 011(2) 3(10) 1101(2) 13(10) 11100(2) 28(10)+ 011(2) + 3(10) + 0111(2) + 07(10) + 10011(2) + 19(10) 110(2) 6(10) 10100(2) 20(10) 101111(2) 47(10)Binary SubtractionThere are four basic rules associated while carrying Binary subtraction 0(2) – 0(2) = 0(2) 1(2) – 1(2) = 0(2) � 1(2) – 0(2) = 1(2) 0(2) – 1(2) = invalid there fore obtain a borrow 1 from MSB and perform binary subtraction 10(2) – 1(2) = 1(2) �Note: In last rule it is not possible to subtract 1 from 0 therefore a 1 is borrowed from immediatenext MSB to have a value of 10 and then the subtraction of 1 from 10 is carried outExample: perform the binary subtraction on the followings 11 11 011(2) 3(10) 1101(2) 13(10) 11100(2) 28(10)– 011(2) – 3(10) – 0111(2) – 07(10) – 10011(2) – 19(10)
- 23. 000(2) 0(10) 0110(2) 06(10) 01001(2) 09(10)Binary MultiplicationThere are four basic rules associated while carrying Binary multiplication 0(2) x 0(2) = 0(2) 0(2) x 1(2) = 0(2) � 1(2) x 0(2) = 0(2) 1(2) x 1(2) = 1(2) �Note: While carrying binary multiplication with binary numbers the rule of shift and add is madeused similar to the decimal multiplication. i.e. multiplication is first carried out with the LSB ofthe multiplicand on the multiplier bit by bit basis. While multiplying with the MSB bits, first thepartial sum is obtained. Then result is shifted to the left by one bit and added to the earlier resultobtained.Example: perform the binary multiplication on the followings011(2) 3(10) 1101(2) 13(10)x 1(2) x 1(10) x 11(2) x 03(10) 1101(2)011(2) 3(10) 1101 (2) 100111(2) 39(10)Binary DivisionThe binary division is similar to the decimal division procedureExample: perform the binary division 101(2) 10.1(2) 1111 1111.011 110 11 110 001 0011 000 000
- 24. 11 110 11 110 00 000Complementary numbering systems: 1’s and 2’s Complements1’s complement of a given binary number can be obtained by replacing all 0s by 1s and 1s by 0s.Let us describe the 1’s complement with the following examplesExamples: 1’s complement of the binary numbersBinary Number 1’s Complement 1101110 0010001 111010 000101 110 001 11011011 00100100Binary subtraction using 1’s complementary Method:Binary number subtraction can be carried out using the method discussed in binary subtractionmethod. The complementary method also can be used. While performing the subtraction the1’s complement of the subtrahend is obtained first and then added to the minuend. Therefore1’s complement method is useful in the sense subtraction can be carried with adder circuits ofALU (Arithmetic logic unit) of a processor.Two different approaches were discussed here depending on, whether the subtrahend is smalleror larger compared with minuend.Case i) Subtrahend is smaller compared to minuendStep 1: Determine the 1’s complement of the subtrahendStep 2: 1’s complement is added to the minuend, which results in a carry generation known asend-around carry.Step 3: From the answer remove the end-around carry thus generated and add to the answer.Example: Perform the subtraction using 1’s complement methodBinary Subtraction Binary Subtraction(usual method) ( 1’s complement method)11101(2) 11101(2)
- 25. – 10001(2) + 01110(2) 1’s complement of 10001 1 01011(2) end-around carry generated01100(2) + 1(2) add end-around carry 01100(2) AnswerCase ii) Subtrahend is larger compared to minuend Step 1: Determine the 1’s complement of the subtrahend Step 2: Add the 1’s complement to the minuend and no carry is generated. Step 3: Answer is negative singed and is in 1’s complement form. Therefore obtain the 1’s complement of the answer and indicate with a negative sign.Example: Perform the subtraction using 1’s complement methodBinary Subtraction Binary Subtraction(usual method) ( 1’s complement method)10001(2) 10001(2)– 11101(2) + 00010(2) 1’s complement of 10001– 01100(2) 10011(2) No carry generated. Answer is negative and is in 1’s complement form – 01100(2) AnswerBinary subtraction using 2’s complementary Method:2’s complement of a given binary number can be obtained by first obtaining 1’s complementand then add 1 to it. Let us obtain the 2’s complement of the following.Examples: 2’s complement of the binary numbersBinary Number 2’s Complement 00100011101110 +1 0010010 000101111010 +1
- 26. 000110 001110 +1 010 0010010011011011 +1 00100101Binary number subtraction can be carried out using 2’s complement method also. Whileperforming the subtraction the 2’s complement of the subtrahend is obtained first and then addedto the minuend.Two different approaches were discussed here depending on, whether the subtrahend is smalleror larger compared with minuend.Case i) Subtrahend is smaller compared to minuend Step 1: Determine the 2’s complement of the subtrahend Step 2: 2’s complement is added to the minuend generating an end-around carry. Step 3: From the answer remove the end-around carry and drop it.Example: Perform the subtraction using 2’s complement methodBinary Subtraction Binary Subtraction(usual method) ( 1’s complement method)11101(2) 11101(2)– 10001(2) + 01111(2) 2’s complement of 10001 1 01100(2) end-around carry generated01100(2) drop the carry 01100(2) AnswerCase ii) Subtrahend is larger compared to minuend
- 27. Step 1: Determine the 2’s complement of the subtrahendStep 2: Add the 2’s complement to the minuend and no carry is generated.Step 3: Answer is negative singed and is in 2’s complement form. Therefore obtain the 2’scomplement of the answer and indicate with a negative sign.Example: Perform the subtraction using 1’s complement methodBinary Subtraction Binary Subtraction(usual method) ( 2’s complement method)10001(2) 10001(2)– 11101(2) + 00011(2) 1’s complement of 10001– 01100(2) 10000(2) No carry generated. Answer is negative and is in 1’s complement form – 01100(2) AnswerSelf Assessment Question 15:Perform the following subtractions using 1’s complement and 2’s complement methodsa) 1101(2) – 1010(2) b) 10001(2) - 11100(2) c) 10101(2) - 10111(2MC0062-1.7 Binary Coded Decimal (BCD)Numbering systemBinary Coded Decimal (BCD) Numbering systemThe BCD code is also known as 8421 code. It is a 4 bit weighted code representing decimaldigits 0 to 9 with four bits of binary weights (23, 22, 21, 20). Please note that with four bits thepossible numbers of binary combinations are 24 = 16, out of which only first 10 combinationswere used. The codes 1010, 1011, 1100, 1101, 1110 and 1111 are not used.BCD or 8421 code Decimal Number0000 00001 10010 20011 30100 40101 50110 60111 7
- 28. 1000 81001 9A given decimal number can be represented with equivalent BCD number by replacing theindividual decimal digit with its equivalent BCD code.Example: 348.16 (10) = 0011 0100 1000 . 0001 0110 (BCD) 18 (10) = 0001 1000 (BCD) 9357 (10) = 1001 0011 0101 0111 (BCD)BCD AdditionBCD codes are the 4 bit binary weighted code representation of decimal numbers. The additionoperation carried on decimal can be represented with BCD addition. Since BCD does not uses all16 combinations possible from 4-bit representation, while addition performed on BCDnumbers, may result into invalid code words. The rule to be followed while BCD were addeddirectly are given as 1. Add the given two BCD numbers using the addition rules for binary addition 2. If the resultant 4-bit binary is less than 9 then it is a valid BCD code 3. If a 4-bit sum is greater than 9 then it is an invalid BCD code 4. If there is carry generated while adding the two 4-bit numbers the result is an invalid sum. 5. For both the cases discussed in 3 and 4 add a BCD equivalent of 6 i.e. 0110(2) so that sum skips all six invalid states and results into a valid BCD number.Example: few examples for the generation of valid BCD codes during BCD addition0011 3 1000 0110 0111 867 0100 0101 0010 452+ 0101 +5 + 0001 0011 0010 + 132 + 0100 0001 0110 + 4161000 8 1001 1001 1001 999 1000 0110 1000 868Example: few examples for the generation of invalid BCD codes during BCD addition1000 8+ 0111 +7
- 29. 1111 Invalid BCD combination >9+ 0110 Add 61 0101 Valid BCD number 151000 8+ 1001 +91 0001 Invalid BCD combination , carry generated+ 0110 Add 61 0111 Valid BCD number 17Note: While carrying BCD addition as discussed in the examples above, if the answer has morethan one group of 4-bit combination, which is invalid (either invalid combination or due to carrygeneration) 6 to be added to each group to get a valid BCD code.Self Assessment Question 16:Add the following BCD Numbersa) 0100000 + 1001011 b) 01100100 + 00110011 c) 0111 + 0010 d) 1010 + 0111Summary • A binary number system has a base of two and consists of two digits (called bits) 1 and 0. • A binary number is a weighted number with the weight of each whole number digit from least significant (20) to most significant being an increasing positive power of two. The weight of each fractional digit beginning at 2-1 is an increasing negative power of two. • The 1’s complement of a binary number is derived by changing 1s to 0s and 0s to 1s • The 2’s complement of a binary number is derived by adding 1 to the 1’s complement • Binary subtraction can be accomplished by addition using the 1’s or 2’s complement methods • A decimal whole number can be converted to binary by using the sum-of-weights or by repeated division by 2 method • A decimal fraction can be converted to binary by using the sum-of-weights or by repeated division by 2 method • The octal number system has a base of eight and consists of eight digits (0 to 7) • A decimal whole number can be converted to octal by using the repeated division-by-8 method • Octal to binary conversion is accomplished by simply replacing each octal digit with its three-bit binary equivalent. The process is reversed for binary-to-octal conversion • The hexadecimal number system has a base of sixteen and consists of 16 digits and characters 0 through 9 and A to F • One hexadecimal digit represents a four-bit binary number and its primary usefulness is simplifying bit patterns by making then easier to read
- 30. • BCD represents each decimal digit by a four-bit binary number. Arithmetic operations can be performed in BCD. • The Main feature of the Gray-code is the single-bit change going from one number in sequence to the nextTerminal Questions 1. Convert the following binary numbers to decimal 1. 11.001(2) 2. 1100(2) 3. 1111(2) 4. 1011.101(2) 5. 0.1101(2) 2. Convert the following decimal numbers to binary using sum-of weight and repeated division methods 1. 40.345(10) 2. 143.7(10) 3. 467(10) 1. Convert the following octal number to decimal 1. 73.24(8) 2. 276(8) 3. 0.625(8) 4. 57.231(8) 2. Convert the octal numbers in question 3 into binary format 3. Convert the decimal numbers in question 2 into octal format 4. Convert the binary numbers in question 1 into octal format 5. Give the equivalent BCD representation for the decimal numbers given in question 2 6. Perform the BCD addition 1. 1001(2) + 0110(2) 2. 01010001(2) + 01011000(2) 3. 0111(2) + 0101(2) 4. 0101011100001(2) + 011100001000(2) 7. Perform the 1’s and 2’s complement to realize the binary subtraction. 1. 10011(2) – 10101(2) 2. 10010(2) – 11001(2)1111000(2) – 1111111(2)Unit 3 Combinational LogicThis unit mainly focuses on realization of combinational logic using basic gates, reducedrepresentation of combinational logic using basic gates, specific truth table realization, universal
- 31. properties of NOR and NAND gates, canonical logic forms, sum of products (SOP) and productof sum(POS) form representation.MC0062(A)3.1 IntroductionIntroductionIn unit 2, logic gates were studied on an individual basis and in simple combinations. When logicgates where connected together to produce a specified output for certain specified combinationsof input variables, with no storage involved, the resulting network is called combinational logic.In combinational logic, the output level is at all times dependent on the combination of inputlevels. The chapter mainly focuses on realization of combinational logic using basic gates,reduced representation of combinational logic using basic gates, specific truth table realization,universal properties of NOR and NAND gates, canonical logic forms, sum of products (SOP) andproduct of sum(POS) form representation.Objectives:By the end of this chapter, reader should know • How to simplify the combinational logic expressions using Boolean rules and laws and with the application of Demorgan’s theorem. • How to realize the simplified expressions using basic logic gates. • How to represent the logic expressions with the canonical forms such as sum of products and product of sum forms. • What are Universal gates and its application in the realization of simplified logic functions? • What are Timing diagrams and the concept of synchronization • How to realize the combinational circuits from the specified truth table.MC0062(A)3.2 Realization of switchingRealization of switching functions using logic gatesA given logic function can be realized with the combination of basic gates. Boolean laws andrules are used to simplify and simplified realization of the same function with the basic gates areshown here.Example: Realize the given function using basic gates. Use Boolean rulesand laws to simplify the logic function and realize the minimized function using basic gates.
- 32. Solution:Direct realization: �Simplifying using Boolean Algebra:
- 33. Example: Realize the logic expression using basic gates.Solution: Direct realization of the expressionExample: A logic function if defined by . Give the basic gate realization.Simplify the logic function and represent with basic gates.Solution: Direct realization of the functionSimplifying the expression using Boolean Laws
- 34. Self Assessment Question: Use Boolean algebra to simplify the logic function and realize thegiven function and minimized function using discrete gates.Solution: i) Direct realization of the functionii) Simplified realization of the functionMC0062(A)3.3 Canonical Logic FormsCanonical Logic Forms
- 35. The form of the Boolean expression does determine how many logic gates are used and whattypes of gates are needed for the realization and their interconnection. The more complex anexpression, the more complex the circuit realization will be. Therefore an advantage of simplifyan expression is to have the simple gate network.There are two representations in which a given Boolean expressions can be represented. • Sum of Product form (SOP) • Product of Sum form (POS)Sum of Products FormIn Boolean algebra the product of two variables can be represented with AND function and sumof any two variable can be represented with OR function. Therefore AND and OR functions aredefined with two or more input gate circuitries.Sum of products (SOP) expression is two or more AND functions ORed together. The ANDedterms in a SOP form are known as minterms.Example:Here in the first example the function is having 4 minterms and the second example has 3minterms. One reason the sum of products is a useful form of Boolean expression, which is thestraightforward manner in which it can be implemented with logic gates. It is to be noted that thecorresponding implementation is always a 2-level gate network. i.e. the maximum number ofgates through which a signal must pass 2in going from an input to the output is two (excludinginversions if any).A most popular method of representation of SOP form is with the minterms. Since the mintermsare ORed, a summation notation with the prefix m is used to indicate SOP expression. If thenumber of variables are used is n, then the minterms are notated with a numeric representationstarting from 0 to 2n.Consider the above example, where the given logic expression can be represented in terms ofassociated minterms. consists of 3 variables. Therefore minterms can berepresented with the associated 3-bit representation. Representation of minterms with 3-bitbinary and equivalent decimal number can be noted. , , , .
- 36. There fore the logic function can b given asSelf Assessment Question: implement the SOP expression given by orProduct of Sum FormProduct of Sum (POS) expression is the ANDed representation of two or more OR functions.The ORed terms in a POS form are known as maxterms.Example:Here in the first example the function is having 4 maxterms and the second example has 3maxterms. This form is also useful in the straightforward implementation of Boolean expressionis with logic gates. It is to be noted that the corresponding implementation is always a 2-levelgate network. i.e. the maximum number of gates through which a signal must pass 2in goingfrom an input to the output is two (excluding inversions if any).
- 37. Similar to SOP representation, a most popular method of representation of POS form is with themaxterms. Since the maxterms are ANDed, a product notation with the prefix M is used. If thenumber of variables are used is n, then the maxterms are notated with a numeric representationstarting from 0 to 2n.Consider the above example, where the given logic expression can be represented in terms ofassociated maxterms. it consists of 3 variables. Therefore maxtermscan be represented with the associated 3 bit representation. Representation of maxterms with 3-bit binary and equivalent decimal number can be noted. , , .There fore the logic function can b given asSelf Assessment Question: implement the SOP expression given by or .
- 38. MC0062(A)3.5 Timing Diagrams andSynchronous LogicTiming Diagrams and Synchronous LogicIn digital systems, a timing diagram shows the waveform appearing at several different points.Timing diagram is plotted as a plot dependent of time axis (horizontal axis). All observedwaveforms were plotted with time axes are aligned. Therefore, it is possible at a particularinstant to determine the state of each waveform. The timing diagram mainly assists the study ofpropagation delay in the gate circuitry.A clock waveform is a rectangular pulse having HIGH and LOW representations. The basicgates were studied in unit II with digital inputs. Consider these gates were studied with one of theinput is being digital input and the other being a clock waveform. The gates are said to be pulsedor clocked. The study of gate circuitry with respect to the timing pulses is known as synchronouslogic circuits.Gate Circuitry with timing pulses. • NOT Gate • AND GateOutput of an AND gate is HIGH only when all inputs are HIGH at the same time.
- 39. • OR GateThe output of an OR gate is HIGH any time at least one of its inputs is HIGH. The output is LOWonly when all inputs are LOW at the same time. • NAND GateThe output of a NAND gate is LOW only when all inputs are HIGH at the same time.
- 40. • NOR GateThe output of a NOR gate is LOW any time at least one of its inputs is HIGH. The output is HIGHonly when all inputs are LOW at the same time.Example: Determine the output waveform for the combinational circuit shown with theindicated input waveforms.
- 41. MC0062(A)3.6 Realization of CombinationalRealization of Combinational circuits from the truth tableThe Logic functions were represented with the truth tables as discussed in unit II. To realize thegiven logic functions, write down the combination of all logic functions in SOP form. A truthtable gives the logic entries for the all possible combination of inputs related to the output. Theoutput logic is TRUE for a specific input combination is represented with an entry ‘1′ and thelogic FALSE with an entry ‘0′.Example: Design a logic circuit to implement the operations specified in the following truthtable.Inputs Outputa b c f0 0 0 00 0 1 00 1 0 00 1 1 11 0 0 01 0 1 11 1 0 11 1 1 0Solution: From the truth table the function can be given in terms of minterms
- 42. Summary • There are two basic forms of Boolean expressions: the sum-of-products and the product- of-sum • Boolean expressions can be simplified using the algebraic method and are realizable using discrete gates • Any logic function can be represented with equivalently using a truth table. • Truth table simplification can be done using Sum-of-product realization or with product of sum realization • Demorgan’s theorems are used to represent the function only with universal gatesTerminal Questions: 1. Realize the given function using basic gates. Use Boolean rules and laws to simplify the logic function and realize the minimized function using basic gates. 2. Realize the logic expression using basic gates. 3. Use Boolean algebra to simplify the logic function and realize the given function and minimized function using discrete gates. 4. Implement the following SOP expression 1. 2. 3. 4. 5. Use Boolean algebra to simplify the logic function and realize the given function and minimized function using discrete gates.
- 43. 1. 2. 6. Implement the following SOP expressions with discrete gates 1. 2. 3. 7. Give the NAND realization for the logic expressions given in question number 3 and 4. 8. Design a logic circuit to implement the operations specified in the following truth table. Inputs Output a b c f 0 0 0 1 0 0 1 0 0 1 0 0 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 0MC0062(A)4.1 IntroductionIntroductionA given logic function can be realized with minimal gate logic. Boolean algebra and laws wereof great help to reduce the given expression into a minimal expression. But the simplificationprocess of the expression is being not a systematic method, it is not sure that the reducedexpression is the minimal expression in real sense or not.
- 44. In this chapter different combination logic minimization methods were discussed. The mostpreferred method is being the use of Karnaugh Map or also known as K – map. Here a basicstructure of K – map is dealt with two, three and four variable. Other method used is Qune –McClusky method.ObjectivesBy the end of this chapter, reader should be able to explain • the concept of Karnaugh map and simplification of logic expression using Karnaugh Map. • How to group the adjacent cells in K-Map with two, three and four variable maps and to solve the logic functions • How logic expressions are simplified using Quine McClusky method • What are the multiple output functions and how to simplify and to realize the same.MC0062(A)4.2 Karnaugh Map or K – MapKarnaugh Map or K – MapThe Karnaugh map provides a systematic procedure in the simplification of logic expression. Itproduces the simplest SOP expression if properly used. An user is required to know the mapstructure and associated mapping rules.Karnaugh Map consists of an arrangement of cells. Each adjacent cells represents a particularcombination of variables in the product form. For an ‘n’ number of variables the total number ofcombinations possible are 2n, hence Karnaugh Map consists of 2n cells.For example, with two input variables, there are four combinations. Therefore a four cell mapmust be used.Format of a two-variable Karnaugh – Map is shown in Figure 4.1. For the purpose of illustrationonly the variable combinations are labeled inside the cells. In practice, the mapping of thevariables to a cell is such that the variable to the left of a row of cells applies to each cell in thatrow. And the variable above a column of cells applies to each cell in that column.
- 45. Similarly three variable and four variable Karnaugh Maps were shown in the Figure 4.2. A threevariable map consists of 23 = 8 cells and a four variable map consists of 24 = 16 cells. The valueof the minterms are indicated within the cell. Note that in a Karnaugh Map, the cells are arrangedsuch a way that there is only a one bit or one variable change between any two adjacent cells.Karnaugh maps can also be used for five, six or more variables.MC0062(A)4.3 Plotting a Boolean expressionPlotting a Boolean expressionGiven a logic function get its sum – of – product (SOP) realization. Place 1 in each cellcorresponding to the term obtained in the logic function. And 0 in all other empty cells.Example: Plot a two variable logic functionFigure 4.3: three variable and four variables Karnaugh Map.Self Assessment Question: Plot a three variable logic function in a K – map
- 46. Self Assessment Question: Plot a Four variable logic function in a K – mapMC0062(A)4.4 Logic expressionsimplificationLogic expression simplification with grouping cellsLet us discuss the simplification procedure for the Boolean expressions. The procedure beingsame irrespective of the dimensionality of K – map. A four variable K – map is used for thediscussion on grouping cells for expression minimizing process.Grouping of adjacent cells are done by drawing a loop around them with the followingguidelines or rules. • Rule 1: Adjacent cells are cells that differ by only a single variable. • Rule 2: The 1s in the adjacent cells must be combined in groups of 1, 2, 4, 8, 16 so on • Rule 3: Each group of 1s should be maximized to include the largest number of adjacent cells as possible in accordance with rule 2. • Rule 4: Every 1 on the map must be included in at least one group. There can be overlapping groups, if they include non common 1s.Simplifying the expression:
- 47. • Each group of 1s creates a product term composed of all variables that appear in only one form within the group • Variables that appear both uncomplemented and complemented are eliminated. • Final simplified expression is formed by summing the product terms of all the groups.Example: Use Karnaugh Map to simplify the expressionSolution:Example: reduce the following expression using Karnaugh MapSolution:Example: Using Karnaugh Map, Implement the simplified logic expression specified by thetruth table.
- 48. Inputs Outputa b c f0 0 0 10 0 1 00 1 0 00 1 1 01 0 0 11 0 1 01 1 0 11 1 1 1Solution:Example: A logic circuit has three inputs and one output terminals. Output is high when two ormore inputs are at high. Write the truth table and simplify using Karnaugh Map.Inputs Outputa b c f
- 49. 0 0 0 00 0 1 00 1 0 00 1 1 11 0 0 01 0 1 11 1 0 11 1 1 1Solution:Simplified expressionSelf Assessment Question: 1. Reduce the following expression using K – Map and implement using universal gate 1. 2. 2. Reduce using the K-map 1. 2. 3.MC0062(A)4.5 Quine McClusky Method
- 50. Quine McClusky MethodQuine McClusky method is known as tabular method, a more systematic method of minimizingexpressions of larger number of variables. Therefore its an edge over the disadvantage ofKarnaugh Map method were it supports a maximum of six variable. Qunie McClusky method isvery suitable for hand computation as well as for the soft program implementation.Prime implicantsSolution of logical expression with Quine McClusky method involves in the computation ofprime implicants, from which minimal sum should be selected.The procedure for the minimization of a logic expression is done as follows. • Arrange all minterms in groups of the same number of 1s in their binary representations. Start with the least number of 1s present in the number and continuing with increasing number of 1s. • Now compare each term of the lowest index group with every term in the succeeding group. Whenever the two terms differ by one bit position, the two terms were combined with (-) used in place of differing position. • Place a tick mark next to the every term used while combining. • Perform the combining operation till last group to complete the first iteration. • Compare the terms generated with same procedure with dashed line mapping the dashed line in two terms under comparison. • Continue the process till no further combinations are possible. • The terms which are not ticked constitute the prime implicants.Prime implicant chartThe Prime implicant chart is a representation giving the relationship between the primeimplicants and the minterms constituting the logic expression. The prime implicant chart gives anidea to have a set of minimum number of prime implicants which cover all minterms. Thus thenumber of minimal set of prime implicants may be more than one which cover all minterms. Tofind a subset of prime implicants which are essential part to cover all minterms or which arefound in all such subsets which covers the given minterms, are known as essential primeimplicants.Thus the simplified expression for a given logic function consists of all essentialprime implicants and one or more prime implicants. In Prime implicant chart have all primeimplicants found in row wise and all minterms in column wise. Put a tick mark against theminterms which are covered by individual prime implicants. Find the minterms which arecovered by only one prime implicant. These prime implicants will be the essential primeimplicants. After finished with finding all essential prime implicants, find the set of primeimplicants necessary to cover all other minterms.
- 51. Example: Obtain the set of prime implicants for Column 1 Column 2 Column 3 Min Binary terms Designation a b d a b d a b d c c c 0 0 0 – (0,1) √Grou 0 0 0 0 √ – 0 0 – V 0 (0,1,8,9)p0 – 0 0 0 (0,8) √ 0 0 0 1 √ – 0 0 1 1 (1,9) √Group1 1 0 0 0 √ 1 0 0 – 8 (8,9) √ 0 1 1 – √ (6,7) 0 1 1 0 √ 6Grou – 1 1 0 √ (6,7,14,15 – 1 1 – U (6,14)p2 1 0 0 1 √ ) 9 1 – 0 1 X (9,13) 0 1 1 1 √ (7,15) – 1 1 1 7 √Grou 1 1 0 1 √ (13,15) 1 1 – 1 13 Wp3 1 1 1 0 √ (14,15) 1 1 1 – 14 √Grou 1 1 1 1 √ 15p4It is found that U, V, W and X are prime implicants. Now to find essential prime implicants fromPrime implicant chart. √ √ √ √ √ √ √ √Prime Implicants Minterms 0 1 6 7 8 9 13 14 15 ↓ U 6,7,14,15 X X X X V 0,1,8,9 X X X X W 13,15 X X
- 52. X 9,13 X XIn the column corresponding to minterms 0, 1, 6, 7, 8 there are only one entries and the primeimplicants covering them are U and V. Therefore U and V are considered as essential primeimplicants. Other than the above minterms they cover minterms 14 and 15 too. But minterm 13 isnot covered by these two essential prime implicants. Therefore along with U and V either W orX can be used to represent the simplified Boolean expression.Where �Therefore the simplified logic expression can be given as orExample: Obtain the set of prime implicants for Column 1 Column 2 Column 3 Min Binary terms Designation a c a b c d a b c d b d (1,3) 0 0 – 1 √ (1,3,5,7) 0 – – 1 Y 0 0 1 0 1 √ (1,5) 0 – 0 1 √ (1,5,9,13) – – 0 1 XGrou 0 1 2 0 0 √p1 (1,9) – 0 0 1 √ (2,3,6,7) 0 – 1 – W 1 0 8 0 0 √ (2,3) 0 0 1 – √ (8,9,12,13 1 – 0 – V )
- 53. (2,6) 0 – 1 0 √ (8,9) 1 0 0 – √ (8,12) 1 – 0 0 √ (3,7) 0 – 1 1 √ 0 1 3 0 1 √ (5,7) 0 1 – 1 √ 0 1 0 √ 5 1 (5,13) – 1 0 1 √Grou 0 1 1 0 √ (5,7,13,15 – 1 – 1 U 6p2 (6,7) 0 1 1 – ) √ 1 0 0 1 √ 9 (9,13) 1 – 0 1 √ 1 1 0 0 √ 12 (12,13 1 1 0 – √ ) 0 1 (7,15) – 1 1 1 √ 7 1 1 √Group3 1 0 (13,15 1 1 – 1 √ 13 1 1 √ )Grou 1 1 15 1 1 √p4It is found that U, V, W, X and Y are prime implicants. Now to find essential prime implicantsfrom Prime implicant chart. √ √ √ √ √ √ √ √ √ √Prime Implicants Minterms 1 2 3 5 6 7 8 9 12 13 15 ↓ U 5,7,13,15 X X X X V 8,9,12,13 X X X X W 2,3,6,7 X X X X X 1,5,9,13 X X X X Y 1,3,5,7 X X X XIn the column corresponding to minterms 2, 6, 8 and 15 there are only one entries and theprime implicants covering them are U, V and W. Therefore U, V and W are considered asessential prime implicants. Other than the above minterms these essential prime implicantscover additional minterms 3, 5, 7, 9, 12 and 13 too. But the minterm is not covered by theessential prime implicants. Therefore along with U, V and W either X or Y can be used to coverall minterms and represents the simplified Boolean expression.
- 54. WhereTherefore the simplified logic expression can be given as orSelf Assessment Question: Obtain the set of prime implicants for the following expressionMC0062(A)4.6 Multiple Output functionsMultiple Output functionsTill now the single valued expressions were realized using Boolean rules and simplification withKarnaugh Map methods. In practical case the problems are involved with the design of morethan one output with the given inputs. • Individual logic expression is simplified. Separate K – maps or Quine McClusky method are used for simplification.
- 55. • Both the expression uses same inputs and allowed to have same common minterms in addition to the specific minterms for two.Example: Simplify the given logic expressions with the given three inputs.Solution:Or
- 56. Case i.) Output is withCase ii.) Output is withCase ii) has a common term . Therefore realization requires lesser number of gatesCase i.) Output is withCase ii) Output is withExample: Minimize and implement the following multiple output functions
- 57. andSolution: Note that the realization of multiple function involves SOP realization for function f1and POS realization for function f2. K – map realization of functions for POS can be done byhaving alternate SOP representation.
- 58. Self Assessment Question: Minimize the following multiple output function using K – map andSummary • Boolean expressions can be simplified using the algebraic method or the Karnaugh map method. • There are two basic forms of Boolean expression the sum of product form and product of sum forms. • SOPs can be solved with minterm entries into the K-map with 1s for the respective terms • Grouping of the terms were defined with predefined logic. Grouping of two, four, eight or sixteen cells can be done with the entries 1s. • Simplified logic expression is written in SOP form and is realized with simple gate circuitry • POS from can also be solved with K-map • Quine Mcclusky is an other method to simplify the logic expression with possible more number of entries used. • Essesntial prime implicants are found using prime implicant chart. • Combinational logic expressions with multiple output function are realized using basic gagtes.Terminal Questions:
- 59. 1. Reduce the following expression using K – Map and implement using universal gate a. b. 2. Reduce using the K-map a. b. c. 3. Obtain the set of prime implicants for the following expression a. b. 4. Minimize the following multiple output function using K – map a. b. 5. Minimize the following multiple output function using K – map a. andb.
- 60. Unit 6 Latches and Flip FlopsThis unit has more clear and complete coverage on latches and flip flops. The edge triggered,master-slave flip flops were discussed. More emphasis is been given on D and JK flip-flops.MC0062(A)6.1 IntroductionIntroductionUsually switching circuits are either combinational or sequential type. The switching circuitsstudied till now are the combinational circuits whose output level at any instant of timedependent on the present inputs because these circuits have no memory or storage. Where as insequential circuits the logic used is such that output depends not only on the present inputs butalso on the previous input/outputs. Thus concept of requirement of memory units in the logic isto be studied.A simple memory unit is the flip-flop. A flip-flop can be thought as an assembly of logic gatesconnected such a way that it permits the information to be stored. Usually flip-flops used arememory elements stores 1 bit of information over a specific time. Flip-flops forms thefundamental components of shift registers and counters.Objectives:By the end of this chapter, reader should be able to explain • The concept of basic Latch • Active low and High concept used in Latches. • What are the gated latches? • What are the flip-flops and the concept of edge triggering • Concept of the use of asynchronous inputs like PRESET and CLEAR. • Concept of Master and Slave J-K flip-flop.MC0062(A)6.2 Latches The S-R LatchLatches: The S-R LatchThe latch is a bi-stable device. The term bi-stable refers with respect to the output of the devicethat can reside in either of two states and a feedback mechanism is used. These are similar to theflip-flops in that even flip-flops are bi-stable devices. The difference between the two is in themethod used for changing their output state.It is known as SET-RESET (S-R) latch. It has two inputs labeled as S and R and two outputslabeled as indicating a HIGH or 1 and indicating a LOW or 0. The two outputs and
- 61. are complementary to each other. The figure 6.1 shows logic symbol and the table 6.1 gives thetruth table of a S-R latch. Figure 6.1: S-R Latch Logic Symbol Inputs Output Comments S R 0 0 No change 0 1 0 1 RESET 1 0 1 0 SET 1 ? ? InvalidTable 6.1: Truth table of S-R LatchFrom table 6.1 when SET input or S is HIGH or 1, output SETs or becomes 1 (inturnbecomes 0) and when RESET input or R is HIGH output RESETs or becomes 0 (inturnbecomes 1). Thus the name S-R latch. If both the inputs S and R are LOW or 0 then the outputretain the previous state or there is no change in the output state compared to the previous state.If both the inputs are HIGH or 1, then the output of the latch is unpredictable or indicates invalidstate.Active HIGH S-R Latch (NOR gate S-R Latch)An NOR gate active high S-R latch can be constructed and is shown in figure 6.2 which has twocross connected or coupled NOR gate circuitry.Figure 6.2 active HIGH S-R Latch
- 62. Case i.) Assume the latch output is initially SET, = 1 and = 0. if the inputs are S = 0 and R=0. The inputs of G1 are 0 and 0 therefore output retains at = 1. The inputs of G2 are 0 and 1therefore its output is 0. Similarly if = 0 and = 1 initially and if the inputs are S = 0 and R=0. The inputs of G2 are 0 and 0 therefore its output retains at = 1. The inputs of G1 are 0 and 1therefore its output is 0.Therefore when S = 0 and R = 0 the output of the latch retains the previous state withoutany change, or no change in the output.Case ii.) Assume the latch output is initially SET, = 1 and = 0 and if the inputs are S = 1 andR =0 are applied to the latch. The inputs of G2 are 1 and 1, therefore its output is 0. The inputsof G1 are 0 and 0 therefore its output is 1. Similarly if = 0 and = 1 initially and if the inputsare S = 1 and R = 0. The inputs of G2 are 1 and 0 therefore its output = 0. The inputs of G1 are0 and a 0 therefore output is 1.Therefore when S = 1 and R = 0 the output of the latch SETs.Case iii.) Assume the latch output is initially SET, = 1 and = 0 and if the inputs are S = 0 andR =1 are applied to the latch. The inputs of G1 are 1 and 0, therefore its output is 0. The inputsof G2 are 0 and 0 therefore its output is 1. Similarly if = 0 and = 1 initially and if the inputsare S = 0 and R = 1. The inputs of G1 are 1 and 1 therefore its output is 0. The inputs of G2 are0 and a 0 therefore output is 1.Therefore when S = 0 and R = 1 the output of the latch RESETs.Case iv.) If the inputs are S = 1 and R =1 the corresponding outputs are = 0 and =0which is an invalid combinationThe operation of the active-HIGH NOR latch can be summarized as follows 1. SET = 0 and RESET = 0: has no effect on the output state from its previous state. 2. SET = 1 and RESET = 0: always sets the output = 1 and =0
- 63. 3. SET = 0 and RESET = 1: always resets the output = 0 and = 1 4. SET = 1 and RESET = 1: the condition tries to set and reset the output of the latch at the same time or output is unpredictable. This state is referred as invalid state.Active Low S-R Latch ( NAND Gate S-R Latch)A NAND gate active high S-R latch can be constructed and is shown in figure 6.3 which has twocross connected or coupled NAND gate circuitry. Figure 6.3: active LOW S-R Latch Inputs Output Comments S R 0 0 ? ? Invalid 0 1 1 0 SET 1 0 0 1 RESET 1 1 No changeTable 6.2: Truth table of S-R LatchThe operation of the active-LOW NAND latch can be summarized as follows 1. SET = 0 and RESET = 0: the condition tries to set and reset the output of the latch at the same time or output is unpredictable. This state is referred as invalid state. 2. SET = 0 and RESET = 1: always sets the output = 1 and =0 3. SET = 1 and RE 4. SET = 0: always resets the output = 0 and = 1 5. SET = 1 and RESET = 1: has no effect on the output state from its previous state.Active HIGH NAND latch can be implemented whose circuit diagram is shown in figure 6.4 andits truth table is shown in table 6.3
- 64. Figure 6.4: active HIGH S-R Latch Inputs Output Comments S R 0 0 No change 0 1 0 1 RESET 1 0 1 0 SET 1 1 ? ? InvalidTable 6.3: Truth table of S-R LatchSelf Assessment Question: 1. What do you mean by latch?Explain the working of NAND gate based latch operation.MC0062(A)6.3 Gated LatchesGated LatchesThe latches described in section 6.2 are known as asynchronous latches. The term asynchronousrepresents the output changes the state any time with respect to the conditions on the inputterminals. To enable the control over the latch output gated latches are used. A control pin or anenable pin EN is used which controls the output of the latch. The latches with the outputcontrolled with an enable input are known as gated latch or synchronous latch or flip-flop.Gated S-R Latches
- 65. When pin EN is HIGH the input S and R controls the output of the flip-flop. When EN pin isLOW the inputs become ineffective and no state change in the output of the flip-flop. Since aHIGH voltage level on the EN pin enables or controls the output of the latch, gated latches ofthese types are also known as level triggered latches or flip-flops.The logic symbol and the truth table of the gated latch are shown in figure 6.5 and table 6.4 andthe logic diagram of gated S-R flip-flop is shown in figure 6.6. Figure 6.5: S-R Latch Logic SymbolFig. 6.6: Gated Latch or Flip-flop Inputs Output Comments EN S R 0 0 High No change 0 1 High 0 1 RESET 1 0 High 1 0 SET 1 1 High ? ? InvalidTable 6.4: Truth table of gated S-R Latch
- 66. Figure 6.7: Waveform of gated S-R latchGated D-Latch or D-flip-flopThe S-R flip-flop makes use of four input combinations and in many applications S = R = 0 andS = R = 1 are never used. This represents that S and R are always complement to each other. Theinput R can be obtained by inverting the input S.The concept of D flip-flop has only one input data pin D along with the control logic over latchi.e EN pin. With the enable pin EN is HIGH and D = 1, we have S = 1 and R = 0 which SETs theinput. With the enable pin EN is HIGH and D = 0, we have S = 0 and R = 1 which RESETs theinput.The logic symbol and the truth table of the gated D-latch are shown in figure 6.8 and table 6.5and the logic diagram of gated S-R flip-flop is shown in figure 6.9. Figure 6.8: Gated D Latch Logic Symbol
- 67. Fig 6.9: Gated D-Latch or D-flip-flop Input Output EN Comments D 0 High 0 RESET 1 High 1 SET Table 6.5: Truth table of gated D-Latch or D-flip-flop Figure 6.10: Waveform of Gated D-LatchSelf Assessment Question: 1. What do you mean by gated latch?Explain the working of gated D-latch.MC0062(A)6.4 Edge triggered Flip-FlopsEdge triggered Flip-FlopsThe logic systems or digital systems operate either synchronously or asynchronously. Inasynchronous systems when one or more input changes the output of the logic system changes.In synchronous systems output changes with respect to a control or enable signal usually thesesignals are known as clock signal.A flip-flop circuit which uses the clock signal is known as clocked flip-flops. Many systemoutput changes occur when clock makes its transition. Clock transitions are defined as positivetransition when clock output changes from 0 to 1 and negative transition when clock outputchanges from 1 to 0. The system outputs make changes during either of these transitions areknown as edge triggered systems. Edge triggering is also known as dynamic triggering.
- 68. Flip-flops whose output changes during positive transition of the clock are known as positiveedge triggered flip-flop and the flip-flops which change its output during negative transition ofthe clock are known as negative edge triggered flip-flop.Positive edge triggering is indicated by a triangle at the clock terminal and negative edgetriggering is indicated by a triangle with a bubble at the clock terminal. There are three basictypes of edge-triggered flip-flops. S-R flip-flop, J-K flip-flop and D flip-flops.Edge triggered S-R Flip-Flop (S-R FF)Figure 6.11 and figure 6.12 indicates the positive edge triggered and negative edge triggered S-Rflip-flops. Figure 6.13 gives the simplified circuitry of edge triggered S-R FF. The S and Rinputs are known as synchronous control inputs. Without a clock pulse these inputs cannotchange the output state. The table 6.6 and table 6.7 give the truth table for S-R FF for positiveand negative edge triggering. Fig. 6.13: edge triggered S-R flip-flop Inputs Output Clock Clk Comments S R 0 0 ↑ No change
- 69. 0 1 ↑ 0 1 RESET 1 0 ↑ 1 0 SET 1 1 ↑ ? ? Invalid Table 6.6: Truth table for positive edge triggered S-R flip-flop Inputs Output Clock Clk Comments S R 0 0 ↓ No change 0 1 ↓ 0 1 RESET 1 0 ↓ 1 0 SET 1 1 ↓ ? ? Invalid Table 6.7: Truth table for negative edge triggered S-R flip-flop Figure 6.14: waveforms for positive edge triggered S-R flip-flopEdge triggered D-Flip-Flop (D-FF)Figure 6.11 and figure 6.12 indicates the positive edge triggered and negative edge triggered Dflip-flops. Figure 6.15 gives the simplified circuitry of edge triggered D FF. There is only oneinput D. Without a clock pulse the input cannot change the output state. The table 6.8 and table6.9 give the truth table for D-FF for positive and negative edge triggering.
- 70. Figure 6.15: edge triggered D-FF Input Clock Output Comments D Clk 0 ↑ 0 RESET 1 ↑ 1 SET Table 6.8: Truth table for positive edge triggered D- flip-flop Input Output Clock Clk Comments D 0 ↓ 0 RESET 1 ↓ 1 SET Table 6.9: Truth table for negative edge triggered D- flip-flop Figure 6.16: waveforms for negative edge triggered D- flip-flopEdge triggered J-K Flip-Flop (J-K FF)
- 71. Figure 6.11 and figure 6.12 indicate the positive edge triggered and negative edge triggered J-Kflip-flops. Figure 6.17 gives the simplified circuitry of edge triggered J-K FF. These are similar toS-R FFs except that J-K FFs has no invalid state. Therefore J-K FFs are versatile and mostly usedFFs. Without a clock pulse the inputs J and K cannot change the output state. The table 6.10 andtable 6.11 give the truth table for J-K FF for positive and negative edge triggering. Figure 6.17: edge triggered J-K FF 1. When J = 0 and K = 0: no change of state when a clock pulse is applied 2. When J = 0 and K = 1: output resets on positive/negative going edge of the clock pulse applied. 3. When J = 1 and K = 0: output sets on positive/negative going edge of the clock pulse applied. 4. When J = 1 and K = 1: output toggles between two states 0 and 1 for every positive/negative going edge of the clock pulse applied. Inputs Output Clock Clk Comments J K 0 0 ↑ No change 0 1 ↑ 0 1 RESET 1 0 ↑ 1 0 SET 1 1 ↑ Toggle Table 6.10: Truth table for positive edge triggered J-K flip-flop
- 72. Table 6.11: Truth table for negative edge triggered J-K flip-flop Figure 6.23: waveforms for negative edge triggered J-K flip-flopSelf Assessment Question: 1. What do you mean by level triggered FF and an edge triggered FF.Explain the working of positive and negative edge triggered J-K flip-flop.MC0062(A)6.5 Asynchronous inputsPRESET and CLEARAsynchronous inputs: PRESET and CLEAR
- 73. Edge triggered or synchronous FFs were studied in section 6.3 and 6.4 were the S-R, D and J-Kinputs are called as synchronous inputs. The effect of these signals on the output issynchronised with the clock pulse or the control pulse.ICs consistis of one or more asynchronous inputs which work independently of the synchronousand clock inputs. These asynchronous inputs are used to control the output of a given flip-flopto PRESET (priorly set to 1) or to CLEAR (priorly set to 0). Usually active low PRESET (PRE pin)and active low CLEAR (CLR pin) are used. Figure 6.19 gives the logic symbol of J-K FF with activeLOW PRESET and active LOW CLEAR pins and the truth table 6.12 gives its function. Figure 6.19: negative edge triggered J-K FF with active low PRESET and CLEARFigure 6.20: Logic diagram of edge triggered J-K FF with active low PRESET and CLEAR 1. PRE = 0 and CLR = 0 not used 2. PRE = 0 and CLR = 1 is used to PRESET or SET the output to 1. 3. PRE = 1 and CLR = 0 is used to CLEAR or RESET the output to 0.PRE = 1 and CLR = 1 is used to have clocked or edge triggered operation of FF.MC0062(A)6.6 Master-Slave J-K Flip FlopMaster-Slave J-K Flip FlopMaster-slave FFs were developed to make the synchronous operation more predictable. A knowntime delay is introduced between the time that the FF responds to a clock pulse and the time
- 74. response appears at its output. It is also known as pulse triggered flip-flop due to the fact that thelength of the time required for its output to change state equals the width of one clock pulse.A master-slave FF actually consists of two FFs. One is known as master and the other as slave.Control inputs are applied to the master FF prior to the clock pulse. On the rising edge of theclock pulse output of the master is defined by the control inputs. The falling edge of the clockpulse, the state of the master is transferred to the slave and output of the slave are taken as and . Note that the requirement in the master-slave that the input must be held stable while clock isHIGH. Figure 6.21 indicates the logic diagram of J-K master slave FF. Truth table is shown intable 6.12Figure 6.21: Logic diagram of JK Master Slave FFsTable 6.12: Truth table for negative edge triggered J-K flip-flop
- 75. Figure 6.22: waveforms for master slave J-K flip-flopT – Flip-FlopThe concept of J-K flip-flop with both J = 1 and K = 1 leads the output to toggle between the twopossible states 0 and 1. Thus the concept of Toggle flip-flop or T flip-flop is to have both J = 1and K = 1 all time or connect both J and K to HIGH all time and apply the clock pulse. Figure6.23 shows the logic block diagram of the T – flip-flop. The table 6.13 shows the truth table of T– flip-flop.Table 6.13: Truth table of T flip-flopSelf Assessment Question • Explain the working of Toggle flip flop • Give the timing diagram of the toggle flop flopSummary • Latches are bistable elements whose state normally depends on asynchronous inputs.

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