Mosfet must-read-2-slup169

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Mosfet must-read-2-slup169

  1. 1. Design And Application Guide For High Speed MOSFET Gate Drive Circuits By Laszlo BaloghABSTRACTThe main purpose of this paper is to demonstrate a systematic approach to design high performancegate drive circuits for high speed switching applications. It is an informative collection of topics offeringa “one-stop-shopping” to solve the most common design challenges. Thus it should be of interest topower electronics engineers at all levels of experience.The most popular circuit solutions and their performance are analyzed, including the effect of parasiticcomponents, transient and extreme operating conditions. The discussion builds from simple to morecomplex problems starting with an overview of MOSFET technology and switching operation. Designprocedure for ground referenced and high side gate drive circuits, AC coupled and transformer isolatedsolutions are described in great details. A special chapter deals with the gate drive requirements of theMOSFETs in synchronous rectifier applications.Several, step-by-step numerical design examples complement the paper.INTRODUCTIONMOSFET – is an acronym for Metal Oxide sourcing and sinking sufficient current to provideSemiconductor Field Effect Transistor and it is for fast insertion and extraction of the controllingthe key component in high frequency, high charge. From this point of view, the MOSFETsefficiency switching applications across the have to be driven just as “hard” during turn-onelectronics industry. It might be surprising, but and turn-off as a bipolar transistor to achieveFET technology was invented in 1930, some 20 comparable switching speeds. Theoretically, theyears before the bipolar transistor. The first switching speeds of the bipolar and MOSFETsignal level FET transistors were built in the late devices are close to identical, determined by the1950’s while power MOSFETs have been time required for the charge carriers to travelavailable from the mid 70’s. Today, millions of across the semiconductor region. Typical valuesMOSFET transistors are integrated in modern in power devices are approximately 20 to 200electronic components, from microprocessors, picoseconds depending on the size of the device.through “discrete” power transistors. The popularity and proliferation of MOSFETThe focus of this topic is the gate drive technology for digital and power applications isrequirements of the power MOSFET in various driven by two of their major advantages over theswitch mode power conversion applications. bipolar junction transistors. One of these benefits is the ease of use of the MOSFET devices in highMOSFET TECHNOLOGY frequency switching applications. The MOSFETThe bipolar and the MOSFET transistors exploit transistors are simpler to drive because theirthe same operating principle. Fundamentally, control electrode is isolated from the currentboth type of transistors are charge controlled conducting silicon, therefore a continuous ONdevices which means that their output current is current is not required. Once the MOSFETproportional to the charge established in the transistors are turned-on, their drive current issemiconductor by the control electrode. When practically zero. Also, the controlling charge andthese devices are used as switches, both must be accordingly the storage time in the MOSFETdriven from a low impedance source capable of transistors is greatly reduced. This basically 1
  2. 2. eliminates the design trade-off between on statevoltage drop – which is inversely proportional to SOURCEexcess control charge – and turn-off time. As aresult, MOSFET technology promises to use GATEmuch simpler and more efficient drive circuits n+ n+with significant economic benefits compared to p+ p+bipolar devices.Furthermore, it is important to highlight n- EPI layerespecially for power applications, that MOSFETs n+ Substrate DRAINhave a resistive nature. The voltage drop across (a)the drain source terminals of a MOSFET is a SOURCElinear function of the current flowing in the GATEsemiconductor. This linear relationship is n+ n+characterized by the RDS(on) of the MOSFET and p pknown as the on-resistance. On-resistance isconstant for a given gate-to-source voltage and n- EPI layertemperature of the device. As opposed to the n+ Substrate DRAIN-2.2mV/°C temperature coefficient of a p-n (b)junction, the MOSFETs exhibit a positive SOURCEtemperature coefficient of approximately GATE DRAIN0.7%/°C to 1%/°C. This positive temperature OXIDEcoefficient of the MOSFET makes it an ideal n+ n+candidate for parallel operation in higher power p napplications where using a single device would pnot be practical or possible. Due to the positive SubstrateTC of the channel resistance, parallel connected (c)MOSFETs tend to share the current evenlyamong themselves. This current sharing works Figure 1. Power MOSFET device typesautomatically in MOSFETs since the positive TC Double-diffused MOS transistors wereacts as a slow negative feedback system. The introduced in the 1970’s for power applicationsdevice carrying a higher current will heat up and evolved continuously during the years. Usingmore – don’t forget that the drain to source polycrystalline silicon gate structures and self-voltages are equal – and the higher temperature aligning processes, higher density integration andwill increase its RDS(on) value. The increasing rapid reduction in capacitances became possible.resistance will cause the current to decrease, The next significant advancement was offered bytherefore the temperature to drop. Eventually, an the V-groove or trench technology to furtherequilibrium is reached where the parallel increase cell density in power MOSFET devices.connected devices carry similar current levels. The better performance and denser integrationInitial tolerance in RDS(on) values and different don’t come free however, as trench MOS devicesjunction to ambient thermal resistances can cause are more difficult to manufacture.significant – up to 30% – error in currentdistribution. The third device type to be mentioned here is the lateral power MOSFETs. This device type isDevice types constrained in voltage and current rating due toAlmost all manufacturers have got their unique its inefficient utilization of the chip geometry.twist on how to manufacture the best power Nevertheless, they can provide significantMOSFETs, but all of these devices on the market benefits in low voltage applications, like incan be categorized into three basic device types. microprocessor power supplies or as synchronousThese are illustrated in Figure 1. rectifiers in isolated converters. 2
  3. 3. The lateral power MOSFETs have significantlylower capacitances, therefore they can switchmuch faster and they require much less gate drive Dpower.MOSFET ModelsThere are numerous models available to illustrate Ghow the MOSFET works, nevertheless findingthe right representation might be difficult. Mostof the MOSFET manufacturers provide Spiceand/or Saber models for their devices, but thesemodels say very little about the application trapsdesigners have to face in practice. They provideeven fewer clues how to solve the most common Sdesign challenges. (a)A really useful MOSFET model which woulddescribe all important properties of the devicefrom an application point of view would be verycomplicated. On the other hand, very simple and Dmeaningful models can be derived of theMOSFET transistor if we limit the applicabilityof the model to certain problem areas. GThe first model in Figure 2 is based on the actualstructure of the MOSFET device and can be usedmainly for DC analysis. The MOSFET symbol inFigure 2a represents the channel resistance andthe JFET corresponds to the resistance of theepitaxial layer. The length, thus the resistance of Sthe epi layer is a function of the voltage rating ofthe device as high voltage MOSFETs require (b)thicker epitaxial layer.Figure 2b can be used very effectively to modelthe dv/dt induced breakdown characteristic of a DMOSFET. It shows both main breakdownmechanisms, namely the dv/dt induced turn-on ofthe parasitic bipolar transistor - present in allpower MOSFETs - and the dv/dt induced turn-onof the channel as a function of the gate Gterminating impedance. Modern powerMOSFETs are practically immune to dv/dttriggering of the parasitic npn transistor due tomanufacturing improvements to reduce theresistance between the base and emitter regions.It must be mentioned also that the parasitic Sbipolar transistor plays another important role. Its (c)base – collector junction is the famous bodydiode of the MOSFET. Figure 2. Power MOSFET models 3
  4. 4. Figure 2c is the switching model of the The CDS capacitor is also non-linear since it is theMOSFET. The most important parasitic junction capacitance of the body diode. Itscomponents influencing switching performance voltage dependence can be described as:are shown in this model. Their respective roles C DS,0will be discussed in the next chapter which is C DS ≈dedicated to the switching procedure of the K 2 ⋅ VDSdevice. Unfortunately, non of the above mentioned capacitance values are defined directly in theMOSFET Critical Parameters transistor data sheets. Their values are givenWhen switch mode operation of the MOSFET is indirectly by the CISS, CRSS, and COSS capacitorconsidered, the goal is to switch between the values and must be calculated as:lowest and highest resistance states of the devicein the shortest possible time. Since the practical C GD = C RSSswitching times of the MOSFETs (~10ns to 60ns) C GS = C ISS − C RSSis at least two to three orders of magnitude longer C DS = C OSS − C RSSthan the theoretical switching time (~50ps to200ps), it seems important to understand the Further complication is caused by the CGDdiscrepancy. Referring back to the MOSFET capacitor in switching applications because it ismodels in Figure 2, note that all models include placed in the feedback path between the inputthree capacitors connected between the three and output of the device. Accordingly, itsterminals of the device. Ultimately, the switching effective value in switching applications can beperformance of the MOSFET transistor is much larger depending on the drain sourcedetermined by how quickly the voltages can be voltage of the MOSFET. This phenomenon ischanged across these capacitors. called the “Miller” effect and it can be expressed as:Therefore, in high speed switching applications,the most important parameters are the parasitic C GD,eqv = (1 + g fs ⋅ R L ) ⋅ C GDcapacitances of the device. Two of these Since the CGD and CDS capacitors are voltagecapacitors, the CGS and CGD capacitors dependent, the data sheet numbers are valid onlycorrespond to the actual geometry of the device at the test conditions listed. The relevant averagewhile the CDS capacitor is the capacitance of the capacitances for a certain application have to bebase collector diode of the parasitic bipolar calculated based on the required charge totransistor (body diode). establish the actual voltage change across theThe CGS capacitor is formed by the overlap of the capacitors. For most power MOSFETs thesource and channel region by the gate electrode. following approximations can be useful:Its value is defined by the actual geometry of the VDS,specregions and stays constant (linear) under different C GD,ave = 2 ⋅ C RSS,spec ⋅operating conditions. VDS,offThe CGD capacitor is the result of two effects. VDS,specPart of it is the overlap of the JFET region and C OSS,ave = 2 ⋅ C OSS,spec ⋅the gate electrode in addition to the capacitance VDS,offof the depletion region which is non-linear. The The next important parameter to mention is theequivalent CGD capacitance is a function of the gate mesh resistance, RG,I. This parasiticdrain source voltage of the device approximated resistance describes the resistance associated byby the following formula: the gate signal distribution within the device. Its C GD,0 importance is very significant in high speedC GD ≈ switching applications because it is in between 1 + K 1 ⋅ VDS the driver and the input capacitor of the device, directly impeding the switching times and the 4
  5. 5. dv/dt immunity of the MOSFET. This effect is Other important parameters like the sourcerecognized in the industry, where real high speed inductance (LS) and drain inductance (LD) exhibitdevices like RF MOSFET transistors use metal significant restrictions in switching performance.gate electrodes instead of the higher resistance Typical LS and LD values are listed in the datapolysilicon gate mesh for gate signal distribution. sheets, and they are mainly dependant on theThe RG,I resistance is not specified in the data package type of the transistor. Their effects cansheets, but in certain applications it can be a very be investigated together with the externalimportant characteristic of the device. In the back parasitic components usually associated withof this paper, Appendix A4 shows a typical layout and with accompanying external circuitmeasurement setup to determine the internal gate elements like leakage inductance, a current senseresistor value with an impedance bridge. resistor, etc.Obviously, the gate threshold voltage is also a For completeness, the external series gate resistorcritical characteristic. It is important to note that and the MOSFET driver’s output impedancethe data sheet VTH value is defined at 25°C and at must be mentioned as determining factors in higha very low current, typically at 250μA. performance gate drive designs as they have aTherefore, it is not equal to the Miller plateau profound effect on switching speeds andregion of the commonly known gate switching consequently on switching losses.waveform. Another rarely mentioned fact aboutVTH is its approximately –7mV/°C temperature SWITCHING APPLICATIONScoefficient. It has particular significance in gate Now, that all the players are identified, let’sdrive circuits designed for logic level MOSFET investigate the actual switching behavior of thewhere VTH is already low under the usual test MOSFET transistors. To gain a betterconditions. Since MOSFETs usually operate at understanding of the fundamental procedure, theelevated temperatures, proper gate drive design parasitic inductances of the circuit will bemust account for the lower VTH when turn-off neglected. Later their respective effects on thetime, and dv/dt immunity is calculated as shown basic operation will be analyzed individually.in Appendix A and F. Furthermore, the following descriptions relate toThe transconductance of the MOSFET is its clamped inductive switching because mostsmall signal gain in the linear region of its MOSFET transistors and high speed gate driveoperation. It is important to point out that every circuits used in switch mode power supplies worktime the MOSFET is turned-on or turned-off, it in that operating mode.must go through its linear operating mode wherethe current is determined by the gate-to-source IDCvoltage. The transconductance, gfs, is the smallsignal relationship between drain current andgate-to-source voltage: dI RGATEg fs = D dVGSAccordingly, the maximum current of theMOSFET in the linear region is given by: VOUTI D = (VGS − Vth ) ⋅ g fs VDRVRearranging this equation for VGS yields theapproximate value of the Miller plateau as afunction of the drain current. IVGS,Miller = Vth + D Figure 3. Simplified clamped inductive switching g fs model 5
  6. 6. The simplest model of clamped inductive This period is called the turn-on delay, becauseswitching is shown in Figure 3, where the DC both the drain current and the drain voltage of thecurrent source represents the inductor. Its current device remain unchanged.can be considered constant during the short Once the gate is charged to the threshold level,switching interval. The diode provides a path for the MOSFET is ready to carry current. In thethe current during the off time of the MOSFET second interval the gate is rising from VTH to theand clamps the drain terminal of the device to the Miller plateau level, VGS,Miller. This is the linearoutput voltage symbolized by the battery. operation of the device when current is proportional to the gate voltage. On the gate side,Turn-On procedure current is flowing into the CGS and CGDThe turn-on event of the MOSFET transistor can capacitors just like in the first time interval andbe divided into four intervals as depicted in the VGS voltage is increasing. On the output sideFigure 4. of the device, the drain current is increasing, V D RV while the drain-to-source voltage stays at the ID D previous level (VDS,OFF). This can be understood C GD looking at the schematic in Figure 3. Until all the R HI R G A TE G R G ,I C DS current is transferred into the MOSFET and the IG diode is turned-off completely to be able to block CGS reverse voltage across its pn junction, the drain S voltage must stay at the output voltage level. Entering into the third period of the turn-on procedure the gate is already charged to the VGS sufficient voltage (VGS,Miller) to carry the entire load current and the rectifier diode is turned off. That now allows the drain voltage to fall. While VTH the drain voltage falls across the device, the gate- IG to-source voltage stays steady. This is the Miller plateau region in the gate voltage waveform. All the gate current available from the driver is diverted to discharge the CGD capacitor to V DS facilitate the rapid voltage change across the drain-to-source terminals. The drain current of the device stays constant since it is now limited by the external circuitry, i.e. the DC current ID source. The last step of the turn-on is to fully enhance the conducting channel of the MOSFET by applying a higher gate drive voltage. The final amplitude 1 2 3 4 of VGS determines the ultimate on-resistance of the device during its on-time. Therefore, in this Figure 4. MOSFET turn-on time intervals fourth interval, VGS is increased from VGS,Miller toIn the first step the input capacitance of the its final value, VDRV. This is accomplished bydevice is charged from 0V to VTH. During this charging the CGS and CGD capacitors, thus gateinterval most of the gate current is charging the current is now split between the two components.CGS capacitor. A small current is flowing through While these capacitors are being charged, thethe CGD capacitor too. As the voltage increases at drain current is still constant, and the drain-to-the gate terminal and the CGD capacitor’s voltage source voltage is slightly decreasing as the on-has to be slightly reduced. resistance of the device is being reduced. 6
  7. 7. Turn-Off procedureThe description of the turn-off procedure for the In the second period, the drain-to-source voltageMOSFET transistor is basically back tracking the of the MOSFET rises from ID⋅RDS(on) to the finalturn-on steps from the previous section. Start VDS(off) level, where it is clamped to the outputwith VGS being equal to VDRV and the current in voltage by the rectifier diode according to thethe device is the full load current represented by simplified schematic of Figure 3. During thisIDC in Figure 3. The drain-to-source voltage is time period – which corresponds to the Millerbeing defined by IDC and the RDS(on) of the plateau in the gate voltage waveform - the gateMOSFET. The four turn-off steps are shown in current is strictly the charging current of the CGDFigure 5. for completeness. capacitor because the gate-to-source voltage is V DRV constant. This current is provided by the bypass D ID capacitor of the power stage and it is subtracted CGD from the drain current. The total drain current R LO R G ATE R G,I still equals the load current, i.e. the inductor current represented by the DC current source in G C DS Figure 3. IG C GS S The beginning of the third time interval is signified by the turn-on of the diode, thus providing an alternative route to the load current. The gate voltage resumes falling from VGS,Miller to V GS VTH. The majority of the gate current is coming out of the CGS capacitor, because the CGD V TH capacitor is virtually fully charged from the previous time interval. The MOSFET is in linear IG operation and the declining gate-to-source voltage causes the drain current to decrease and reach near zero by the end of this interval. Meanwhile the drain voltage is steady at VDS(off) V DS due to the forward biased rectifier diode. The last step of the turn-off procedure is to fully discharge the input capacitors of the device. VGS is further reduced until it reaches 0V. The bigger ID portion of the gate current, similarly to the third turn-off time interval, supplied by the CGS capacitor. The drain current and the drain voltage in the device are unchanged. 1 2 3 4 Summarizing the results, it can be concluded that the MOSFET transistor can be switched between Figure 5. MOSFET turn-off time intervals its highest and lowest impedance states (eitherThe first time interval is the turn-off delay which turn-on or turn-off) in four time intervals. Theis required to discharge the CISS capacitance from lengths of all four time intervals are a function ofits initial value to the Miller plateau level. the parasitic capacitance values, the requiredDuring this time the gate current is supplied by voltage change across them and the available gatethe CISS capacitor itself and it is flowing through drive current. This emphasizes the importance ofthe CGS and CGD capacitors of the MOSFET. The the proper component selection and optimumdrain voltage of the device is slightly increasing gate drive design for high speed, high frequencyas the overdrive voltage is diminishing. The switching applications.current in the drain is unchanged. 7
  8. 8. Characteristic numbers for turn-on, turn-off This graph gives a relatively accurate worst casedelays, rise and fall times of the MOSFET estimate of the gate charge as a function of theswitching waveforms are listed in the transistor gate drive voltage. The parameter used todata sheets. Unfortunately, these numbers generate the individual curves is the drain-to-correspond to the specific test conditions and to source off state voltage of the device. VDS(off)resistive load, making the comparison of different influences the Miller charge – the area below themanufacturers’ products difficult. Also, flat portion of the curves – thus also, the totalswitching performance in practical applications gate charge required in a switching cycle. Oncewith clamped inductive load is significantly the total gate charge is obtained from Figure 6,different from the numbers given in the data the gate charge losses can be calculated as:sheets. PGATE = VDRV ⋅ Q G ⋅ f DRVPower losses where VDRV is the amplitude of the gate driveThe switching action in the MOSFET transistor waveform and fDRV is the gate drive frequency –in power applications will result in some which is in most cases equal to the switchingunavoidable losses, which can be divided into frequency. It is interesting to notice that thetwo categories. QG⋅fDRV term in the previous equation gives theThe simpler of the two loss mechanisms is the average bias current required to drive the gate.gate drive loss of the device. As described before, The power lost to drive the gate of the MOSFETturning-on or off the MOSFET involves charging transistor is dissipated in the gate drive circuitry.or discharging the CISS capacitor. When the Referring back to Figures 4 and 5, the dissipatingvoltage across a capacitor is changing, a certain components can be identified as the combinationamount of charge has to be transferred. The of the series ohmic impedances in the gate driveamount of charge required to change the gate path. In every switching cycle the required gatevoltage between 0V and the actual gate drive charge has to pass through the driver outputvoltage VDRV, is characterized by the typical gate impedances, the external gate resistor, and thecharge vs. gate-to-source voltage curve in the internal gate mesh resistance. As it turns out, theMOSFET datasheet. An example is shown in power dissipation is independent of how quicklyFigure 6. the charge is delivered through the resistors. Using the resistor designators from Figures 4 and 5, the driver power dissipation can be expressed Vgs, Gate-to-Source Voltage (V) as: 1 R ⋅V ⋅Q ⋅f PDRV,ON = ⋅ HI DRV G DRV 2 R HI + R GATE + R G,I VDRV 1 R LO ⋅ VDRV ⋅ Q G ⋅ f DRV PDRV,OFF = ⋅ 2 R LO + R GATE + R G,I PDRV = PDRV,ON + PDRV,OFF In the above equations, the gate drive circuit is VDS represented by a resistive output impedance and this assumption is valid for MOS based gate QG drivers. When bipolar transistors are utilized in the gate drive circuit, the output impedance becomes non-linear and the equations do not Qg, Total Gate Charge (nC) yield the correct answers. It is safe to assume that with low value gate resistors (<5Ω) most gateFigure 6. Typical gate charge vs. gate-to-source drive losses are dissipated in the driver. If RGATE voltage is sufficiently large to limit IG below the output 8
  9. 9. current capability of the bipolar driver, the drain voltage changes from VDS(off) to 0V, themajority of the gate drive power loss is then approximate switching times are given as:dissipated in RGATE. V − VTHIn addition to the gate drive power loss, the t2 = C ISS ⋅ GS,Miller I G2transistors accrue switching losses in thetraditional sense due to high current and high VDS,off t3 = C RSS ⋅voltage being present in the device I G3simultaneously for a short period. In order to During t2 the drain voltage is VDS(off) and theensure the least amount of switching losses, the current is ramping from 0A to the load current, ILduration of this time interval must be minimized. while in t3 time interval the drain voltage isLooking at the turn-on and turn-off procedures of falling from VDS(off) to near 0V. Again, usingthe MOSFET, this condition is limited to linear approximations of the waveforms, theintervals 2 and 3 of the switching transitions in power loss components for the respective timeboth turn-on and turn-off operation. These time intervals can be estimated:intervals correspond to the linear operation of thedevice when the gate voltage is between VTH and t2 I P2 = ⋅ VDS,off ⋅ LVGS,Miller, causing changes in the current of the T 2device and to the Miller plateau region when the t3 VDS,offdrain voltage goes through its switching P3 = ⋅ ⋅ IL T 2transition. where T is the switching period. The totalThis is a very important realization to properly switching loss is the sum of the two lossdesign high speed gate drive circuits. It highlights components, which yields the followingthe fact that the most important characteristic of simplifed expression:the gate driver is its source-sink currentcapability around the Miller plateau voltage level. VDS(off) ⋅ I L t2 + t3 PSW = ⋅Peak current capability, which is measured at full 2 TVDRV across the driver’s output impedance, has Even though the switching transitions are wellvery little relevance to the actual switching understood, calculating the exact switching lossesperformance of the MOSFET. What really is almost impossible. The reason is the effect ofdetermines the switching times of the device is the parasitic inductive components which willthe gate drive current capability when the gate-to- significantly alter the current and voltagesource voltage, i.e. the output of the driver is at waveforms, as well as the switching times during~5V (~2.5V for logic level MOSFETs). the switching procedures. Taking into account theA crude estimate of the MOSFET switching effect of the different source and drainlosses can be calculated using simplified linear inductances of a real circuit would result inapproximations of the gate drive current, drain second order differential equations to describecurrent and drain voltage waveforms during the actual waveforms of the circuit. Since theperiods 2 and 3 of the switching transitions. First variables, including gate threshold voltage,the gate drive currents must be determined for the MOSFET capacitor values, driver outputsecond and third time intervals respectively: impedances, etc. have a very wide tolerance, the above described linear approximation seems to V − 0.5 ⋅ (VGS,Miller + VTH ) be a reasonable enough compromise to estimate I G2 = DRV R HI + R GATE + R G.I switching losses in the MOSFET. VDRV − VGS,MillerI G3 = Effects of parasitic components R HI + R GATE + R G.I The most profound effect on switchingAssuming that IG2 charges the input capacitor of performance is exhibited by the sourcethe device from VTH to VGS,Miller and IG3 is the inductance. There are two sources for parasiticdischarge current of the CRSS capacitor while the source inductance in a typical circuit, the source 9
  10. 10. bond wire neatly integrated into the MOSFET Smaller resistor values will result an overshoot inpackage and the printed circuit board wiring the gate drive voltage waveform, but also resultinductance between the source lead and the in faster turn-on speed. Higher resistor valuescommon ground. This is usually referenced as the will underdamp the oscillation and extend thenegative electrode of the high frequency filter switching times without offering any benefit forcapacitor around the power stage and the bypass the gate drive design.capacitor of the gate driver. Current sense The second effect of the source inductance is aresistors in series with the source can add negative feedback whenever the drain current ofadditional inductance to the previous two the device is changing rapidly. This effect iscomponents. present in the second time interval of the turn-onThere are two mechanisms in the switching and in the third time interval of the turn-offprocedure which involve the source inductor. At procedure. During these periods the gate voltagethe beginning of the switching transitions the gate is between VTH and VGS,Miller, and the gate currentcurrent is increasing very rapidly as illustrated in is defined by the voltage across the driveFigures 4 and 5. This current must flow through impedance, VDRV-VGS. In order to increase thethe source inductance and will be slowed down drain current quickly, significant voltage has tobased on the inductor value. Consequently, the be applied across the source inductance. Thistime required to charge/discharge the input voltage reduces the available voltage across thecapacitance of the MOSFET gets longer, mainly drive impedance, thus reduces the rate of changeinfluencing the turn-on and turn-off delays (step in the gate drive voltage which will result in a1). Furthermore, the source inductor and the CISS lower di/dt of the drain current. The lower di/dtcapacitor form a resonant circuit as shown in requires less voltage across the sourceFigure 7. inductance. A delicate balance of gate current and drain di/dt is established through the negative feedback by the source inductor. RG LS The other parasitic inductance of the switching CISS network is the drain inductance which is again VDRV composed of several components. They are the packaging inductance inside the transistor package, all the inductances associated with interconnection and the leakage inductance of a transformer in isolated power supplies. TheirFigure 7. Gate drive resonant circuit components effect can be lumped together since they are inThe resonant circuit is exited by the steep edges series with each other. They act as a turn-onof the gate drive voltage waveform and it is the snubber for the MOSFET. During turn-on theyfundamental reason for the oscillatory spikes limit the di/dt of the drain current and reduce theobserved in most gate drive circuits. Fortunately, drain-to-source voltage across the device by thethe otherwise very high Q resonance between factor of LD⋅di/dt. In fact, LD can reduce the turn-CISS and LS is damped or can be damped by the on switching losses significantly. While higherseries resistive components of the loop which LD values seem beneficial at turn-on, they causeinclude the driver output impedance, the external considerable problems at turn-off when the draingate resistor, and the internal gate mesh resistor. current must ramp down quickly. To support theThe only user adjustable value, RGATE, can be rapid reduction in drain current due to the turn-calculated for optimum performance by: off of the MOSFET, a voltage in the opposite direction with respect to turn-on must be across LSR GATE,OPT = 2 ⋅ − (R DRV + R G,I ) LD. This voltage is above the theoretical VDS(off) C ISS level, producing an overshoot in the drain-to- source voltage and an increase in turn-off switching losses. 10
  11. 11. Accurate mathematical analysis of the complete Another limiting factor for MOSFET die sizeswitching transitions including the effects of with direct gate drive is the power dissipation ofparasitic inductances are available in the the driver within the controller. An external gateliterature but points beyond the scope of this resistor can mitigate this problem as discussedpaper. before. When direct gate drive is absolutely necessary for space and/or cost savings, specialGROUND REFERENCED GATE considerations are required to provide appropriateDRIVE bypassing for the controller. The high current spikes driving the gate of the MOSFET canPWM Direct drive disrupt the sensitive analog circuitry inside theIn power supply applications, the simplest way of PWM controller. As MOSFET die size increases,driving the gate of the main switching transistor so too does gate charge required. The selection ofis to utilize the gate drive output of the PWM the proper bypass capacitor calls for a little bitcontroller as shown in Figure 8. more scientific approach than picking the usual 0.1μF or 1μF bypass capacitor. VDRV (VBIAS) Sizing the bypass capacitor In this chapter the calculation of the MOSFET VCC gate driver’s bypass capacitor is demonstrated. PWM This capacitor is the same as the PWM controller RGATE controller’s bypass capacitor in direct gate drive OUT application because that is the capacitor which provides the gate drive current at turn-on. In case of a separate driver circuit, whether a gate drive GND IC or discrete solution, this capacitor must be distance! placed close, preferably directly across the bias and ground connection of the driver. There are two current components to consider. Figure 8. Direct gate drive circuit One is the quiescent current which can change byThe most difficult task in direct gate drives is to a 10x factor based on the input state of someoptimize the circuit layout. As indicated in Figure integrated drivers. This itself will cause a duty8, there might be considerable distance between cycle dependent ripple across the bypassthe PWM controller and the MOSFET. This capacitor which can be calculated as:distance introduces a parasitic inductance due to I ⋅Dthe loop formed by the gate drive and ground ΔVQ = Q,HI MAX C DRV ⋅ f DRVreturn traces which can slow down the switchingspeed and can cause ringing in the gate drive where it is assumed that the driver’s quiescentwaveform. Even with a ground plane, the current is higher when its input is driven high.inductance can not be completely eliminated The other ripple component is the gate current.since the ground plane provides a low inductance Although the actual current amplitude is notpath for the ground return current only. To reduce know in most cases, the voltage ripple across thethe inductance linked to the gate drive bypass capacitor can be determined based on theconnection, a wider PCB trace is desirable. value of the gate charge. At turn-on, this chargeAnother problem in direct gate drive is the is taken out of the bypass capacitor andlimited drive current capability of the PWM transferred to the MOSFET input capacitor.controllers. Very few integrated circuits offer Accordingly the ripple is given by:more than 1A peak gate drive capability. This Qwill limit the maximum die size which can be ΔVQG = Gdriven at a reasonable speed by the controller. C DRV 11
  12. 12. Using the principle of superposition and solving drop Schottky diodes are generally needed tothe equations for CDRV, the bypass capacitor protect the outputs. The diodes must be placedvalue for a tolerable ripple voltage (ΔV) can be very close to the output pin and to the bypassfound: capacitor of the driver. It is important to point out D also, that the diodes protect the driver only, they I Q,HI ⋅ MAX + Q G are not clamping the gate-to-source voltage f DRV against excessive ringing especially with directC DRV = ΔV drive where the control IC might be far awaywhere IQ,HI is the quiescent current of the driver from the gate-source terminals of the MOSFET.when its input is driven high, DMAX is themaximum duty cycle of the driver while the input Bipolar totem-pole drivercan stay high, fDRV is the operating frequency of One of the most popular and cost effective drivethe driver, and QG is the total gate charge based circuit for driving MOSFETs is a bipolar, non-on the amplitude of the gate drive and drain-to- inverting totem-pole driver as shown in Figuresource off state voltages. 10.Driver protection VBIAS VDRVAnother must-do with direct drive and with gate Rdrive ICs using bipolar output stage is to provide VCCsuitable protection for the output bipolar PWMtransistors against reverse currents. As indicated controller RGATEin the simplified diagram in Figure 9, the output OUTstage of the integrated bipolar drivers is built RBfrom npn transistors due to their more efficientarea utilization and better performance. GND VDRV distance! PWM or VCC Driver IC Figure 10. Bipolar totem-pole MOSFET driver Like all external drivers, this circuit handles the OUT RGATE current spikes and power losses making the operating conditions for the PWM controller more favorable. Of course, they can be and should be placed right next to the power MOSFET they are driving. That way the high GND current transients of driving the gate are localized in a very small loop area, reducing the value of Figure 9. Gate drive with integrated bipolar parasitic inductances. Even though the driver is transistors built from discrete components, it needs its own bypass capacitor placed across the collectors ofThe npn transistors can handle currents in one the upper npn and the lower pnp transistors.direction only. The high side npn can source but Ideally there is a smoothing resistor or inductorcan not sink current while the low side is exactly between the bypass capacitor of the driver andthe opposite. Unavoidable oscillations between the bypass capacitor of the PWM controller forthe source inductor and the input capacitor of the increased noise immunity. The RGATE resistor ofMOSFET during turn-on and turn-off necessitate Figure 10 is optional and RB can be sized tothat current should be able to flow in both provide the required gate impedance based on thedirections at the output of the driver. To provide large signal beta of the driver transistors.a path for reverse currents, low forward voltage 12
  13. 13. An interesting property of the bipolar totem-pole Speed enhancement circuitsdriver that the two base-emitter junctions protect When speed enhancement circuits are mentionedeach other against reverse breakdown. designers exclusively consider circuits whichFurthermore, assuming that the loop area is really speed-up the turn-off process of the MOSFET.small and RGATE is negligible, they can clamp the The reason is that the turn-on speed is usuallygate voltage between VBIAS+VBE and GND-VBE limited by the turn-off, or reverse recovery speedusing the base-emitter diodes of the transistors. of the rectifier component in the power supply.Another benefit of this solution, based on the As discussed with respect to the inductivesame clamp mechanism, is that the npn-pnp clamped model in Figure 3, the turn-on of thetotem-pole driver does not require any Schottky MOSFET coincides with the turn-off of thediode for reverse current protection. rectifier diode. Therefore, the fastest switching action is determined by the reverse recoveryMOSFET totem-pole driver characteristic of the diode, not by the strength ofThe MOSFET equivalent of the bipolar totem- the gate drive circuit. In an optimum design thepole driver is pictured in Figure 11. All the gate drive speed at turn-on is matched to thebenefits mentioned about the bipolar totem-pole diode switching characteristic. Considering alsodriver are equally applicable to this that the Miller region is closer to GND than toimplementation. the final gate drive voltage VDRV, a higher VBIAS VDRV voltage can be applied across the driver output impedance and the gate resistor. Usually the R obtained turn-on speed is sufficient to drive the VCC MOSFET. PWM The situation is vastly different at turn-off. In controller RGATE theory, the turn-off speed of the MOSFET OUT depends only on the gate drive circuit. A higher current turn-off circuit can discharge the input capacitors quicker, providing shorter switching GND times and consequently lower switching losses. The higher discharge current can be achieved by distance! a lower output impedance MOSFET driver and/or a negative turn-off voltage in case of the Figure 11. MOSFET based totem-pole driver common N-channel device. While fasterUnfortunately, this circuit has several drawbacks switching can potentially lower the switchingcompared to the bipolar version which explain losses, the turn-off speed-up circuits increase thethat it is very rarely implemented discretely. The ringing in the waveforms due to the higher turn-circuit of Figure 11 is an inverting driver, off di/dt and dv/dt of the MOSFET. This istherefore the PWM output signal must be something to consider in selecting the properinverted. In addition, the suitable MOSFET voltage rating and EMI containment for thetransistors are more expensive than the bipolar power device.ones and they will have a large shoot through Turn-off diodecurrent when their common gate voltage is in The following examples of turn-off circuits aretransition. This problem can be circumvented by demonstrated on simple ground referenced gateadditional logic or timing components which drive circuits, but are equally applicable to othertechnique is extensively used in IC implementations discussed later in the paper. Theimplementations. simplest technique is the anti-parallel diode, as shown in Figure 12. 13
  14. 14. VDRV VDRV VCC VCC DON Driver Driver RGATE RGATE OUT OUT QOFF DOFF GND GND Figure 12. Simple turn-off speed enhancement Figure 13. Local pnp turn-off circuit circuit The turn-off current does not go back to theIn this circuit RGATE allows adjustment of the driver, it does not cause ground bounce problemsMOSFET turn-on speed. During turn-off the anti- and the power dissipation of the driver is reducedparallel diode shunts out the resistor. DOFF works by a factor of two. The turn-off transistor shuntsonly when the gate current is higher than: out the gate drive loop inductance, the potential V current sense resistor, and the output impedanceI G > D,FWD of the driver. Furthermore, QOFF never saturates R GATE which is important to be able to turn it on and offtypically around 150mA using a 1N4148 and quickly. Taking a closer look at the circuitaround 300mA with a BAS40 Schottky anti- reveals that this solution is a simplified bipolarparallel diode. Consequently, as the gate-to- totem-pole driver, where the npn pull-upsource voltage approaches 0V the diode helps transistor is replaced by a diode. Similarly to theless and less. As a result, this circuit will provide totem-pole driver, the MOSFET gate is clampeda significant reduction in turn-off delay time, but by the turn-off circuit between GND-0.7V andonly incremental improvement on switching VDRV+0.7V approximately, eliminating the risktimes and dv/dt immunity. Another disadvantage of excessive voltage stress at the gate. The onlyis that the gate turn-off current still must flow known shortcoming of the circuit is that it can notthrough the driver’s output impedance. pull the gate all the way to 0V because of the voltage drop across the base-emitter junction ofPNP turn-off circuit QOFF.Undoubtedly the most popular arrangement forfast turn-off is the local pnp turn-off circuit of NPN turn-off circuitFigure 13. With the help of QOFF, the gate and the The next circuit to examine is the local npn turn-source are shorted locally at the MOSFET off circuit, illustrated in Figure 14. Similarly toterminals during turn-off. RGATE limits the turn- the pnp solution, the gate discharge current ison speed, and DON provides the path for the turn- well localized. The npn transistor holds the gateon current. Also, DON protects the base-emitter closer to GND than its pnp counterpart. Also, thisjunction of QOFF against reverse breakdown at the implementation provides a self biasingbeginning of the turn-on procedure. mechanism to keep the MOSFET off duringThe most important advantage of this solution is power up.that the high peak discharge current of the Unfortunately, this circuit has some significantMOSFET input capacitance is confined in the drawbacks. The npn turn-off transistor, QOFF is ansmallest possible loop between the gate, source inverting stage, it requires an inverted PWMand collector, emitter connections of the two signal provided by QINV.transistors. 14
  15. 15. to the CISS capacitance of the main power VDRV MOSFET. This will increase the effective “Total Gate Charge” the driver has to provide. Also to VCC DON consider, the gate of the main MOSFET is floating before the outputs of the driver IC Driver becomes intelligent during power up. RGATE OUT QOFF dv/dt protection There are two situations when the MOSFET has QINV to be protected against dv/dt triggered turn-on. GND One is during power up where protection can usually be provided by a resistor between the gate and source terminals of the device. The pullFigure 14. Local npn self biasing turn-off circuit down resistor value depends on the worst case dv/dt of the power rail during power upThe inverter draws current from the driver during according to:the on time of the MOSFET, lowering theefficiency of the circuit. Furthermore, QINV VTH ⎛ dt ⎞ RGS < ⋅⎜ ⎟saturates during the on-time which can prolong CGD ⎝ dv ⎠TURN −ONturn-off delay in the gate drive. In this calculation the biggest challenge is to findNMOS turn-off circuit the highest dv/dt which can occur during power up and provide sufficient protection for thatAn improved, lower parts count implementation particular dv/dt.of this principle is offered in Figure 15, using adual driver to provide the inverted PWM signal The second situation is in normal operation whenfor a small N-channel discharge transistor. turn-off dv/dt is forced across the drain-to-source terminals of the power switch while it is off. This VDRV situation is more common than one may originally anticipate. All synchronous rectifier switches are operated in this mode as will be VCC discussed later. Most resonant and soft switching RGATE converters can force a dv/dt across the main OUT switch right after its turn-off instance, driven by Driver the resonant components of the power stage. OUT QOFF Since these dv/dt’s are significantly higher than during power up and VTH is usually lower due to GND the higher operating junction temperature, protection must be provided by the low output impedance of the gate drive circuit.Figure 15. Improved N-channel MOS based turn- The first task is to determine the maximum dv/dt off circuit which can occur under worst case conditions. The next step in evaluating the suitability of aThis circuit offers very fast switching and particular device to the application is to calculatecomplete discharge of the MOSFET gate to 0V. its natural dv/dt limit, imposed by the internalRGATE sets the turn-on speed like before, but is gate resistance and the CGD capacitance of thealso utilized to prevent any shoot through MOSFET. Assuming ideal (zero Ohm) externalcurrents between the two outputs of the driver in drive impedance the natural dv/dt limit is:case of imperfect timing of the drive signals.Another important fact to consider is that the dv V − 0.007 ⋅ (TJ − 25) = THCOSS capacitance of QOFF is connected in parallel dt LIMIT R G,I ⋅ C GD 15
  16. 16. where VTH is the gate threshold at 25°C, -0.007 is voltage outputs of the power supplies instead ofthe temperature coefficient of VTH, RG,I is the rectifier diodes. They usually work with a veryinternal gate mesh resistance and CGD is the gate- limited drain-to-source voltage swing, therefore,to-drain capacitor. If the natural dv/dt limit of the their CDS and CGD capacitors exhibit relativelyMOSFET is lower than the maximum dv/dt of large capacitance values. Moreover, theirthe resonant circuit, either a different MOSFET application is unique because these devices areor a negative gate bias voltage must be operated in the fourth quadrant of their V-I plane.considered. If the result is favorable for the The current is flowing from the source toward thedevice, the maximum gate drive impedance can drain terminal. That makes the gate drive signalbe calculated by rearranging and solving the kind of irrelevant. If the circumstances, otherprevious equation according to: components around the synchronous switch VTH − 0.007 ⋅ (TJ − 25) ⎛ dt ⎞ require, current will flow in the device, eitherR MAX = ⋅⎜ ⎟ through the resistive channel or through the C GD ⎝ dv ⎠ MAX parasitic body diode of the MOSFET. The easiestwhere RMAX=RLO+RGATE+RG,I. model to examine the switching behavior of theOnce the maximum pull down resistor value is MOSFET synchronous rectifier is a simplifiedgiven, the gate drive design can be executed. It buck power stage where the rectifier diode isshould be taken into account that the driver’s pull replaced by the QSR transistor as shown in Figuredown impedance is also temperature dependent. 16.At elevated junction temperature the MOSFETbased gate drive ICs exhibit higher outputresistance than at 25°C where they are usually QFWcharacterized. V IL QSRTurn-off speed enhancement circuits can also beused to meet dv/dt immunity for the MOSFETsince they can shunt out RGATE at turn-off andduring the off state of the device. For instance,the simple pnp turn-off circuit of Figure 13 canboost the maximum dv/dt of the MOSFET. The Figure 16. Simplified synchronous rectificationequation modified by the effect of the beta of the modelpnp transistor yields the increased dv/dt rating of: The first thing to recognize in this circuit is that dv VTH − 0.007 ⋅ (TJ − 25) the operation of the synchronous rectifier = MOSFET depends on the operation of another dt ⎛ R + R LO ⎞ ⎜ R G,I + GATE ⎜ ⎟ ⋅ C GD ⎟ controlled switch in the circuit, namely the ⎝ β ⎠ forward switch, QFW. The two gate driveIn the dv/dt calculations a returning factor is the waveforms are not independent and specificinternal gate resistance of the MOSFET, which is timing criteria must be met. Overlapping gatenot defined in any data sheet. As pointed out drive signals would be fatal because the twoearlier, this resistance depends on the material MOSFETs would short circuit the voltage sourceproperties used to distribute the gate signal, the without any significant current limitingcell density, and the cell design within the component in the loop. Ideally, the two switchessemiconductor. would turn-on and off simultaneously to prevent the body diode of the QSR MOSFET to turn-on.SYNCHRONOUS RECTIFIER DRIVE Unfortunately, the window of opportunity toThe MOSFET synchronous rectifier is a special avoid body diode conduction is very narrow.case of ground referenced switches. These Very accurate, adaptive timing and fast switchingdevices are the same N-channel MOSFETs used speeds are required, which are usually out ofin traditional applications, but applied in low reach with traditional design techniques. 16
  17. 17. Consequently, in most cases a brief period – from through the driver output impedance. Before20ns to 80ns – of body diode conduction turn-on, while the drain-to-source voltageprecedes the turn-on and follows the turn-off of changes across the device, the Miller chargethe synchronous MOSFET switch. provided by the power stage must flow through the driver of the synchronous MOSFET causingGate charge additional power dissipation. This phenomenonDuring the body diode conduction period the full can be seen in Figure 17, which is part of the nextload current is established in the device and the discussion on dv/dt considerations.drain-to-source voltage equals the body diode The turn-off procedure of the synchronousforward voltage drop. Under these conditions the MOSFET obeys the same rules as the turn-onrequired gate charge to turn the device on or off procedure, therefore all the previousis different from the gate charge needed in considerations with respect to gate charge aretraditional first quadrant operation. When the applicable.gate is turned-on, the drain-to-source voltage ispractically zero and the CGD and CDS capacitors dv/dt considerationsare discharged. Also, the Miller effect is not Figure 17 shows the most important circuit andpresent, there is no feedback between the drain current components during the turn-on and turn-and gate terminals. Therefore, the required gate off procedures of QSR. Actually, it is morecharge equals the charge needed to raise the accurate to say that the switching actions takingvoltage across the gate-to-source and gate-to- place in QFW forces QSR to turn-on or offdrain capacitors from 0V to the final VDRV level. independently of its own gate drive signal.For an accurate estimate, the low voltage averagevalue of the CGD capacitor between 0V and VDRVhas to be determined according to: QFW VDS,SPEC ILC GD,SR = 2 ⋅ C RSS.SPEC ⋅ QSR 0.5 ⋅ VDRV V - RLO,SRThe following equation can then be used to +estimate the total gate charge of the synchronousMOSFET rectifier:Q Q,SR = (C GS + C GD,SR )⋅ VDRVThis value is appreciably lower than the total gate QFWcharge listed in the MOSFET data sheets. The QSR ILsame MOSFET with an identical driver circuit V RLO,SR +used for synchronous rectification can be turned -on or off quicker than if it would be driven in itsfirst quadrant operation. Unfortunately, thisadvantage can not be realized since the low Figure 17. Synchronous switching modelRDS(on) devices, applicable for synchronousrectification, usually have pretty large input and The turn-on of QSR starts with the turn-off ofoutput capacitances due to their large die size. QFW. When the gate drive signal of QFW transitions from high to low, the switching nodeAnother important note from driver power transitions from the input voltage level to GND.dissipation point of view is that the total gate The current stays in the forward switch until thecharge value from the data sheet should be CRSS capacitor is discharged and the body diodeconsidered. Although the gate charge delivered of QSR is forward biased. At that instant theby the driver during turn-on is less than the synchronous MOSFET takes over the currenttypical number listed in the data sheet, that flow and QFW turns off completely. After a shortcovers a portion of the total charge passing 17
  18. 18. delay dominated by the capabilities of the A typical example with logic level MOSFETscontroller, the gate drive signal of QSR is applied driven by a 10V drive signal would yield a ratioand the MOSFET is turned on. At that time the of 0.417, which means that the pull down drivecurrent transfers from the body diode to the impedance of QSR must be less than 42% of thechannel of the device. pull up drive impedance of QFW. When carryingAt the end of the conduction period of QSR the out these calculations, remember that everyMOSFET must be turned off. This procedure is parameter except VDRV is temperature dependentinitiated by removing the drive signal from the and their values might have to be adjusted togate of the synchronous switch. This event itself reflect the worst case operating conditions of thewill not cause the turn-off of the device. Instead, design.it will force the current to flow in the body diodeinstead of the channel. The operation of the HIGH SIDE NON-ISOLATED GATEcircuit is indifferent to this change. Current starts DRIVESto shift from QSR to QFW when the gate of the High side non-isolated gate drive circuits can beforward switch transitions from low to high. classified by the device type they are driving orOnce the full load current is taken over by QFW by the type of drive circuit involved.and the body diode is fully recovered, the Accordingly, they are differentiated whetherswitching node transitions from GND to the input P-channel or N-channel devices are used orvoltage level. During this transition the CRSS whether they implement direct drive, level shiftedcapacitor of QSR is charged and the synchronous drive, or bootstrap technique. Which ever way,MOSFET is susceptible to dv/dt induced turn-on. the design of high side drivers need moreSummarizing this unique operation of the attention and the following checklist might besynchronous MOSFET and its gate drive, the useful to cover all aspects of the design:most important conclusion is to recognize that • Efficiencyboth turn-on and turn-off dv/dt of the • Bias / power requirementssynchronous MOSFET is forced on the device bythe gate drive characteristics (i.e. the switching • Speed limitationsspeed) of the forward switch. Therefore, the two • Maximum duty-cycle limitgate drive circuits should be designed together to • dv/dt implicationsensure that their respective speed and dv/dt limitmatches under all operating conditions. This can • Start-up conditionsbe ensured by adhering to the steps of the • Transient operationfollowing simple calculations: • Bypass capacitor size dv VDRV − VGS,PLATEAU(FW ) • Layout, grounding considerations = dt TURN−ON(FW) (R HI(FW) + R GATE(FW) + R G,I(FW)) ⋅ CRSS(FW) High side drivers for P-channel devicesdv VTH(SR) In this group of circuits the source terminal of the =dt MAX(SR) (R LO(SR) + R GATE(SR) + R G,I(SR) ) ⋅ CRSS(SR) P-channel MOSFET switch is connected to the positive input rail. The driver applies a negative dv dv < amplitude turn-on signal to the gate with respect dt TURN−ON(FW) dt MAX(SR) to the source of the device. This means that theAssuming the same devices for QSR and QFW, no output of the PWM controller has to be invertedexternal gate resistors, and that the internal gate and referenced to the positive input rail. Becauseresistance is negligible compared to the drivers the input voltage can be considered as a DCoutput impedance, the ratio of the driver output voltage source, high side P-channel drivers doimpedances can be approximated by: not have to swing between large potential R LO(SR) VTH(SR) differences on the switching frequency basis, but ≤ they must work over the entire input voltage R HI(FW) VDRV − VGS,PLATEAU(FW ) 18
  19. 19. range. Moreover, the driver is referenced to anAC ground potential due to the low AC VDRV VINimpedance of the input voltage source. VCCP-channel direct drive ROFF DriverThe easiest case of P-channel high side drivers is RGATEdirect drive, which can be implemented if the OUTmaximum input voltage is less then the gate-to- OCsource breakdown voltage of the device. Atypical application area is 12V input DC/DC GNDconverters using a P-channel MOSFET, similarto the schematic in Figure 18. Note the invertedPWM output signal is readily available in some Figure 19. Open collector drive for PMOS devicededicated controllers for P-channel devices. Problems are numerous with this implementation starting with the limited input voltage range due VDRV=VIN to the voltage rating of the open collector transistor. But the most inhibiting obstacle is the VCC high drive impedance. Both resistors, ROFF and PWM RGATE must be a high value resistor to limit the controller continuous current in the driver during the RGATE conduction period of the switch. Furthermore, the OUT gate drive amplitude depends on the resistor divider ratio and the input voltage level. Switching speed and dv/dt immunity are severely GND limited which excludes this circuit from switching applications. Nevertheless, this very simple level shift interface can be used for Figure 18. Direct drive for P-channel MOSFET driving switches in inrush current limiters orThe operation of the circuit is similar to the similar applications where speed is not anground referenced direct driver for N-channel important consideration.devices. The significant difference is the path of Figure 20 shows a level shifted gate drive circuitthe gate drive current, which never flows in the which is suitable for high speed applications andground connections. Instead, the high charge and works seamlessly with regular PWM controllers.discharge currents of the gate are conducted by The open collector level shift principle can bethe positive rail interconnection. Consequently, to easily recognized at the input of a bipolar totem-minimize the loop inductance in the gate drive, pole driver stage. The level shifter serves twowide traces or a plane is desirable for the positive purposes in this implementation; it inverts theinput. PWM output and references the PWM signal to the input rail.P-channel level shifted drive The turn-on speed is fast, defined by RGATE andFor input voltages exceeding the gate-to-source R2. During the on-time of the switch a small DCvoltage limit of the MOSFET, level shifted gate current flows in the level shifter keeping thedrive circuits are necessary. The simplest level driver biased in the right state. Both the gateshift technique is using an open collector driver drive power and the level shift current areas shown in Figure 19. Unfortunately, open provided by the positive input of the power stagecollector level shifters are not suitable for driving which is usually well bypassed.MOSFETs directly in a high speed application. 19
  20. 20. dv/dt induced turn-on during the off state of the VIN P-channel MOSFET transistor. VBIAS In general, the DC level shift drivers have relatively low efficiency and are power R1 VCC dissipation limited above a certain input voltage RGATE PWM level. The fundamental trade-off is to balance the R2 controller switching speed and the power consumption of OUT QINV the level shifter to meet all requirements under RB the entire input voltage range. High side direct drivers for N-channel devices GND The majority of power supply applications utilize N-channel MOSFETs as the main power switch Figure 20. Level shifted P-channel MOSFET because of their lower price, higher speed and driver lower on-resistance. Using N-channel devices as a high side switch necessitates a gate drive circuitThe power consumption of the driver has a which is referenced to the source of thefrequency dependent portion based on the gate MOSFET. The driver must tolerate the violentcharge of the main switch and a duty-cycle and voltage swings occurring during the switchinginput voltage dependent portion due to the transitions and drive the gate of the MOSFETcurrent flowing in the level shifter. above the positive supply rail of the power V ⋅D supply. In most cases, the gate drive voltage must PDRIVE = Q G ⋅ VDRV ⋅ f DRV + IN MAX R1 + R2 be above the highest DC potential available in theOne of the drawbacks of this circuit is that VDRV circuit. All these difficulties make the high sideis still a function of the input voltage due to the driver design a challenging task.R1, R2 divider. In most cases protection circuits High side direct drive for N-channel MOSFETmight be needed to prevent excessive voltageacross the gate-to-source terminals. Another In the easiest high side applications the MOSFETpotential difficulty is the saturation of the npn can be driven directly by the PWM controller orlevel shift transistor, which can extend the turn- by a ground referenced driver. Two conditionsoff time otherwise defined by R1 and RGATE. must be met for this application:Fortunately both of these shortcomings can be VDRV < VGS,MAXaddressed by moving R2 between the emitter of VIN < VDRV − VGS,MillerQINV and GND. The resulting circuit providesconstant gate drive amplitude and fast, A typical application schematic is illustrated insymmetrical switching speed during turn-on and Figure 21 with an optional pnp turn-off circuit.turn-off. The dv/dt immunity of the driver VDRV VINscheme is primarily set by the R1 resistor. A Optionallower value resistor will improve the immunityagainst dv/dt induced turn-on but also increases VCC PWMthe power losses of the level shifter. Also, notice controller RGATEthat this solution has a built in self-biasing OUTmechanism during power up. While the PWMcontroller is still inactive, QINV is off and the gateof the main MOSFET is held below its threshold GNDby R1 and the upper npn transistor of the totem-pole driver. Pay specific attention to rapid inputvoltage transients though as they could cause Figure 21. Direct drive of N-channel MOSFET 20

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